UC3843AD1013TR

UC284XA UC384XA HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER NOT FOR NEW DESIGN 1 ■ ■ ■ ■ ■ ■ FEATURES TRIMMED OSCILLATOR DISCHARGE CURRENT CURRENT MODE OPERATION TO 500kHz AUTOMATIC FEED FORWARD COMPENSATION LATCHING PWM FOR CYCLE-BY-CYCLE CURRENT LIMITING INTERNALLY TRIMMED REFERENCE WITH UNDERVOLTAGE LOCKOUT HIGH CURRENT TOTEM POLE OUTPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LOW START-UP CURRENT (< 0.5mA) DOUBLE PULSE SUPPRESSION Figure 1. Package DIP-8 SO-8 Table 1. Order Codes Part Number 2 DESCRIPTION The UC384xA family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off-state. Package UC2842AD1; UC3842AD1; UC2843AD1; UC3843AD1; UC2844AD1; UC3844AD1; UC2845AD1; UC3845AD1 SO-8 UC2842AN; UC3842AN; UC2843AN; UC3843AN; UC2844AN; UC3844AN; UC2845AN; UC3845AN DIP-8 Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842A and UC3844A have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line applications The corresponding thresholds for the UC3843A and UC3845A are 8.5 V and 7.9V. The UC3842A and UC3843A can operate to duty cycles approaching 100%. A range of the zero to < 50 % is obtained by the UC3844A and UC3845A by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. Figure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A) Vi 7 UVLO 34V GROUND S/R 5 8 5V REF INTERNAL BIAS 2.50V VREF GOOD LOGIC RT/CT VFB COMP CURRENT SENSE 4 2 1 3 6 OSC + - ERROR AMP. VREF 5V 50mA OUTPUT T 2R R S 1V R PWM LATCH CURRENT SENSE COMPARATOR D95IN331 May 2004 REV. 5 1/16 UC384XA - UC284XA Table 2. Absolute Maximum Ratings Symbol Parameter Vi Supply Voltage (low impedance source) Value Unit 30 V Vi Supply Voltage (Ii < 30mA) IO Output Current ±1 A EO Output Energy (capacitive load) 5 µJ Self Limiting Analog Inputs (pins 2, 3) Error Amplifier Output Sink Current – 0.3 to 5.5 V 10 mA Ptot Power Dissipation at Tamb ≤ 25 °C (DIP-8) 1.25 W Ptot Power Dissipation at Tamb ≤ 25 °C (SO-8) 800 mW Tstg Storage Temperature Range – 65 to 150 °C TJ Junction Operating Temperature – 40 to 150 °C TL Lead Temperature (soldering 10s) 300 °C * All voltages are with respect to pin 5, all currents are positive into the specified terminal. Figure 3. DIP-8/SO-8 Pin Connection (Top view) COMP 1 8 VREF VFB 2 7 Vi ISENSE 3 6 OUTPUT RT/CT 4 5 GROUND D95IN332 Table 3. Pin Description N° Pin 1 COMP 2 VFB 3 ISENSE A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. 4 RT/CT The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible. 5 GROUND This pin is the combined control circuitry and power ground. 6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. 7 VCC This pin is the positive supply of the control IC. 8 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT. 2/16 Function This pin is the Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. UC384XA - UC284XA Table 4. Thermal Data Symbol Parameter Rth j-amb Thermal Resistance Junction-ambient Max. DIP-8 SO-8 Unit 100 150 °C/W Table 5. Electrical Characteristcs ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA; 0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF) Symbol Parameter Test Condition UC284XA UC384XA Min. Typ. Max. Min. Typ. Max. 4.95 4.90 Unit REFERENCE SECTION VREF Output Voltage Tj = 25°C Io= 1mA 5.00 5.05 5.00 5.10 V ∆VREF Line Regulation 12V ≤ Vi ≤ 25V 2 20 2 20 mV ∆VREF Load Regulation 1 ≤ Io ≤ 20mA 3 25 3 25 mV ∆VREF/∆T Temperature Stability eN (Note 2) Total Output Variation Line, Load, Temperature Output Noise Voltage 10Hz ≤ f ≤ 10KHz Tj = 25°C (note 2) Long Term Stability Tamb 0.2 4.9 0.2 5.1 4.82 50 25 -30 -100 -180 Tj = 25°C 47 52 VCC = 12V to 25V – 0.2 V µV 50 5 = 125°C, 1000Hrs mV/°C 5.18 5 25 mV -30 -100 -180 mA 57 47 52 57 KHz 1 – 0.2 1 % (note 2) ISC Output Short Circuit OSCILLATOR SECTION fOSC Frequency ∆fOSC/∆V Frequency Change with Volt. ∆VREF/∆T Frequency Change with Temp. TA = Tlow to Thigh – 5 – – 5 – % VOSC Oscillator Voltage Swing (peak to peak) – 1.6 – – 1.6 – V Idischg Discharge Current (VOSC =2V) TJ = 25°C 7.8 8.3 8.8 7.8 8.3 8.8 mA VPIN1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V -0.1 -1 -0.1 -2 µA ERROR AMP SECTION V2 Ib Input Voltage Input Bias Current VFB = 5V AVOL 2V ≤ Vo ≤ 4V 65 90 65 90 dB Unity Gain Bandwidth TJ = 25°C 0.7 1 0.7 1 MHz Power Supply Rejec. Ratio 12V ≤ Vi ≤ 25V 60 70 60 70 dB Io Output Sink Current VPIN2 = 2.7V VPIN1= 1.1V 2 12 2 12 mA Io Output Source Current VPIN2 = 2.3V VPIN1 = 5V -0.5 -1 -0.5 -1 mA VOUT High VPIN2 = 2.3V;RL = 15KΩ to Ground 5 6.2 5 6.2 V VOUT Low VPIN2 = 2.7V;RL = 15KΩ to Pin 8 BW PSRR 0.8 1.1 0.8 1.1 V CURRENT SENSE SECTION GV Gain (note 3 & 4) 2.85 3 3.15 2.85 3 3.15 V/V V3 Maximum Input Signal VPIN1 = 5V (note 3) 0.9 1 1.1 0.9 1 1.1 V Supply Voltage Rejection 12 ≤ Vi ≤ 25V (note 3) SVR Ib Input Bias Current Delay to Output 70 70 dB -2 -10 -2 -10 µA 150 300 150 300 ns 3/16 UC384XA - UC284XA Table 5. Electrical Characteristcs (continued) ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA; 0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF) Symbol Parameter Test Condition UC284XA Min. UC384XA Typ. Max. ISINK = 20mA 0.1 ISINK = 200mA 1.6 Min. Unit Typ. Max. 0.4 0.1 0.4 V 2.2 1.6 2.2 V OUTPUT SECTION VOL Output Low Level VOH Output High Level VOLS UVLO Saturation VCC = 6V; I SINK = 1mA 0.7 1.2 0.7 1.2 V Rise Time Tj = 25°C 50 150 50 150 ns 50 150 50 150 ns tr ISOURCE = 20mA 13 13.5 ISOURCE = 200mA 12 13.5 13 13.5 12 13.5 V V CL = 1nF (2) tf Fall Time Tj = 25°C CL = 1nF (2) UNDER-VOLTAGE LOCKOUT SECTION Start Threshold Min Operating Voltage After Turn-on X842A/4A 15 16 17 14.5 16 17.5 V X843A/5A 7.8 8.4 9.0 7.8 8.4 9.0 V X842A/4A 9 10 11 8.5 10 11.5 V X842A/3A 94 96 100 94 96 100 % X844A/5A 47 48 50 47 48 50 % 0 % PWM SECTION Maximum Duty Cycle Minimum Duty Cycle 0 TOTAL STANDBY CURRENT Ist Ii Viz Start-up Current Vi = 6.5V for UCX843A/ 45A 0.3 0.5 0.3 0.5 mA Vi = 14V for UCX842A/44A 0.3 0.5 0.3 0.5 mA 12 17 12 17 mA Operating Supply Current VPIN2 = VPIN3 = 0V Zener Voltage Ii = 25mA 30 36 30 36 V Notes: 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to Tamb as possible. 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2 = 0. 4. Gain defined as : A = ∆VPIN1/∆VPIN3; 0 ≤ VPIN3 ≤ 0.8V 5. Adjust Vi above the start threshold before setting at 15 V. 4/16 UC384XA - UC284XA Figure 4. Open Loop Test Circuit. VREF 4.7KΩ RT 2N2222 100KΩ ERROR AMP. ADJUST 4.7KΩ A VREF COMP VFB 1KΩ ISENSE ISENSE ADJUST 5KΩ RT/CT 1 Vi 0.1µF 8 7 2 Vi 1W 1KΩ 0.1µF 3 6 4 5 OUTPUT OUTPUT GROUND CT GROUND D95IN343 High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 KΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Figure 5. Oscillator Frequency vs Timing Resistance fo (Hz) D96IN362 Figure 7. Oscillator Discharge Current vs. Temperature. Idischg (mA) D95IN335 Vi=15V VOSC=2V 8.5 1M CT =4 1nF 2.2 100K 70 pF 8.0 nF 4.7 nF 7.5 10K 7.0 1K 300 1K 3K 10K 30K Figure 6. Maximum Duty Cycle vs Timing Resistor fo (Hz) -55 RT(Ω) D96IN363 -25 0 25 50 75 100 TA(˚C) Figure 8. Error Amp Open-Loop Gain and Phase vs. Frequency. D95IN337 (dB) Vi=15V VO=2V to 4V RL=100K TA=25˚C 80 80 Gain 60 φ 30 60 60 40 Phase 90 40 20 0 300 1K 3K 10K 30K RT(Ω) 20 120 0 150 -20 10 100 1K 10K 100K 1M 180 f(Hz) 5/16 UC384XA - UC284XA Figure 9. Current Sense Input Threshold vs. Error Amp Output Voltage. Vth (V) Figure 12. Output Saturation Voltage vs. Load Current. Vsat (V) D95IN338 D95IN341 Vi=15V Vi -1 1.0 TA=25˚C -2 0.8 Source Saturation (Load to Ground) TA=25˚C TA=-40˚C Vi=15V 80µs Pulsed Load 120Hz Rate TA=125˚C 0.6 3 0.4 TA=-40˚C 2 TA=25˚C TA=-40˚C 0.2 1 0.0 0 0 2 4 6 VO(V) Figure 10. Reference Voltage Change vs. Source Current.. D95IN339 60 Sink Saturation (Load to Vi) 0 200 400 GND 600 IO(mA) Figure 13. Supply Current vs. Supply Voltage. Ii (mA) D95IN342 Vi=15V 50 20 TA=-40˚C 40 15 TA=125˚C 10 5 10 0 0 20 40 60 80 100 Iref(mA) Figure 11. Reference Short Circuit Current vs. Temperature.. D95IN340 ISC (mA) Vi=15V RL≤0.1Ω 100 90 80 70 60 50 -55 6/16 -25 0 25 50 75 100 TA(˚C) 0 0 RT=10K CT=3.3nF VFB=0V ISense=0V TA=25˚C UCX842/44 20 UCX843/45 TA=25˚C 30 10 20 30 Vi(V) UC384XA - UC284XA Figure 14. Output Waveform. Figure 15. Output Cross Conduction Figure 16. Oscillator and Output Waveforms. Vi 7 8 CT 5V REG OUTPUT PWM 6 RT OUTPUT LARGE RT/SMALL CT CLOCK 4 OSCILLATOR CT ID CT OUTPUT 5 SMALL RT/LARGE CT GND D95IN344 Figure 17. Error Amp Configuration. 2.5V 1mA + Zi VFB 2 COMP 1 - Zf D95IN345 7/16 UC384XA - UC284XA Figure 18. Under Voltage Lockout. 7 Vi ON/OFF COMMAND TO REST OF IC ICC UC3842A UC3843A UC3844A UC3845A VON 16V 8.4V VOFF 10V 7.6V