UPSD3234A-40T6

UPSD3234A, UPSD3234BV UPSD3233B, UPSD3233BV Flash programmable system devices with 8032 MCU and 64 Kbit SRAM Features ■ Fast 8-bit 8032 MCU – 40 MHz at 5.0 V, 24 MHz at 3.3 V – Core, 12-clocks per instruction ■ Dual Flash memories with memory management – Place either memory into 8032 program address space or data address space – Read-while-write operation for inapplication programming and EEPROM emulation – Single voltage program and erase – 100,000 minimum erase cycles, 15-year retention LQFP52 (T) 52-lead, thin, quad flat package ■ Clock, reset, and supply management – Normal, idle, and power down modes – Power-on and low voltage reset supervisor – Programmable watchdog timer ■ Programmable logic, general-purpose – 16 macrocells – Implements state machines, glue-logic, etc. ■ Timers and interrupts – Three 8032 standard 16-bit timers – 10 Interrupt sources with two external interrupt pins Table 1. LQFP80 (U) 80-lead, thin, quad flat package ■ A/D converter – Four channels, 8-bit resolution, 10 µs ■ Communication interfaces – USB v1.1, low-speed 1.5 Mbps, 3 endpoints – I2C master/slave bus controller – Two UARTs with independent baud rate – Six I/O ports with up to 46 I/O pins – 8032 address/data bus available on TQFP80 package – 5 PWM outputs, 8-bit resolution ■ JTAG in-system programming – Program the entire device in as little as 10 seconds ■ Single supply voltage – 4.5 to 5.5 V – 3.0 to 3.6 V ■ ECOPACK® packages Device summary Order code UPSD3233B-40T6 Max. clock 1st 2nd 8032 SRAM GPIO USB VCC (V) (MHz) Flash Flash bus 40 128 KB 32 KB 8 KB 37 No No Pkg. Temp. 4.5-5.5 TQFP52 –40°C to 85°C UPSD3233BV-24T6 24 128 KB 32 KB 8 KB 37 No No 3.0-3.6 TQFP52 –40°C to 85°C UPSD3233B-40U6 40 128 KB 32 KB 8 KB 46 No Yes 4.5-5.5 TQFP80 –40°C to 85°C UPSD3233BV-24U6 24 128 KB 32 KB 8 KB 46 No Yes 3.0-3.6 TQFP80 –40°C to 85°C UPSD3234A-40T6 40 256 KB 32 KB 8 KB 37 Yes No 4.5-5.5 TQFP52 –40°C to 85°C UPSD3234A-40U6 40 256 KB 32 KB 8 KB 46 Yes Yes 4.5-5.5 TQFP80 –40°C to 85°C UPSD3234BV-24U6 24 256 KB 32 KB 8 KB 46 No Yes 3.0-3.6 TQFP80 –40°C to 85°C January 2009 Rev 5 1/189 www.st.com 1 Contents UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Contents 1 UPSD323xx description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 2 Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.2 B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.3 Stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.4 Program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.5 Program status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.6 Registers R0~R7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.7 Data pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.5 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6 XRAM-DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.7 XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.8 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9 Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.9.1 Direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.9.2 Indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.9.3 Register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.9.4 Register-specific addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.9.5 Immediate constants addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.9.6 Indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.10 Arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.11 Logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.12 Data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.13 2/189 52-pin package I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.12.1 Internal RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.12.2 External RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.12.3 Lookup tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Boolean instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Contents 2.14 Relative offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.15 Jump instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.16 Machine cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3 UPSD323xx hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 MCU module description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 5 6 7 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.1 External Int0 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2 Timer 0 and 1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3 Timer 2 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4 I2C interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.5 External Int1 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.6 DDC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.7 USB interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.8 USART interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.9 Interrupt priority structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.10 Interrupt enable structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.11 How interrupts are handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Power-saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3 Power control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.4 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.5 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O ports (MCU module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1 Port type and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9 Supervisory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3/189 Contents UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 9.1 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2 Low VDD voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.3 Watchdog timer overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.4 USB reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11 Timer/counters (Timer 0, Timer 1 and Timer 2) . . . . . . . . . . . . . . . . . . 59 11.1 11.2 12 13 15 4/189 11.1.1 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.1.2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.1.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.1.4 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Standard serial interface (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.1 Multiprocessor communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.2 Serial port control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.2.1 Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.2.2 Using Timer 1 to generate baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.2.3 Using Timer/counter 2 to generate baud rates . . . . . . . . . . . . . . . . . . . 68 12.2.4 More about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.2.5 More about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.2.6 More about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Analog-to-digital convertor (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.1 14 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ADC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Pulse width modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 14.1 4-channel PWM unit (PWM 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 14.2 Programmable period 8-bit PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 14.3 PWM 4-channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 15.1 Serial status register (SxSTA: S1STA, S2STA) . . . . . . . . . . . . . . . . . . . . 86 15.2 Data shift register (SxDAT: S1DAT, S2DAT) . . . . . . . . . . . . . . . . . . . . . . . 86 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 15.3 16 18 Address register (SxADR: S1ADR, S2ADR) . . . . . . . . . . . . . . . . . . . . . . 87 DDC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 16.1 17 Contents Special Function register for the DDC interface . . . . . . . . . . . . . . . . . . . . 89 16.1.1 DDCDAT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16.1.2 DDCADR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16.2 Host type detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 16.3 DDC1 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 16.4 DDC2B protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 USB hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 17.1 USB related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 17.2 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 17.2.1 USB physical layer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 17.2.2 Low speed driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 17.3 Receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 17.4 External USB pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 PSD module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 18.1 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 18.2 In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 19 Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 20 PSD module register description and address offset . . . . . . . . . . . . 110 21 PSD module detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 22 Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 22.1 Primary Flash memory and secondary Flash memory description . . . . 112 22.2 Memory block select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 22.2.1 Ready/Busy (PC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 22.2.2 Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 22.3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 22.4 Power-down instruction and Power-up mode . . . . . . . . . . . . . . . . . . . . . 115 22.4.1 Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5/189 Contents UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 22.5 22.6 22.7 22.8 22.9 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 22.5.1 Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 22.5.2 Read memory sector protection status . . . . . . . . . . . . . . . . . . . . . . . . 115 22.5.3 Reading the Erase/Program status bits . . . . . . . . . . . . . . . . . . . . . . . . 115 22.5.4 Data polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 22.5.5 Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 22.5.6 Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 22.5.7 Erase time-out flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 22.6.1 Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 22.6.2 Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 22.6.3 Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 22.7.1 Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 22.7.2 Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 22.7.3 Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 22.7.4 Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 22.8.1 Flash memory sector protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 22.8.2 Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 22.8.3 Reset (RESET) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 22.10 Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 22.10.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 22.10.2 Memory Select configuration in Program and Data spaces . . . . . . . . . 123 22.10.3 Separate Space mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 22.10.4 Combined Space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 22.11 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 23 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 23.1 Turbo bit in PSD module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 23.2 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 23.3 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 23.4 Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 23.5 Product term allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 23.5.1 6/189 Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . 132 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 23.6 24 Contents 23.5.2 OMC mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 23.5.3 Output enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 I/O ports (PSD module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 24.1 General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 24.2 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 24.3 MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 24.4 PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 24.5 Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 24.6 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 24.7 JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 24.8 Port configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 24.9 24.8.1 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 24.8.2 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 24.8.3 Drive Select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 24.9.1 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 24.9.2 Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 24.9.3 Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 24.9.4 OMC mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 24.9.5 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 24.9.6 Enable out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 24.10 Ports A and B – functionality and structure . . . . . . . . . . . . . . . . . . . . . . 141 24.11 Port C – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 24.12 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 24.13 External chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 25 26 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 25.1 PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 25.2 PSD chip select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 25.3 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 25.4 Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 RESET timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . 150 7/189 Contents 27 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 26.1 Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 26.2 I/O pin, register and PLD status at RESET . . . . . . . . . . . . . . . . . . . . . . 150 26.3 Reset of Flash Memory Erase and Program Cycles . . . . . . . . . . . . . . . 150 Programming in-circuit using the JTAG serial interface . . . . . . . . . . 152 27.1 Standard JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 27.2 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 27.3 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . 153 28 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 29 AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 30 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 31 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 31.1 31.2 31.3 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . 159 31.1.1 ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 31.1.2 FTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 159 31.2.1 Software recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 31.2.2 Prequalification trials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . . 160 31.3.1 Electro-static discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 31.3.2 Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 31.3.3 Dynamic latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 32 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 33 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 34 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 8/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 1 UPSD323xx description UPSD323xx description The UPSD323xx Series combines a fast 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix including USB, to form an ideal embedded controller. At its core is an industry-standard 8032 MCU operating up to 40MHz. A JTAG serial interface is used for In-System Programming (ISP) in as little as 10 seconds, perfect for manufacturing and lab development. The USB 1.1 low-speed interface has one Control endpoint and two Interrupt endpoints suitable for HID class drivers. The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize the 8032 memory structure, offering two independent banks of Flash memory that can be placed at virtually any address within 8032 program or data address space, and easily paged beyond 64 Kbytes using on-chip programmable decode logic. Dual Flash memory banks provide a robust solution for remote product updates in the field through In-Application Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating the need for external EEPROM chips. General purpose programmable logic (PLD) is included to build an endless variety of gluelogic, saving external logic devices. The PLD is configured using the software development tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge. The UPSD323xx also includes supervisor functions such as a programmable watchdog timer and low-voltage reset. In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 9/189 UPSD323xx description Figure 1. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV UPSD323xx block diagram uPSD323x (3) 16-bit Timer/ Counters 8032 MCU Core (2) External Interrupts P3.0:7 1st Flash Memory: 128K or 256K Bytes Programmable Decode and Page Logic I2C 2nd Flash Memory: 32K Bytes SRAM: 8K Bytes (8) GPIO, Port 3 P1.0:7 (8) GPIO, Port 1 (4) 8-bit ADC SYSTEM BUS UART0 General Purpose Programmable Logic, 16 Macrocells (8) GPIO, Port A (80-pin only) PA0:7 (8) GPIO, Port B PB0:7 (2) GPIO, Port D PD1:2 (4) GPIO, Port C PC0:7 UART1 JTAG ISP (5) 8-bit PWM 8032 Address/Data/Control Bus (80-pin device only) P4.0:7 (8) GPIO, Port 4 Supervisor: Watchdog and Low-Voltage Reset USB+, USB– USB v1.1 VCC, VDD, GND, Reset, Crystal In MCU Bus Dedicated Pins AI10429 10/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 40 P1.6/ADC2 41 P1.7/ADC3 42 PB7 43 PB6 44 RESET_ 45 GND 46 VREF 47 PB5 48 PB4 49 PB3 50 PB2 51 PB1 TQFP52 connections 52 PB0 Figure 2. UPSD323xx description PD1/CLKIN 1 39 P1.5/ADC1 PC7 2 38 P1.4/ADC0 JTAG TDO 3 37 P1.3/TXD1 JTAG TDI 4 USB–(1) 5 36 P1.2/RXD1 35 P1.1/T2X PC4/TERR_ 6 34 P1.0/T2 USB+ 7 VCC 8 33 VCC 32 XTAL2 GND 9 31 XTAL1 PC3/TSTAT 10 30 P3.7/SCL1 PC2/VSTBY 11 JTAG TCK 12 29 P3.6/SDA1 28 P3.5/T1 JTAG TMS 13 P3.3/EXINT1 26 P3.2/EXINT0 25 P3.1/TXD 24 P3.0/RXD 23 P4.0/DDC SDA 22 P4.1/DDC SCL 21 P4.2/DDC VSYNC 20 GND 19 P4.3/PWM0 18 P4.4/PWM1 17 P4.5/PWM2 16 P4.6/PWM3 15 P4.7/PWM4 14 27 P3.4/T0 AI07423b 1. Pull-up resistor required on pin 5 (2 kΩ for 3 V devices, 7.5 kΩ for 5 V devices) for all 52-pin devices, with or without USB function. 11/189 UPSD323xx description 61 P1.6/ADC2 62 WR_ 63 PSEN_ 64 P1.7/ADC3 65 RD_ 66 PB7 67 PB6 68 RESET_ 69 GND 70 VREF 72 PB5 71 NC(2) 73 PB4 74 PB3 75 P3.0/RXD0 76 PB2 77 P3.1/TXD0 78 PB1 79 P3.2/EXINT0 TQFP80 connections 80 PB0 Figure 3. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PD2 1 60 P1.5/ADC1 P3.3 /EXINT1 2 59 P1.4/ADC0 PD1/CLKIN 3 58 P1.3/TXD1 ALE 4 57 A11 PC7 5 56 P1.2/RXD1 JTAG/TDO 6 55 A10 JTAG/TDI 7 USB–(1) 8 54 P1.1/TX2 53 A9 PC4/TERR_ 9 52 P1.0/T2 USB+ 10 NC(2) 11 51 A8 50 VCC 49 XTAL2 VCC 12 GND 13 48 XTAL1 PC3/TSTAT 14 47 AD7 PC2/VSTBY 15 JTAG TCK 16 NC(2) 17 46 P3.7/SCL1 P4.7/PWM4 18 43 AD5 P4.6/PWM3 19 42 P3.5/T1 45 AD6 44 P3.6/SDA1 JTAG TMS 20 P3.4/T0 40 AD3 39 AD2 38 AD1 37 AD0 36 PA0 35 PA1 34 P4.0/DDC SDA 33 PA2 32 P4.1/DDC SCL 31 P4.2/DDC VSYNC 30 GND 29 PA3 28 P4.3/PWM0 27 PA4 26 P4.4/PWM1 25 PA5 24 P4.5/PWM2 23 PA6 22 PA7 21 41 AD4 AI07424b 1. Pull-up resistor required on pin 8 (2 kΩ for 3 V devices, 7.5 kΩ for 5 V devices) for all 82-pin devices, with or without USB function. 2. NC = Not Connected Table 2. Port pin 12/189 80-pin package pin description Function Signal name Pin no. In/ out AD0 36 I/O External Bus: Multiplexed Address/Data bus A1/D1 AD1 37 I/O Multiplexed Address/Data bus A0/D0 AD2 38 I/O Multiplexed Address/Data bus A2/D2 AD3 39 I/O Multiplexed Address/Data bus A3/D3 AD4 41 I/O Multiplexed Address/Data bus A4/D4 AD5 43 I/O Multiplexed Address/Data bus A5/D5 AD6 45 I/O Multiplexed Address/Data bus A6/D6 Basic Alternate UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 2. Port pin UPSD323xx description 80-pin package pin description (continued) Function Signal name Pin no. In/ out AD7 47 I/O Multiplexed Address/Data bus A7/D7 P1.0 T2 52 I/O General I/O port pin Timer 2 Count input P1.1 TX2 54 I/O General I/O port pin Timer 2 Trigger input P1.2 RxD1 56 I/O General I/O port pin 2nd UART Receive P1.3 TxD1 58 I/O General I/O port pin 2nd UART Transmit P1.4 ADC0 59 I/O General I/O port pin ADC Channel 0 input P1.5 ADC1 60 I/O General I/O port pin ADC Channel 1 input P1.6 ADC2 61 I/O General I/O port pin ADC Channel 2 input P1.7 ADC3 64 I/O General I/O port pin ADC Channel 3 input A8 51 O External Bus, Address A8 A9 53 O External Bus, Address A9 A10 55 O External Bus, Address A10 A11 57 O External Bus, Address A11 P3.0 RxD0 75 I/O General I/O port pin UART Receive P3.1 TxD0 77 I/O General I/O port pin UART Transmit P3.2 EXINT0 79 I/O General I/O port pin Interrupt 0 input / Timer 0 gate control P3.3 EXINT1 2 I/O General I/O port pin Interrupt 1 input / Timer 1 gate control P3.4 T0 40 I/O General I/O port pin Counter 0 input P3.5 T1 42 I/O General I/O port pin Counter 1 input P3.6 SDA1 44 I/O General I/O port pin I2C Bus serial data I/O P3.7 SCL1 46 I/O General I/O port pin I2C Bus clock I/O P4.0 DDC SDA 33 I/O General I/O port pin P4.1 DDC SCL 31 I/O General I/O port pin P4.2 DDC VSYNC 30 I/O General I/O port pin P4.3 PWM0 27 I/O General I/O port pin 8-bit Pulse Width Modulation output 0 P4.4 PWM1 25 I/O General I/O port pin 8-bit Pulse Width Modulation output 1 P4.5 PWM2 23 I/O General I/O port pin 8-bit Pulse Width Modulation output 2 P4.6 PWM3 19 I/O General I/O port pin 8-bit Pulse Width Modulation output 3 Basic Alternate 13/189 UPSD323xx description Table 2. 14/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 80-pin package pin description (continued) Function Port pin Signal name Pin no. In/ out P4.7 PWM4 18 I/O General I/O port pin USB– 8 I/O Pull-up resistor required (2 kΩ for 3 V devices, 7.5 kΩ for 5 V devices) VREF 70 O Reference Voltage input for ADC RD_ 65 O READ signal, external bus WR_ 62 O WRITE signal, external bus PSEN_ 63 O PSEN signal, external bus ALE 4 O Address Latch signal, external bus RESET_ 68 I Active low RESET input XTAL1 48 I Oscillator input pin for system clock XTAL2 49 O Oscillator output pin for system clock PA0 35 I/O General I/O port pin PA1 34 I/O General I/O port pin PA2 32 I/O General I/O port pin PA3 28 I/O General I/O port pin PA4 26 I/O General I/O port pin PA5 24 I/O General I/O port pin PA6 22 I/O General I/O port pin PA7 21 I/O General I/O port pin PB0 80 I/O General I/O port pin PB1 78 I/O General I/O port pin PB2 76 I/O General I/O port pin PB3 74 I/O General I/O port pin PB4 73 I/O General I/O port pin PB5 72 I/O General I/O port pin PB6 67 I/O General I/O port pin PB7 66 I/O General I/O port pin Basic Alternate Programmable 8-bit Pulse Width modulation output 4 PLD macrocell outputs PLD inputs Latched address out (A0A7) Peripheral I/O mode PLD macrocell outputs PLD inputs Latched address out (A0A7) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 2. Port pin 80-pin package pin description (continued) Function Signal name Pin no. In/ out JTAG TMS 20 I JTAG pin JTAG TCK 16 I JTAG pin PC3 TSTAT 14 I/O General I/O port pin PC4 TERR_ 9 I/O General I/O port pin JTAG TDI 7 I JTAG pin JTAG TDO 6 O JTAG pin 5 I/O General I/O port pin 3 I/O General I/O port pin PLD I/O Clock input to PLD and APD PD2 1 I/O General I/O port pin PLD I/O Chip select to PSD module Vcc 12 Vcc 50 GND 13 GND 29 GND 69 PC7 PD1 CLKIN USB+ 1.1 UPSD323xx description Basic Alternate PLD macrocell outputs PLD inputs JTAG pins are dedicated pins 10 NC 11 NC 17 NC 71 52-pin package I/O port The 52-pin package members of the UPSD323xx devices have the same port pins as those of the 80-pin package except: ● Port 0 (P0.0-P0.7, external address/data bus AD0-AD7) ● Port 2 (P2.0-P2.3, external address bus A8-A11) ● Port A (PA0-PA7) ● Port D (PD2) ● Bus control signal (RD,WR,PSEN,ALE) ● Pin 5 requires a pull-up resistor (2 kΩ for 3 V devices, 7.5 kΩ for 5 V devices) for all devices, with or without USB function. 15/189 Architecture overview UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2 Architecture overview 2.1 Memory organization The UPSD323xx devices’ standard 8032 Core has separate 64-Kbyte address spaces for Program memory and Data Memory. Program memory is where the 8032 executes instructions from. Data memory is used to hold data variables. Flash memory can be mapped in either program or data space. The Flash memory consists of two Flash memory blocks: the main Flash memory (1 or 2 Mbit) and the Secondary Flash memory (256 Kbit). Except during flash memory programming or update, Flash memory can only be read, not written to. A Page Register is used to access memory beyond the 64-Kbyte address space. Refer to the PSD module for details on mapping of the Flash memory. The 8032 core has two types of data memory (internal and external) that can be read and written. The internal SRAM consists of 256 bytes, and includes the stack area. The SFR (Special Function Registers) occupies the upper 128 bytes of the internal SRAM, the registers can be accessed by Direct addressing only. There are two separate blocks of external SRAM inside the UPSD325X devices: one 256-byte block is assigned for DDC data storage. Another 8 Kbytes resides in the PSD module that can be mapped to any address space defined by the user. Figure 4. Memory map and address space MAIN FLASH EXT. RAM INT. RAM SFR Indirect Addressing Direct Addressing FF SECONDARY FLASH 128KB EXT. RAM (DDC) FFFF 256B 8KB OR 7F 32KB 256KB Indirect or Direct Addressing 0 Flash Memory Space FF00 Internal RAM Space (256 Bytes) External RAM Space (MOVX) AI06635 2.2 Registers The 8032 has several registers; these are the Program Counter (PC), Accumulator (A), B Register (B), the Stack Pointer (SP), the Program Status Word (PSW), General purpose registers (R0 to R7), and DPTR (Data Pointer register). 16/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 5. Architecture overview 8032 MCU registers A Accumulator B B Register Stack Pointer SP PCH PCL Program Counter PSW Program Status Word General Purpose Register (Bank0-3) Data Pointer Register R0-R7 DPTR(DPH) DPTR(DPL) AI06636 2.2.1 Accumulator The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional tests. The Accumulator can be used as a 16-bit register with B Register as shown below. Figure 6. Configuration of BA 16-bit registers B B A A Two 8-bit Registers can be used as a "BA" 16-bit Registers AI06637 2.2.2 B register The B Register is the 8-bit general purpose register, used for an arithmetic operation such as multiply, division with Accumulator. 2.2.3 Stack pointer The Stack Pointer Register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07h after reset. This causes the stack to begin at location 08h. Figure 7. Stack pointer Stack Area (30h-FFh) Bit 15 Bit 8 Bit 7 00h Hardware Fixed Bit 0 SP 00h-FFh SP (Stack Pointer) could be in 00h-FFh AI06638 17/189 Architecture overview 2.2.4 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Program counter The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In RESET state, the program counter has reset routine address (PCH:00h, PCL:00h). 2.2.5 Program status word The Program Status Word (PSW) contains several bits that reflect the current state of the CPU and select Internal RAM (00h to 1Fh: Bank0 to Bank3). The PSW is described in Figure 8. It contains the Carry flag, the Auxiliary Carry flag, the Half Carry (for BCD operation), the General Purpose flag, the Register Bank Select flags, the Overflow flag, and Parity flag. [Carry flag, CY]. This flag stores any carry or not borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Auxiliary Carry flag, AC]. After operation, this flag is set when there is a carry from Bit 3 of ALU or there is no borrow from Bit 4 of ALU. [Register Bank Select flags, RS0, RS1]. These flags select one of four banks (00~07H:bank0, 08~0Fh:bank1, 10~17h:bank2, 17~1Fh:bank3) in Internal RAM. [Overflow flag, OV]. This flag is set to '1' when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127 (7Fh) or -128 (80h). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, Bit 6 of memory is copied to this flag. [Parity flag, P]. This flag reflects the number of Accumulator’s 1. If the number of Accumulator’s 1 is odd, P=0; otherwise, P=1. The sum when adding Accumulator’s 1 to P is always even. 2.2.6 Registers R0~R7 General purpose 8-bit registers that are locked in the lower portion of internal data area. 2.2.7 Data pointer register Data Pointer Register is 16-bit wide which consists of two-8bit registers, DPH and DPL. This register is used as a data pointer for the data transmission with external data memory in the PSD module. Figure 8. PSW (Program Status Word) register MSB PSW CY AC FO RS1 RS0 OV LSB P Reset Value 00h Parity Flag Carry Flag Auxillary Carry Flag Bit not assigned General Purpose Flag Overflow Flag Register Bank Select Flags (to select Bank0-3) AI06639 18/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2.3 Architecture overview Program memory The program memory consists of two Flash memories: the main Flash memory (1 or 2 Mbit) and the Secondary Flash memory (256 Kbit). The Flash memory can be mapped to any address space as defined by the user in the PSDsoft Tool. It can also be mapped to Data memory space during Flash memory update or programming. After reset, the CPU begins execution from location 0000h. As shown in Figure 9, each interrupt is assigned a fixed location in Program Memory. The interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External Interrupt 0, for example, is assigned to location 0003h. If External Interrupt 0 is going to be used, its service routine must begin at location 0003h. If the interrupt is not going to be used, its service location is available as general purpose Program Memory. The interrupt service locations are spaced at 8-byte intervals: 0003h for External Interrupt 0, 000Bh for Timer 0, 0013h for External Interrupt 1, 001Bh for Timer 1 and so forth. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. 2.4 Data memory The internal data memory is divided into four physically separated blocks: 256 bytes of internal RAM, 128 bytes of Special Function Registers (SFRs) areas, 256 bytes of external RAM (XRAM-DDC) and 8 Kbytes (XRAM-PSD) in the PSD module. 2.5 RAM Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. The stack depth is only limited by the available internal RAM space of 256 bytes. Figure 9. Interrupt location of program memory Interrupt Location • • • • • 008Bh • • • • 0013h 8 Bytes 000Bh 0003h Reset 0000h AI06640 19/189 Architecture overview 2.6 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV XRAM-DDC The 256 bytes of XRAM-DDC used to support DDC interface is also available for system usage by indirect addressing through the address pointer DDCADR and data I/O buffer RAMBUF. The address pointer (DDCADR) is equipped with the post increment capability to facilitate the transfer of data in bulk (for details refer to DDC Interface part). However, it is also possible to address the RAM through MOVX command as normally used in the internal RAM extension of 80C51 derivatives. XRAM-DDC FF00 to FFFF is directly addressable as external data memory locations FF00 to FFFF via MOVX-DPTR instruction or via MOVX-Ri instruction. When XRAM-DDC is disabled, the address space FF00 to FFFF can be assigned to other resources. 2.7 XRAM-PSD The 8 Kbytes of XRAM-PSD resides in the PSD module and can be mapped to any address space through the DPLD (Decoding PLD) as defined by the user in PSDsoft Development tool. 2.8 SFR The SFRs can only be addressed directly in the address range from 80h to FFh. Table 15 gives an overview of the Special Function Registers. Sixteen address in the SFRs space are both-byte and bit-addressable. The bit-addressable SFRs are those whose address ends in 0h and 8h. The bit addresses in this area are 80h to FFh. Table 3. RAM address Byte address (in hexadecimal) Byte address (in decimal) ¯ ¯ FFh 255 30h 48 MSB 20/189 Bit address (hex) LSB 2Fh 7F 7E 7D 7C 7B 7A 79 78 47 2Eh 77 76 75 74 73 72 71 70 46 2Dh 6F 6E 6D 6C 6B 6A 69 68 45 2Ch 67 66 65 64 63 62 61 60 44 2Bh 5F 5E 5D 5C 5B 5A 59 58 43 2Ah 57 56 55 54 53 52 51 50 42 29h 4F 4E 4D 4C 4B 4A 49 48 41 28h 47 46 45 44 43 42 41 40 40 27h 3F 3E 3D 3C 3B 3A 39 38 39 26h 37 36 35 34 33 32 31 30 38 25h 2F 2E 2D 2C 2B 2A 29 28 37 24h 27 26 25 24 23 22 21 20 36 23h 1F 1E 1D 1C 1B 1A 19 18 35 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 3. Architecture overview RAM address (continued) Byte address (in hexadecimal) Byte address (in decimal) ¯ ¯ 22h 17 16 15 14 13 12 11 10 34 21h 0F 0E 0D 0C 0B 0A 09 08 33 20h 07 06 05 04 03 02 01 00 32 1Fh 18h 17h 24 23 Register bank 2 10h 0Fh 16 15 Register bank 1 08h 07h 8 7 Register bank 0 00h 2.9 31 Register bank 3 0 Addressing modes The addressing modes in UPSD323xx devices instruction set are as follows 2.9.1 1. Direct addressing 2. Indirect addressing 3. Register addressing 4. Register-specific addressing 5. Immediate constants addressing 6. Indexed addressing Direct addressing In a direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal Data RAM and SFRs (80~FFH RAM) can be directly addressed. Example: mov A, 3EH ; A 50ns) Required Start/Stop Hold Time Note 00h 1EA 50ns When Bit 7 (enable bit) = 0, the number of sample clock is 1EA (ignore Bit 6 to Bit 0) 80h 1EA 50ns 81h 2EA 100ns 82h 3EA 150ns ... ... ... 8Bh 12EA 600ns ... ... ... FFh 128EA 6000ns Table 59. 88/189 System clock of 40MHz Fast mode I²C Start/Stop hold time specification System clock setup examples System Clock S1SETUP, S2SETUP Register Value Number of Sample Clock Required Start/Stop Hold Time 40MHz (fOSC/2 -> 50ns) 8Bh 12 EA 600ns 30MHz (fOSC/2 -> 66.6ns) 89h 9 EA 600ns 20MHz (fOSC/2 -> 100ns) 86h 6 EA 600ns 8MHz (fOSC/2 -> 250ns) 83h 3 EA 750ns UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 16 DDC interface DDC interface The basic DDC unit consists of an I2C interface and 256 bytes of SRAM for DDC data storage. The 8032 core is responsible of loading the contents of the SRAM with the DDC data. The DDC unit has the following features: ● Supports both DDC1 and DDC2b modes ● Features 256 bytes of DDC data - initialized by the 8032 core ● Supports fully automatic operation of DDC1 and DDC2b modes ● DDC operates in Slave mode only ● SW Interrupt mode available (existing design) The interface signals for the DDC can be mapped to pins in Port 4. The interface consists of the standard VSYNC (P4.2), SDA (P4.0) and SCL (P4.1) DDC signals. The conceptual block diagram is illustrated in Figure 42. Figure 39. DDC interface block diagram DDC2B/DDC2AB DDC2B+Interface 7 1 0 Monitor Address S1ADR0 Monitor Address S1ADR1 SDA1 Shift Register S1DAT Arbitration Logic SCL1 Internal Bus Bus Clock Generator SICON SISTA DDC1/DDC2 Detection RAMBUF RAM Buffer DDC1 Hold Register DDCDAT DDC1 Transmitter VSYNCEN Address Pointer Initialization Synchronization X EX_ SW DAT ENB X DDC1 DDC1 SWH INT EN INT M0 DDCADR INTR (from SISTA) DDCCON INT AI06628 16.1 Special Function register for the DDC interface There are eight SFR in the DDC interface: ● RAMBUF, DDCCON, DDCADR, DDCDAT are DDC registers. ● S1CON, S1STA, S1DAT, S1ADR are I2C Interface registers, same as the ones described in the standalone I2C bus. 89/189 DDC interface 16.1.1 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DDCDAT register DDC1 DATA register for transmission (DDCDAT: 0D5h) 16.1.2 ● 8-bit READ and WRITE register ● Indicates DATA BYTE to be transmitted in DDC1 protocol DDCADR register Address pointer for DDC interface (DDCADR: 0D6h) Table 60. ● 8-bit READ and WRITE register. ● Address pointer with the capability of the post increment. After each access to RAMBUF register (either by software or by hardware DDC1 interface), the content of this register will be increased by one. It’s available both in DDC1, DDC2 (DDC2B, DDC2B+, and DDC2AB) and system operation. DDC SFR memory map Bit Register Name SFR Addr Reg Name D4 RAMBUF XX DDC Ram Buffer D5 DDCDAT 00 DDC Data xmit register D6 DDCADR 00 Addr pointer register D7 DDCCO N 00 DDC Control Register 7 — Table 61. EX_DAT 5 4 3 2 1 SWEN DDC_A DDCIN SWHIN DDC1EN B X T T 0 M0 Description of the DDCON register bits Bit Symbol 7 — 6 EX_DAT 0 = The SRAM has 128 bytes (Default) 1 = The SRAM has 256 bytes SWENB Note: This bit is valid for DDC1 & DDC2b modes 0 = Data is automatically read from SRAM at the current location of DDCADR and sent out via current DDC protocol. (Default) 1 = MCU is interrupted during the current data byte transmission period to load the next byte of data to send out. DDC_AX Note: This bit is valid for DDC1 & DDC2b modes 0 = Data is automatically read from SRAM at the current location of DDCADR and sent out via current DDC protocol. (Default) 1 = MCU is interrupted during the current data byte transmission period to load the next byte of data to send out. This bit only affects DDC2b mode Operation: 0 = DDC2b I2C Address is A0/A1 (default) 1 = DDC2b I2C Address is AX. Least 3 significant address bits are ignored. 5 4 90/189 6 Reset Comments Value Function Reserved UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 61. Bit 3 2 1 0 Table 62. DDC interface Description of the DDCON register bits (continued) Symbol Function For DDC1 mode Operation Only: 0 = No DDC1 Interrupt DDC1_Int 1 = DDC1 Interrupt request. Set by HW and should be cleared by SW interrupt service routine. Note1: This bit is set in the 9th VCLK at DDC1 Enable mode. (SWENB=1) DDC1EN 0 = DDC1 mode is disabled – VSYNC is ignored. The DDC unit will still respond to DDC2b requests. –provided I2C enabled.(Default) 1 = DDC1 mode is enabled. SWHINT Set by hardware when the DDC unit switches from DDC1 to DDC2b modes. 0 = No interrupt request. 1 = Switch to DDC2b mode (Interrupt pending) Set by HW and should be cleared by SW interrupt service routine. Note1: This bit has no connection with SWENB. Mode Current Mode Indication Bit: 0 = Unit is in DDC1 mode 1 = Unit is in DDC2b mode Note: When the DDC unit transitions to DDC2b mode, the DDC unit will stay in DDC2b mode until the DDC unit is disabled, or the system is reset. SWNEB bit function DDC1 or DDC2b mode Disabled DDC1 or DDC2b mode Enabled DDCCON.bit2 = 0 (DDC1 mode Disable) or DDCCON.bit2 = 1 (DDC1 mode Enable) or S1CON.bit6 = 0 (I2C mode Disable) S1CON.bit6 = 1 (I2C mode Enable) 0 In this state, the DDC unit is disabled. The DDC SRAM cannot be accessed by the MCU. No MCU interrupt and no DDC activity will occur. MCU cannot access internal DDC SRAM: DDC SRAM address space is re-assigned to external data space. In this state, the DDC is enabled and the unit is in automatic mode. The DDC SRAM cannot be accessed by the MCU – only the DDC unit has access. MCU cannot access internal DDC SRAM: data space FF00h-FFFFh is dedicated to DDC SRAM. 1 In this state, the DDC unit is disabled, BUT with SWENB=1, the MCU can access the SRAM. This state is used to load the DDC SRAM with the correct data for automatic modes. No MCU interrupt and no DDC activity will occur. MCU can access DDC SRAM: data space FF00hFFFFh is dedicated to DDC SRAM. In this state, the DDC SRAM can be accessed by the MCU. The DDC unit does not use the DDC SRAM when SWENB=1. Since the DDC unit is in manual mode, the DDC unit generates an MCU interrupt for each byte transferred. The byte transferred is held in the I2C S1DAT SFR register. MCU can access DDC SRAM. SWENB 91/189 DDC interface 16.2 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Host type detection The detection procedure conforms to the sequences proposed by VESA Monitor Display Data Channel (DDC) specification. The monitor needs to determine the type of host system: ● DDC1 or OLD type host ● DDC2B host (Host is master, monitor is always slave) ● DDC2B+/DDC2AB(ACCESS.bus) host Figure 40. Host type detection Power on Communication isidle Is VSYNC present? EDID sent continously using VSYNC as clock Is DDC2 clock present? Stop sending of EDID switch to DDC2 communication mode DDC2 communication is idle. Has a command been received? Is 2B+/A.B command detected? Is it DDC2B command? Respond to DDC2B command Is DDC2B+/DDC2AB? Respond to DDC2B+/ DDC2AB command AI06644 16.3 DDC1 protocol DDC1 is primitive and a point to point interface. The monitor is always put at “Transmit only” mode. In the initialization phase, 9 clock cycles on VCLK pin will be given for the internal synchronization. During this period, the SDA pin will be kept at high impedance state. If DDC1 hardware mode is used, the following procedure is recommended to proceed DDC1 operation. 92/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DDC interface 1. Reset DDC1 enable (by default, DDC1 enable is cleared as LOW after Power-on Reset). 2. Set SWENB as high (the default value is zero.) 3. Depending on the data size of EDID data, set EX_DAT as LOW (128 bytes) or HIGH (256 bytes). 4. By using bulky moving commands (DDCADR, RAMBUF involved) to move the entire EDID data to RAM buffer. 5. Reset SWENB to LOW. 6. Reset DDCADR to 00h. 7. Set DDC1 enable as HIGH. In case SWENB is set as high, interrupt service routine is finished within 133 machine cycle in 40MHz System clock. The maximum VSYNC (VCLK) frequency is 25Khz (40µs). And the 9th clock of VSYNC (VCLK) is interrupt period. So the machine cycle be needed is calculated as below. For example, Note: ● When 40MHz system clock, 40µs = 133 x (25ns x 12); 133 machine cycle. ● 12MHz system clock, 40µs = 40 x (83.3ns x 12); 40 machine cycle. ● 8MHz system clock, 40µs = 26 x (125ns x 12); 26 machine cycle. If EX_DAT equals to LOW, it is meant the lower part is occupied by DDC1 operation and the upper part is still free to the system. Nevertheless, the effect of the post increment just applies to the part related to DDC1 operation. In other words, the system program is still able to address the locations from 128 to 255 in the RAM buffer through MOVX command but without the facility of the post increment. For example, the case of accessing 200 of the RAM Buffer: MOV R0, #200, and MOVX A, @R0 Figure 41. Transmission protocol in the DDC1 interface Max=40us SC VCLK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 DDC1INT DDC1EN SD B Hi-Z tSU(DDC1) t H(VCLK) t L(VCLK) B B B B B B B HiZ B t DOV AI06652 93/189 DDC interface 16.4 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DDC2B protocol DDC2B is constructed based on the Philips I2C interface. However, in the level of DDC2B, PC host is fixed as the master and the monitor is always regarded as the slave. Both master and slave can be operated as a transmitter or receiver, but the master device determines which mode is activated. In this protocol, address pointer is also used. According to DDC2B specification, A0 (for WRITE mode) and A1 (for READ mode) are assigned as the default address of monitors. The reception of the incoming data in WRITE mode or the updating of the outgoing data in READ mode should be finished within the specified time limit. If software in the slave’s side cannot react to the master in time, based on I2C protocol, SCL pin can be stretched low to inhibit the further action from the master. The transaction can be proceeded in either byte or burst format. Figure 42. Conceptual structure of the DDC interface DDC Interrupt vector address ( 0023H ) Check Mode flag in DDCCON Mode = 1 Mode = 1 Mode = 0 DDC2B/DDC2AB commandreceived SWENB =1 DDC2B SWENB =1 DDC2B Utilities DDC2B/DDC2AB Utilities I2C ServiceRoutines SWENB =0 DDC1.DDC2B Utilities DDC Transmitter (H/W) I2C interface (H/W) AI06645 94/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 17 USB hardware USB hardware The characteristics of USB hardware are as follows: ● Complies with the Universal Serial Bus specification Rev. 1.1 ● Integrated SIE (Serial Interface Engine), FIFO memory and transceiver ● Low speed (1.5Mbit/s) device capability ● Supports control endpoint0 and interrupt endpoint1 and 2 ● USB clock input must be 6MHz (requires MCU clock frequency to be 12, 24, or 36MHz). The analog front-end is an on-chip generic USB transceiver. It is designed to allow voltage levels equal to VDD from the standard logic to interface with the physical layer of the Universal Serial Bus. It is capable of receiving and transmitting serial data at low speed (1.5Mb/s). The SIE is the digital-front-end of the USB block. This module recovers the 1.5MHz clock, detects the USB sync word and handles all low-level USB protocols and error checking. The bit-clock recovery circuit recovers the clock from the incoming USB data stream and is able to track jitter and frequency drift according to the USB specification. The SIE also translates the electrical USB signals into bytes or signals. Depending upon the device USB address and the USB endpoint. Address, the USB data is directed to the correct endpoint on SIE interface. The data transfer of this H/W could be of type control or interrupt. The device’s USB address and the enabling of the endpoints are programmable in the SIE configuration header. 17.1 USB related registers The USB block is controlled via seven registers in the memory: (UADR, UCON0, UCON1, UCON2, UISTA, UIEN, and USTA). Three memory locations on chip which communicate the USB block are: ● USB endpoint0 data transmit register (UDT0) ● USB endpoint0 data receive register (UDR0) ● USB endpoint1 data transmit register (UDT1) Table 63. USB address register (UADR: 0EEh) 7 6 5 4 3 2 1 0 USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 95/189 USB hardware UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 64. Bit Symbol R/W Function 7 USBEN R/W USB Function Enable Bit. When USBEN is clear, the USB module will not respond to any tokens from host. RESET clears this bit. 6 to 0 UADD6 to UADD0 R/W Specify the USB address of the device. RESET clears these bits. Table 65. USB interrupt enable register (UIEN: 0E9h) 7 6 5 4 3 2 1 0 SUSPNDI RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMI Table 66. Description of the UIEN bits Bit Symbol R/W 7 SUSPNDI R/W Enable SUSPND Interrupt 6 RSTE R/W Enable USB Reset; also resets the CPU and PSD modules when bit is set to '1.' 5 RSTFIE R/W Enable RSTF (USB Bus Reset Flag) Interrupt 4 TXD0IE R/W Enable TXD0 Interrupt 3 RXD0IE R/W Enable RXD0 Interrupt 2 TXD1IE R/W Enable TXD1 Interrupt 1 EOPIE R/W Enable EOP Interrupt 0 RESUMI R/W Enable USB Resume Interrupt when it is the Suspend mode Table 67. Function USB interrupt status register (UISTA: 0E8h) 7 6 5 4 3 2 1 0 SUSPND — RSTF TXD0F RXD0F TXD1F EOPF RESUMF Table 68. Bit Description of the UISTA bits Symbol R/W Function USB Suspend Mode Flag. To save power, this bit should be set if a 3ms constant idle state is detected on USB bus. Setting this bit stops the clock to the USB and causes the USB module to enter Suspend mode. Software must clear this bit after the Resume flag (RESUMF) is set while this Resume Interrupt Flag is serviced 7 SUSPND R/W 6 — — Reserved R USB Reset Flag. This bit is set when a valid RESET signal state is detected on the D+ and D- lines. When the RSTE bit in the UIEN Register is set, this reset detection will also generate an internal reset signal to reset the CPU and other peripherals including the USB module. 5 96/189 Description of the UADR Bits RSTF UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 68. Bit 4 3 2 1 0 Table 69. USB hardware Description of the UISTA bits (continued) Symbol TXD0F RXD0F TXD1F EOPF RESUMF R/W Function R/W Endpoint0 Data Transmit Flag. This bit is set after the data stored in Endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag. To enable the next data packet transmission, TX0E must also be set. If TXD0F Bit is not cleared, a NAK handshake will be returned in the next IN transactions. RESET clears this bit. R/W Endpoint0 Data Receive Flag. This bit is set after the USB module has received a data packet and responded with ACK handshake packet. Software must clear this flag after all of the received data has been read. Software must also set RX0E Bit to one to enable the next data packet reception. If RXD0F Bit is not cleared, a NAK handshake will be returned in the next OUT transaction. RESET clears this bit. R/W Endpoint1 / Endpoint2 Data Transmit Flag. This bit is shared by Endpoints 1 and Endpoints 2. It is set after the data stored in the shared Endpoint 1/ Endpoint 2 transmit buffer has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag. To enable the next data packet transmission, TX1E must also be set. If TXD1F Bit is not cleared, a NAK handshake will be returned in the next IN transaction. RESET clears this bit. R/W End of Packet Flag. This bit is set when a valid End of Packet sequence is detected on the D+ and D-line. Software must clear this flag. RESET clears this bit. R/W Resume Flag. This bit is set when USB bus activity is detected while the SUSPND Bit is set. Software must clear this flag. RESET clears this bit. USB Endpoint0 transmit control register (UCON0: 0EAh) 7 6 5 4 3 2 1 0 TSEQ0 STALL0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 97/189 USB hardware UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 70. Bit 7 6 5 Symbol TSEQ0 STALL0 TX0E R/W Function R/W Endpoint0 Data Sequence Bit. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction. Toggling of this bit must be controlled by software. RESET clears this bit R/W Endpoint0 Force Stall Bit. This bit causes Endpoint 0 to return a STALL handshake when polled by either an IN or OUT token by the USB Host Controller. The USB hardware clears this bit when a SETUP token is received. RESET clears this bit. R/W Endpoint0 Transmit Enable. This bit enables a transmit to occur when the USB Host Controller sends an IN token to Endpoint 0. Software should set this bit when data is ready to be transmitted. It must be cleared by software when no more Endpoint 0 data needs to be transmitted. If this bit is '0' or the TXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 IN tokens. RESET clears this bit. 4 RX0E R/W Endpoint0 receive enable. This bit enables a receive to occur when the USB Host Controller sends an OUT token to Endpoint 0. Software should set this bit when data is ready to be received. It must be cleared by software when data cannot be received. If this bit is '0' or the RXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 OUT tokens. RESET clears this bit. 3 to 0 TP0SIZ3 to TP0SIZ0 R/W The number of transmit data bytes. These bits are cleared by RESET. Table 71. 98/189 Description of the UCON0 bits USB Endpoint1 (and 2) transmit control register (UCON1: 0EBh) 7 6 5 4 3 2 1 0 TSEQ1 EP12SEL TX1E FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 72. Bit 7 6 5 USB hardware Description of the UCON1 bits Symbol TSEQ1 EP12SEL TX1E R/W Function R/W Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2. Toggling of this bit must be controlled by software. RESET clears this bit. R/W Endpoint 1/ Endpoint 2 Transmit Selection. (0=Endpoint 1, 1=Endpoint 2) This bit specifies whether the data inside the registers UDT1 are used for Endpoint 1 or Endpoint 2. If all the conditions for a successful Endpoint 2 USB response to a hosts IN token are satisfied (TXD1F=0, TX1E=1, STALL2=0, and EP2E=1) except that the EP12SEL Bit is configured for Endpoint 1, the USB responds with a NAK handshake packet. RESET clears this bit. R/W Endpoint1 / Endpoint2 Transmit Enable. This bit enables a transmit to occur when the USB Host Controller send an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint enable bit, EP1E or EP2E Bit in the UCON2 register, should also be set. Software should set the TX1E Bit when data is ready to be transmitted. It must be cleared by software when no more data needs to be transmitted. If this bit is '0' or TXD1F is set, the USB will respond with a NAK handshake to any Endpoint 1 or Endpoint 2 directed IN token. RESET clears this bit. 4 FRESUM R/W Force Resume. This bit forces a resume state (“K” on non-idle state) on the USB data lines to initiate a remote wake-up. Software should control the timing of the forced resume to be between 10ms and 15ms. Setting this bit will not cause the RESUMF Bit to set. 3 to 0 TP1SIZ3 to TP1SIZ0 R/W The number of transmit data bytes. These bits are cleared by RESET. Table 73. USB control register (UCON2: 0ECh) 7 6 5 4 3 2 1 0 — — — SOUT EP2E EP1E STALL2 STALL1 Table 74. Description of the UCON2 bits Bit Symbol R/W Function 7 to 5 — — 4 SOUT R/W Status out is used to automatically respond to the OUT of a control READ transfer 3 EP2E R/W Endpoint2 enable. RESET clears this bit Reserved 99/189 USB hardware UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 74. Description of the UCON2 bits (continued) Bit Symbol R/W 2 EP1E R/W Endpoint1 enable. RESET clears this bit 1 STALL2 R/W Endpoint2 Force Stall Bit. RESET clears this bit 0 STALL1 R/W Endpoint1 Force Stall Bit. RESET clears this bit Table 75. Function USB Endpoint0 status register (USTA: 0EDh) 7 6 5 4 3 2 1 0 RSEQ SETUP IN OUT RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 Table 76. Description of the USTA bits Bit Symbol R/W 7 RSEQ R/W Endpoint0 receive data packet PID. (0=DATA0, 1=DATA1) This bit will be compared with the type of data packet last received for Endpoint0 6 SETUP R SETUP Token Detect Bit. This bit is set when the received token packet is a SEPUP token, PID = b1101. 5 IN R IN Token Detect Bit. This bit is set when the received token packet is an IN token. 4 OUT R OUT Token Detect Bit. This bit is set when the received token packet is an OUT token. 3 to 0 RP0SIZ3 to RP0SIZ0 R The number of data bytes received in a DATA packet Table 77. Function USB Endpoint0 data receive register (UDR0: 0EFh) 7 6 5 4 3 2 1 0 UDR0.7 UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0.0 Table 78. USB Endpoint0 data transmit register (UDT0: 0E7h) 7 6 5 4 3 2 1 0 UDT0.7 UDT0.6 UDT0.5 UDT0.4 UDT0.3 UDT0.2 UDT0.1 UDT0.0 Table 79. USB Endpoint1 data transmit register (UDT1: 0E6h) 7 6 5 4 3 2 1 0 UDT1.7 UDT1.6 UDT1.5 UDT1.4 UDT1.3 UDT1.2 UDT1.1 UDT1.0 The USCL 8-bit prescaler register for USB is at E1h. The USCL should be loaded with a value that results in a clock rate of 6 MHz for the USB using the following formula: USB clock input = (fOSC / 2) / (Prescaler register value +1) Where fOSC is the MCU clock input frequency. Note: 100/189 USB works ONLY with the MCU Clock frequencies of 12, 24, or 36 MHz. The Prescaler values for these frequencies are 0, 1, and 2. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 80. SFR Reg Add Name r USB hardware USB SFR memory map Bit Register Name 7 6 5 4 3 Reset 2 1 E1 USCL E6 UDT1 UDT1.7 UDT1.6 UDT1.5 UDT1.4 UDT1.3 UDT1.2 UDT1.1 E7 UDT0 UDT0.7 UDT0.6 UDT0.5 UDT0.4 UDT0.3 UDT0.2 UDT0.1 E8 UISTA SUSPND — E9 UIEN SUSPNDI E RSTE EA UCON0 0 value Comments 00 8-bit Prescaler for USB logic UDT1.0 00 USB Endpt1 Data Xmit UDT0.0 00 USB Endpt0 Data Xmit RXD1F EOPF RESUMF 00 USB Interrupt Status RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMI E 00 USB Interrupt Enable 00 USB Endpt0 Xmit Control 00 USB Endpt1 Xmit Control STALL1 00 USB Control Register RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 00 USB Endpt0 Status RSTF TX0E TXD0F TSEQ0 STALL0 RX0E EB UCON1 TSEQ1 EP12SE L — EC UCON2 — — — SOUT RXD0F TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 FRESU TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 M EP2E EP1E STALL2 ED USTA RSEQ SETUP IN OUT EE UADR USBEN UADD6 UADD5 UADD4 UADD0 00 USB Address Register EF UDR0 UDR0.7 UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0.0 00 USB Endpt0 Data Recv UADD3 17.2 Transceiver 17.2.1 USB physical layer characteristics UADD2 UADD1 The following section describes the UPSD323xx devices compliance to the Chapter 7 Electrical section of the USB Specification, Revision 1.1. The section contains all signaling, and physical layer specifications necessary to describe a low speed USB function. 101/189 USB hardware 17.2.2 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Low speed driver characteristics The UPSD323xx devices use a differential output driver to drive the Low Speed USB data signal onto the USB cable. The output swings between the differential high and low state are well balanced to minimize signal skew. The slew rate control on the driver minimizes the radiated noise and cross talk on the USB cable. The driver’s outputs support three-state operation to achieve bi-directional half duplex operation. The UPSD323xx devices driver tolerates a voltage on the signal pins of -0.5 V to 3.6 V with respect to local ground reference without damage. The driver tolerates this voltage for 10.0µs while the driver is active and driving, and tolerates this condition indefinitely when the driver is in its high impedance state. A low speed USB connection is made through an unshielded, untwisted wire cable a maximum of 3 meters in length. The rise and fall time of the signals on this cable are well controlled to reduce RFI emissions while limiting delays, signaling skews and distortions. The UPSD323xx devices driver reaches the specified static signal levels with smooth rise and fall times, resulting in segments between low speed devices and the ports to which they are connected. Figure 43. Low speed driver signal waveforms One Bit Time 1.5 Mb/s VSE(max) Driver Signal Pins Signal pins pass output spec levels with minimal reflections and ringing VSE(min) VSS AI06629 17.3 Receiver characteristics UPSD323xx devices have a differential input receiver which is able to accept the USB data signal. The receiver features an input sensitivity of at least 200 mV when both differential data inputs are in the range of at least 0.8 V to 2.5 V with respect to its local ground reference. This is the common mode range, as shown in Figure 44. The receiver tolerates static input voltages between -0.5 V to 3.8 V with respect to its local ground reference without damage. In addition to the differential receiver, there is a single-ended receiver for each of the two data lines. The single-ended receivers have a switching threshold between 0.8 V and 2.0 V (TTL inputs). 102/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV USB hardware Minimum Differential Sensitivity (volts) Figure 44. Differential input sensitivity over entire common mode range 1.0 0.8 0.6 0.4 0.2 0.0 0.0 17.4 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Common Mode Input Voltage (volts) 2.6 2.8 3.0 3.2 AI06630 External USB pull-up resistor The USB system specifies a pull-up resistor on the D- pin for low-speed peripherals. The USB Spec 1.1 describes a 1.5 kΩ pull-up resistor to a 3.3 V supply. An approved alternative method is a 7.5 kΩ pull-up to the USB VCC supply. This alternative is defined for low-speed devices with an integrated cable. The chip is specified for the 7.5 kΩ pull-up. This eliminates the need for an external 3.3 V regulator, or for a pin dedicated to providing a 3.3 V output from the chip. Figure 45. USB data signal timing and voltage levels tR VOH tF D+ 90% 90% VCR VOL 10% 10% D- AI06631 Figure 46. Receiver jitter tolerance TPERIOD Differential Data Lines TJR TJR1 TJR2 Consecutive Transitions N*TPERIOD+TJR1 Paired Transitions N*TPERIOD+TJR2 AI06632 103/189 USB hardware UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 47. Differential to EOP transition skew and EOP width TPERIOD Crossover Point Extended Crossover Point Differential Data Lines Diff. Data to SE0 Skew N*TPERIOD+TDEOP Source EOP Width: TEOPT Receiver EOP Width TEOPR1, TEOPR2 Figure 48. Differential data jitter TPERIOD Crossover Points Differential Data Lines Consecutive Transitions N*TPERIOD+TxJR1 Paired Transitions N*TPERIOD+TxJR2 AI06634 Table 81. Symb Transceiver DC characteristics Parameter Test Conditions(1) Min Max Unit VOH Static Output High 15 kΩ ± 5% to GND(2,3) 2.8 3.6 V VOL Static Output Low Notes 2, 3 — 0.3 V VDI Differential Input Sensitivity |(D+) - (D-)|, Figure 46 0.2 — V VCM Differential Input Common mode Figure 46 0.8 2.5 V VSE Single Ended Receiver Threshold — 0.8 2.0 V CIN Transceiver Capacitance — — 20 pF IIO Data Line (D+, D-) Leakage 0 < (D+,D-) < 3.3 –10 10 µA 7.5 kΩ ± 2% to VCC 7.35 7.65 kΩ 15 kΩ ± 5% 14.25 15.75 kΩ RPU External Bus Pull-up Resistance, D- RPD External Bus Pull-down Resistance 1. VCC = 5 V ± 10%; VSS = 0 V; TA = 0 to 70°C. 2. Level guaranteed for range of VCC = 4.5 V to 5.5 V. 3. With RPU, external idle resistor, 7.5 κ±2%, D- to VCC. 104/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 82. Symb tDRATE USB hardware Transceiver AC characteristics Parameter Low Speed Data Rate Test Conditions(1) Min Max Unit Ave. bit rate (1.5Mb/s ± 1.5%) 1.4775 1.5225 Mbit/s To next transition, Figure 46(5) –75 75 ns For paired transition, Figure 46(5) –45 45 ns Figure 47(5) –40 100 ns tDJR1 Receiver Data Jitter Tolerance tDJR2 Differential Input Sensitivity tDEOP Differential to EOP Transition Skew tEOPR1 EOP Width at Receiver Rejects as EOP(5,6) 165 — ns EOP Width at Receiver EOP(5) 675 — ns — –1.25 1.50 µs tEOPR2 Accepts as tEOPT Source EOP Width tUDJ1 Differential Driver Jitter To next transition, Figure 48 –95 95 ns tUDJ2 Differential Driver Jitter To paired transition, Figure 48 –150 150 ns tR USB Data Transition Rise Time Notes 2, 3, 4 75 300 ns tF USB Data Transition Fall Time Notes 2, 3, 4 75 300 ns tRFM Rise/Fall Time Matching t R / tF 80 120 % VCRS Output Signal Crossover Voltage — 1.3 2.0 V 1. VCC = 5 V ± 10%; VSS = 0 V; TA = 0 to 70°C. 2. Level guaranteed for range of VCC = 4.5 V to 5.5 V. 3. With RPU, external idle resistor, 7.5κ±2%, D- to VCC. 4. CL of 50 pF (75 ns) to 350 pF (300 ns). 5. Measured at crossover point of differential data signals. 6. USB specification indicates 330 ns. 105/189 PSD module 18 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PSD module The PSD module provides configurable Program and Data memories to the 8032 CPU core (MCU). In addition, it has its own set of I/O ports and a PLD with 16 macrocells for general logic implementation. Ports A,B,C, and D are general purpose programmable I/O ports that have a port architecture which is different from the I/O ports in the MCU module. The PSD module communicates with the MCU module through the internal address, data bus (A0-A15, D0-D7) and control signals (RD, WR, PSEN, ALE, RESET). The user defines the Decoding PLD in the PSDsoft Development Tool and can map the resources in the PSD module to any program or data address space. Figure 49 shows the functional blocks in the PSD module. 18.1 Functional overview ● 1 or 2 Mbit Flash memory. This is the main Flash memory. It is divided into eight equalsized blocks that can be accessed with user-specified addresses. ● Secondary 256 Kbit Flash boot memory. It is divided into four equal-sized blocks thatat can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. ● 64 Kbit SRAM. ● CPLD with 16 Output Micro Cells (OMCs} and 20 Input Micro Cells (IMCs). The CPLD may be used to efficiently implement a variety of logic functions for internal and external control. Examples include state machines, loadable shift registers, and loadable counters. ● Decode PLD (DPLD) that decodes address for selection of memory blocks in the PSD module. ● Configurable I/O ports (Port A,B,C and D) that can be used for the following functions: – MCU I/Os – PLD I/Os – Latched MCU address output – Special function I/Os – I/O ports may be configured as open-drain outputs ● Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP). With it, you can program a blank device or reprogram a device in the factory or the field. ● Internal page register that can be used to expand the 8032 MCU module address space by a factor of 256. ● Internal programmable Power Management Unit (PMU) that supports a low-power mode called Power-down mode. The PMU can automatically detect a lack of the 8032 CPU core activity and put the PSD module into Power-down mode. ● Erase/WRITE cycles: Flash memory - 100,000 minimum PLD - 1,000 minimum Data Retention: 15 year minimum (for Main Flash memory, Boot, PLD and Configuration bits) 106/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PSD module 73 PD1 – PD2 JTAG SERIAL CHANNEL PLD, CONFIGURATION & FLASH MEMORY LOADER CLKIN MACROCELL FEEDBACK OR PORT INPUT PORT A ,B & C CLKIN 73 PORT D PROG. PORT PC0 – PC7 PORT C PROG. PORT PB0 – PB7 PORT B 20 INPUT MACROCELLS PROG. PORT PORT A ,B & C FLASH ISP CPLD (CPLD) 2 EXT CS TO PORT D RUNTIME CONTROL AND I/O REGISTERS 16 OUTPUT MACROCELLS PROG. PORT PORT A CSIOP PERIP I/O MODE SELECTS FLASH DECODE PLD (DPLD) SECTOR SELECTS 256 KBIT SECONDARY NON-VOLATILE MEMORY (BOOT OR DATA) 4 SECTORS SECTOR SELECTS 8 SECTORS 8 CLKIN (PD1) GLOBAL CONFIG. & SECURITY BUS Interface D0 – D7 WR_, RD_, PSEN_, ALE, RESET_, A0-A15 8032 Bus BUS Interface PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM ADDRESS/DATA/CONTROL BUS 1 OR 2 MBIT PRIMARY FLASH MEMORY POWER MANGMT UNIT PA0 – PA7 VSTDBY (PC2) Figure 49. UPSD323xx PSD module block diagram AI05797 18.2 In-system programming (ISP) Using the JTAG signals on Port C, the entire PSD module device can be programmed or erased without the use of the MCU. The primary Flash memory can also be programmed insystem by the MCU executing the programming algorithms out of the secondary memory, or SRAM. The secondary memory can be programmed the same way by executing out of the primary Flash memory. The PLD or other PSD module configuration blocks can be programmed through the JTAG port or a device programmer. Table Table 83 indicates which programming methods can program different functional blocks of the PSD module. 107/189 PSD module UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 83. Methods of programming different functional blocks of the PSD module Functional Block 108/189 JTAG programming Device programmer IAP Primary Flash memory Yes Yes Yes Secondary Flash memory Yes Yes Yes PLD array (DPLD and CPLD) Yes Yes No PSD module configuration Yes Yes No UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 19 Development system Development system UPSD323xx devices are supported by PSDsoft, a Windows-based software development tool (Windows-95, Windows-98, Windows-NT). A PSD module design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD module pin functions and memory map information. The general design flow is shown in Figure 50. PSDsoft is available from our web site (the address is given on the back page of this data sheet) or other distribution channels. PSDsoft directly supports a low cost device programmer from ST: FlashLINK (JTAG). The programmer may be purchased through your local distributor/representative. UPSD323xx devices are also supported by third party device programmers. See our web site for the current list. Figure 50. PSDsoft express development tool Choose µPSD Define µPSD Pin and Node Functions Point and click definition of PSD pin functions, internal nodes, and MCU system memory map Define General Purpose Logic in CPLD C Code Generation Point and click definition of combinatorial and registered logic in CPLD. Access HDL is available if needed GENERATE C CODE SPECIFIC TO PSD FUNCTIONS Merge MCU Firmware with PSD Module Configuration A composite object file is created containing MCU firmware and PSD configuration MCU FIRMWARE HEX OR S-RECORD FORMAT USER'S CHOICE OF 8032 COMPILER/LINKER *.OBJ FILE PSD Programmer FlashLINK (JTAG) *.OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS AI05798 109/189 PSD module register description and address offset 20 UPSD3234A, UPSD3234BV, UPSD3233B, PSD module register description and address offset Table 84 shows the offset addresses to the PSD module registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD module registers. Table 84 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description. Table 84. Register address offset Register Name Port A Port B Port C Port D Other(1) 00 01 Control 02 03 Data Out 04 05 12 13 Stores data for output to Port pins, MCU I/O Output mode Direction 06 07 14 15 Configures Port pin as input or output Drive Select 08 09 16 17 Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Input Macrocell 0A 0B 18 Enable Out 0C 0D 1A Output Macrocells AB 20 20 Mask Macrocells AB Mask Macrocells BC 21 22 11 Selects mode between MCU I/O or Address Out Reads Input Macrocells Reads the status of the output enable to the I/O Port driver 1B READ – reads output of macrocells AB WRITE – loads macrocell flip-flops READ – reads output of macrocells BC WRITE – loads macrocell flip-flops 21 Blocks writing to the Output Macrocells AB 22 23 Blocks writing to the Output Macrocells BC 23 Primary Flash Protection C0 Read-only – Primary Flash Sector Protection Secondary Flash memory Protection C2 Read-only – PSD module Security and Secondary Flash memory Sector Protection PMMR0 B0 Power Management Register 0 PMMR2 B4 Power Management Register 2 Page E0 Page Register VM E2 Places PSD module memory areas in Program and/or Data space on an individual basis. 1. Other registers that are not part of the I/O ports. 110/189 Reads Port pin as input, MCU I/O Input mode Data In Output Macrocells BC 10 Description UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 21 PSD module detailed operation PSD module detailed operation As shown in Figure 14, the PSD module consists of five major types of functional blocks: ● Memory blocks ● PLD blocks ● I/O Ports ● Power Management Unit (PMU) ● JTAG Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. 111/189 Memory blocks 22 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Memory blocks The PSD module has the following memory blocks: ● Primary Flash memory ● Secondary Flash memory ● SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft Express. 22.1 Primary Flash memory and secondary Flash memory description The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sector basis. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy (PC3). This pin is set up using PSDsoft Express Configuration. 22.2 Memory block select signals The DPLD generates the Select signals for all the internal memory blocks (see Section 23: PLDs). Each of the eight sectors of the primary Flash memory has a Select signal (FS0FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in Program or Data space. 22.2.1 Ready/Busy (PC3) This signal can be used to output the Ready/Busy status of the Flash memory. The output on Ready/Busy (PC3) is a '0' (Busy) when Flash memory is being written to, or when Flash memory is being erased. The output is a '1' (Ready) when no WRITE or Erase cycle is in progress. 22.2.2 Memory operation The primary Flash memory and secondary Flash memory are addressed through the MCU Bus. The MCU can access these memories in one of two ways: 112/189 ● The MCU can execute a typical bus WRITE or READ operation. ● The MCU can execute a specific Flash memory instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in Table 85. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Memory blocks Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM device. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte directly to Flash memory as it would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a READ operation or polling Ready/Busy (PC3). 22.3 Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD module and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations. The instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into READ mode (Flash memory is read like a ROM device). The Flash memory supports the instructions summarized in Table 85: ● Erase memory by chip or sector ● Suspend or resume sector erase ● Program a Byte ● RESET to READ mode ● Read Sector Protection Status ● Bypass These instructions are detailed in Table 85. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address signals A15-A12 are Don’t Care during the instruction WRITE cycles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of Sector Select (FS0-FS7) is High, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0-CSBOOT3) is High. Table 85. Instructions FS0-FS7 or CSBOOT0CSBOOT3 Cycle 1 READ(5) 1 “Read” RD @ RA READ Sector Protection(6,8,13) 1 AAh@ X555h Instruction Cycle 2 55h@ XAAAh Cycle 3 90h@ X555h Cycle 4 Cycle 5 Cycle 6 Cycle 7 Read status @ XX02h 113/189 Memory blocks Table 85. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Instructions (continued) Instruction FS0-FS7 or CSBOOT0CSBOOT3 Program a Flash Byte(13) 1 AAh@ X555h 55h@ XAAAh A0h@ X555h PD@ PA Flash Sector Erase(7,13) 1 AAh@ X555h 55h@ XAAAh 80h@ X555h AAh@ X555h 55h@ XAAAh 30h@ SA Flash Bulk Erase(13) 1 AAh@ X555h 55h@ XAAAh 80h@ X555h AAh@ X555h 55h@ XAAAh 10h@ X555h Suspend Sector Erase(11) 1 B0h@ XXXXh Resume Sector Erase(12) 1 30h@ XXXXh RESET(6) 1 F0h@ XXXXh Unlock Bypass 1 AAh@ X555h 55h@ XAAAh 20h@ X555h Unlock Bypass Program(9) 1 A0h@ XXXXh PD@ PA Unlock Bypass Reset(10) 1 90h@ XXXXh 00h@ XXXXh Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 30h7@ next SA 1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label 2. All values are in hexadecimal. 3. X = Don’t care. Addresses of the form XXXXh, in this table, must be even addresses 4. RA = Address of the memory location to be read 5. RD = Data READ from location RA during the READ cycle 6. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR, CNTL0). 7. PA is an even address for PSD in Word Programming mode. 8. PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe (WR, CNTL0) 9. SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (High). 10. Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft Express. 11. Only address Bits A11-A0 are used in instruction decoding. 12. No Unlock or instruction cycles are required when the device is in the READ mode 13. The RESET instruction is required to return to the READ mode after reading the Sector Protection Status, or if the Error flag bit (DQ5/DQ13) goes High. 14. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs. 15. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0) 16. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 17. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. 18. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 19. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 114/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Memory blocks 20. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 22.4 Power-down instruction and Power-up mode 22.4.1 Power-up mode The PSD module internal logic is reset upon Power-up to the READ mode. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must be held Low, and WRITE Strobe (WR, CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of WRITE Strobe (WR, CNTL0). Any WRITE cycle initiation is locked when VCC is below VLKO. 22.5 Read Under typical conditions, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions. 22.5.1 Read memory contents Primary Flash memory and secondary Flash memory are placed in the READ mode after Power-up, chip reset, or a Reset Flash instruction (see Table 85). The MCU can read the memory contents of the primary Flash memory or the secondary Flash memory by using READ operations any time the READ operation is not part of an instruction. 22.5.2 Read memory sector protection status The primary Flash memory Sector Protection Status is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 85). During the READ operation, address Bits A6, A1, and A0 must be '0,' '1,' and '0,' respectively, while Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be verified. The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory or secondary Flash memory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O space. See Section 22.8.1: Flash memory sector protect for register definitions. 22.5.3 Reading the Erase/Program status bits The Flash memory provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 86. The status bits can be read as many times as needed. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See Section 22.6: Programming Flash memory, for details. 115/189 Memory blocks 22.5.4 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Data polling flag (DQ7) When erasing or programming in Flash memory, the Data Polling flag bit (DQ7) outputs the complement of the bit being entered for programming/writing on the DQ7 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling flag bit (DQ7) (in a READ operation). 22.5.5 ● Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. ● During an Erase cycle, the Data Polling flag bit (DQ7) outputs a '0.' After completion of the cycle, the Data Polling flag bit (DQ7) outputs the last bit programmed (it is a '1' after erasing). ● If the byte to be programmed is in a protected Flash memory sector, the instruction is ignored. ● If all the Flash memory sectors to be erased are protected, the Data Polling flag bit (DQ7) is reset to '0' for about 100µs, and then returns to the previous addressed byte. No erasure is performed. Toggle flag (DQ6) The Flash memory offers another way for determining when the Program cycle is completed. During the internal WRITE operation and when either the FS0-FS7 or CSBOOT0-CSBOOT3 is true, the Toggle flag bit (DQ6) toggles from '0' to '1' and '1' to '0' on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling stops and the data READ on the Data Bus D0-D7 is the addressed memory byte. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive Reads yield the same output data. 22.5.6 ● The Toggle flag bit (DQ6) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). ● If the byte to be programmed belongs to a protected Flash memory sector, the instruction is ignored. ● If all the Flash memory sectors selected for erasure are protected, the Toggle flag bit (DQ6) toggles to '0' for about 100µs and then returns to the previous addressed byte. Error flag (DQ5) During a normal Program or Erase cycle, the Error flag bit (DQ5) is to '0.' This bit is set to '1' when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error flag bit (DQ5) indicates the attempt to program a Flash memory bit from the programmed state, '0', to the erased state, '1,' which is not valid. The Error flag bit (DQ5) may also indicate a Time-out condition while attempting to program a byte. In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag bit (DQ5) is reset after a Reset Flash instruction. 116/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 22.5.7 Memory blocks Erase time-out flag (DQ3) The Erase Time-out Flag bit (DQ3) reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase Time-out Flag bit (DQ3) is reset to '0' after a Sector Erase cycle for a time period of 100µs + 20% unless an additional Sector Erase instruction is decoded. After this time period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag bit (DQ3) is set to ‘1’. Table 86. Status bit Functional Block FS0-FS7/ CSBOOT0CSBOOT3 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Flash Memory VIH Data Polling Toggle Flag Error Flag X Erase Time-out X X X 1. X = Not guaranteed value, can be read either '1' or '0.' 2. DQ7-DQ0 represent the Data Bus bits, D7-D0. 3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High. 22.6 Programming Flash memory Flash memory must be erased prior to being programmed. A byte of Flash memory is erased to all '1's (FFh), and is programmed by setting selected bits to '0'. The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. However, the MCU may program Flash memory byte-by-byte. The primary and secondary Flash memories require the MCU to send an instruction to program a byte or to erase sectors (see Table 85). Once the MCU issues a Flash memory Program or Erase instruction, it must check for the status bits for completion. The embedded algorithms that are invoked support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PC3). 22.6.1 Data Polling Polling on the Data Polling Flag bit (DQ7) is a method of checking whether a Program or Erase cycle is in progress or has completed. Figure 51 shows the Data Polling algorithm. When the MCU issues a Program instruction, the embedded algorithm begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Data Polling Flag bit (DQ7) of this location becomes the complement of b7 of the original data byte to be programmed. The MCU continues to poll this location, comparing the Data Polling Flag bit (DQ7) and monitoring the Error Flag bit (DQ5). When the Data Polling Flag bit (DQ7) matches b7 of the original data, and the Error Flag bit (DQ5) remains '0,' the embedded algorithm is complete. If the Error Flag bit (DQ5) is '1,' the MCU should test the Data Polling Flag bit (DQ7) again since the Data Polling Flag bit (DQ7) may have changed simultaneously with the Error Flag bit (DQ5) (see Figure 51). The Error Flag bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). 117/189 Memory blocks UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to the Flash memory with the byte that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 51 still applies. However, the Data Polling Flag bit (DQ7) is '0' until the Erase cycle is complete. A '1' on the Error Flag bit (DQ5) indicates a time-out condition on the Erase cycle; a '0' indicates no error. The MCU can read any location within the sector being erased to get the Data Polling Flag bit (DQ7) and the Error Flag bit (DQ5). PSDsoft Express generates ANSI C code functions which implement these Data Polling algorithms. Figure 51. Data polling flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA YES NO NO DQ5 =1 YES READ DQ7 DQ7 = DATA YES NO FAIL PASS AI01369B 22.6.2 Data toggle Checking the Toggle Flag bit (DQ6) is a method of determining whether a Program or Erase cycle is in progress or has completed. Figure 52 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Toggle Flag bit (DQ6) of this location toggles each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking the Toggle Flag bit (DQ6) and monitoring the Error Flag bit (DQ5). When the Toggle Flag bit (DQ6) stops toggling (two consecutive reads yield the same value), and the Error Flag bit (DQ5) remains '0,' the embedded algorithm is complete. If the Error Flag bit (DQ5) is '1,' the MCU should test the Toggle Flag bit (DQ6) again, since the Toggle Flag bit (DQ6) may have changed simultaneously with the Error Flag bit (DQ5) (see Figure 52). The Error Flag bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). 118/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Memory blocks It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to Flash memory with the byte that was intended to be written. When using the Data Toggle method after an Erase cycle, Figure 52 still applies. the Toggle Flag bit (DQ6) toggles until the Erase cycle is complete. A 1 on the Error Flag bit (DQ5) indicates a time-out condition on the Erase cycle; a '0' indicates no error. The MCU can read any location within the sector being erased to get the Toggle Flag bit (DQ6) and the Error Flag bit (DQ5). PSDsoft Express generates ANSI C code functions which implement these Data Toggling algorithms. Figure 52. Data toggle flowchart START READ DQ5 & DQ6 DQ6 = TOGGLE NO YES NO DQ5 =1 YES READ DQ6 DQ6 = TOGGLE NO YES FAIL PASS AI01370B 22.6.3 Unlock Bypass The Unlock Bypass instructions allow the system to program bytes to the Flash memories faster than using the standard Program instruction. The Unlock Bypass mode is entered by first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unlock Bypass code, 20h (as shown in Table 85). The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. These instructions dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total Flash memory programming. During the Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset Flash instructions are valid. 119/189 Memory blocks UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset Flash instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are Don’t Care for both cycles. The Flash memory then returns to READ mode. 22.7 Erasing Flash memory 22.7.1 Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 85. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the READ Flash memory status. During a Bulk Erase, the memory status may be checked by reading the Error Flag bit (DQ5), the Toggle Flag bit (DQ6), and the Data Polling Flag bit (DQ7), as detailed in Section 22.6: Programming Flash memory. The Error Flag bit (DQ5) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed). It is not necessary to program the memory with 00h because the PSD module automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions. 22.7.2 Flash Sector Erase The Sector Erase instruction uses six WRITE operations, as described in Table 85. Additional Flash Sector Erase codes and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than the time-out period of about 100µs. The input of a new Sector Erase code restarts the time-out period. The status of the internal timer can be monitored through the level of the Erase Time-out Flag bit (DQ3). If the Erase Time-out Flag bit (DQ3) is '0,' the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag bit (DQ3) is '1,' the time-out period has expired and the embedded algorithm is busy erasing the Flash memory sector(s). Before and during Erase time-out, any instruction other than Suspend Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in progress, and reset the device to READ mode. During a Sector Erase, the memory status may be checked by reading the Error Flag bit (DQ5), the Toggle Flag bit (DQ6), and the Data Polling Flag bit (DQ7), as detailed in Section 22.6: Programming Flash memory. During execution of the Erase cycle, the Flash memory accepts only RESET and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. 22.7.3 Suspend Sector Erase When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any address when an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 85). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. 120/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Memory blocks Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ mode. A Suspend Sector Erase instruction executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle Flag bit (DQ6) stops toggling when the internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag bit (DQ6) stops toggling between 0.1µs and 15µs after the Suspend Sector Erase instruction has been executed. The Flash memory is then automatically set to READ mode. If an Suspend Sector Erase instruction was executed, the following rules apply: 22.7.4 ● Attempting to read from a Flash memory sector that was being erased outputs invalid data. ● Reading from a Flash sector that was not being erased is valid. ● The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset Flash instructions (READ is an operation and is allowed). ● If a Reset Flash instruction is received, data in the Flash memory sector that was being erased is invalid. Resume Sector Erase If a Suspend Sector Erase instruction was previously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 85.) 22.8 Specific features 22.8.1 Flash memory sector protect Each primary and secondary Flash memory sector can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated through the JTAG Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft Express Configuration program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The MCU can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash memory protection registers (in the CSIOP block). See Table 87 and Table 88. 121/189 Memory blocks UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 87. Sector protection/security bit definition – Flash protection register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot 1. Bit Definitions: Sec_Prot Sec_Prot Table 88. 1 = Primary Flash memory or secondary Flash memory Sector is write-protected. 0 = Primary Flash memory or secondary Flash memory Sector is not write-protected. Sector protection/security bit definition – secondary Flash protection register Bit 7 Bit 6 Bit 5 Bit 4 Security_B it Not used Not used Not used 1. Bit Definitions: Sec_Prot Sec_Prot Security_Bit 22.8.2 Bit 3 Bit 2 Bit 1 Bit 0 Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot 1 = Secondary Flash memory Sector is write-protected. 0 = Secondary Flash memory Sector is not write-protected. 0 = Security Bit in device has not been set; 1 = Security Bit in device has been set. Reset Flash The Reset Flash instruction consists of one WRITE cycle (see Table 85). It can also be optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and 55h to AAAh). It must be executed after: ● Reading the Flash Protection Status or Flash ID ● An Error condition has occurred (and the device has set the Error Flag bit (DQ5) to '1' during a Flash memory Program or Erase cycle. The Reset Flash instruction puts the Flash memory back into normal READ mode. If an Error condition has occurred (and the device has set the Error Flag bit (DQ5) to '1' the Flash memory is put back into normal READ mode within 25µs of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ mode within 25µs. 22.8.3 Reset (RESET) signal A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash memory to the READ mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25μs to return to the READ mode. It is recommended that the Reset (RESET) pulse (except for Power-on RESET, as described in Section 26: RESET timing and device status at reset) be at least 25µs so that the Flash memory is always ready for the MCU to retreive the bootstrap instructions after the reset cycle is complete. 22.9 SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. 122/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 22.10 Memory blocks Sector Select and SRAM Select Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDsoft Express. The following rules apply to the equations for these signals: 22.10.1 1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size. 2. Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector. 3. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O. Example FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Note: An equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 53 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest. 22.10.2 Memory Select configuration in Program and Data spaces The MCU Core has separate address spaces for Program memory and Data memory. Any of the memories within the PSD module can reside in either space or both spaces. This is controlled through manipulation of the VM Register that resides in the CSIOP space. The VM Register is set using PSDsoft Express to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the primary and secondary Flash memories. This is easily done with the VM Register by using PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it when desired. Table 89 describes the VM Register. 123/189 Memory blocks UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 53. Priority level of memory and I/O components in the PSD module Highest Priority Level 1 SRAM, I/O, or Peripheral I/O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority Table 89. Bit 7 PIO_EN 0= disable PIO mode 1= enable PIO mode 22.10.3 AI02867D VM register Bit 4 Bit 6 not used not used Bit 5 Primary FL_Data not used 0 = RD can’t access Flash memory not used 1 = RD access Flash memory Bit 3 Secondary Data Bit 2 Primary FL_Cod e Bit 1 Bit 0 Secondary Code SRAM_Co de 0 = RD can’t access Secondary Flash memory 0= PSEN can’t access Flash memory 0 = PSEN can’t access Secondary Flash memory 0 = PSEN can’t access SRAM 1 = RD access Secondary Flash memory 1= PSEN access Flash memory 1 = PSEN access Secondary Flash memory 1 = PSEN access SRAM Separate Space mode Program space is separated from Data space. For example, Program Select Enable (PSEN) is used to access the program code from the primary Flash memory, while READ Strobe (RD) is used to access data from the secondary Flash memory, SRAM and I/O Port blocks. This configuration requires the VM Register to be set to 0Ch (see Figure 54). 22.10.4 Combined Space modes The Program and Data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN) or READ Strobe (RD). For example, to configure the primary Flash memory in Combined space, Bits b2 and b4 of the VM Register are set to '1' (see Figure 55). 124/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Memory blocks Figure 54. Separate Space mode DPLD Primary Flash Memory RS0 Secondary Flash Memory SRAM CSBOOT0-3 FS0-FS7 CS CS OE CS OE OE PSEN RD AI02869C Figure 55. Combined Space mode DPLD RD RS0 Secondary Flash Memory Primary Flash Memory SRAM CSBOOT0-3 FS0-FS7 CS CS OE CS OE OE VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 RD VM REG BIT 0 AI02870C 22.11 Page register The 8-bit Page Register increases the addressing capability of the MCU Core by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic. Figure 56 shows the Page Register. The eight flip-flops in the register are connected to the internal data bus D0-D7. The MCU can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h. 125/189 Memory blocks UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 56. Page register RESET D0 - D 7 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 PGR0 INTERNAL PSD MODULE SELECTS AND LOGIC PGR1 PGR2 PGR3 PGR4 DPLD AND CPLD PGR5 PGR6 PGR7 R/W PAGE REGISTER 126/189 PLD AI05799 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 23 PLDs PLDs PLDs bring programmable logic functionality to the UPSD. After specifying the logic for the PLDs using PSDsoft Express, the logic is programmed into the device and available upon Power-up. Table 90. DPLD and CPLD Inputs Input Source Input Name Number of Signals MCU Address Bus A15-A0 16 MCU Control Signals PSEN, RD, WR, ALE 4 RESET RST 1 PDN 1 PA7-PA0 8 Port B Input Macrocells PB7-PB0 8 Port C Input Macrocells PC2-4, PC7 4 Port D Inputs PD2-PD1 2 Page Register PGR7-PGR0 8 Macrocell AB Feedback MCELLAB.FB7-FB0 8 Macrocell BC Feedback MCELLBC.FB7-FB0 8 Flash memory Program Status bit Ready/Busy 1 Power-down Port A Input Macrocells(1) Note: 1. These inputs are not available in the 52-pin package. The PSD module contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in Section 23.2: Decode PLD (DPLD), and Section 23.3: Complex PLD (CPLD). Figure 57 shows the configuration of the PLDs. The DPLD performs address decoding for Select signals for PSD module components, such as memory, registers, and I/O ports. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the Output Macrocells (OMC), Input Macrocells (IMC), and the AND Array. The CPLD can also be used to generate External Chip Select (ECS1-ECS2) signals. The AND Array is used to form product terms. These product terms are specified using PSDsoft. The PLD input signals consist of internal MCU signals and external inputs from the I/O ports. The input signals are shown in Table 90. 23.1 Turbo bit in PSD module The PLDs can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70ns. Resetting the Turbo bit to '0' (Bit 3 of PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while reducing power consumption. 127/189 PLDs UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV See Section 25: Power management for details on how to set the Turbo Bit. Additionally, five bits are available in PMMR2 to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections. Figure 57. PLD diagram 8 PAGE REGISTER DECODE PLD 73 8 PRIMARY FLASH MEMORY SELECTS 4 SECONDARY NON-VOLATILE MEMORY SELECTS 1 SRAM SELECT 1 CSIOP SELECT PLD INPUT BUS 2 16 PERIPHERAL SELECTS DIRECT MACROCELL ACCESS FROM MCU DATA BUS OUTPUT MACROCELL FEEDBACK CPLD 16 OUTPUT MACROCELL PT ALLOC. 73 MACROCELL ALLOC. 20 INPUT MACROCELL (PORT A,B,C) I/O PORTS DATA BUS MCELLAB TO PORT A OR B1 8 MCELLBC TO PORT B OR C 8 2 EXTERNAL CHIP SELECTS TO PORT D DIRECT MACROCELL INPUT TO MCU DATA BUS 20 INPUT MACROCELL & INPUT PORTS 2 PORT D INPUTS AI06600 1. Port A is not available in the 52-pin package 23.2 Decode PLD (DPLD) The DPLD, shown in Figure 91, is used for decoding the address for PSD module and external components. The DPLD can be used to generate the following decode signals: 128/189 ● 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) ● 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) ● 1 internal SRAM Select (RS0) signal (two product terms) ● 1 internal CSIOP Select signal (selects the PSD module registers) ● 2 internal Peripheral Select signals (Peripheral I/O mode). UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 91. PLDs DPLD logic array (INPUTS) I /O PORTS (PORT A,B,C)1 3 CSBOOT 0 3 CSBOOT 1 3 CSBOOT 2 3 CSBOOT 3 3 FS0 (20) 3 MCELLAB.FB [7:0] (FEEDBACKS) FS1 (8) 3 MCELLBC.FB [7:0] (FEEDBACKS) FS2 (8) 3 PGR0 - PGR7 FS3 (8) 3 A[15:0]2 FS4 (16) 3 FS5 (2) PD[2:1] 3 PDN (APD OUTPUT) FS6 (1) 3 PSEN, RD, WR, ALE2 FS7 (4) 2 (1) RD_BSY (1) RESET 8 PRIMARY FLASH MEMORY SECTOR SELECTS 2 RS0 1 CSIOP 1 PSEL0 1 PSEL1 SRAM SELECT I/O DECODER SELECT PERIPHERAL I/O MODE SELECT AI06601 1. Port A inputs are not available in the 52-pin package 2. Inputs from the MCU module 23.3 Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate External Chip Select (ECS1-ECS2), routed to Port D. Although External Chip Select (ECS1-ECS2) can be produced by any Output Macrocell (OMC), these External Chip Select (ECS1-ECS2) on Port D do not consume any Output Macrocells (OMC). As shown in Figure 58, the CPLD has the following blocks: ● 20 Input Macrocells (IMC) ● 16 Output Macrocells (OMC) ● Macrocell Allocator ● Product Term Allocator ● AND Array capable of generating up to 137 product terms ● Four I/O Ports. Each of the blocks are described in the sections that follow. 129/189 PLDs UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD module internal data bus and can be directly accessed by the MCU. This enables the MCU software to load data into the Output Macrocells (OMC) or read data from both the Input and Output Macrocells (IMC and OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures. Figure 58. Macrocell and I/O ports PLD INPUT BUS PRODUCT TERMS FROM OTHER MACROCELLS MCU ADDRESS / DATA BUS TO OTHER I/O PORTS CPLD MACROCELLS I/O PORTS DATA LOAD CONTROL PT PRESET MCU DATA IN PRODUCT TERM ALLOCATOR LATCHED ADDRESS OUT DATA MCU LOAD I/O PIN D Q MUX POLARITY SELECT MUX AND ARRAY WR UP TO 10 PRODUCT TERMS CPLD OUTPUT PR DI LD D/T MUX PT CLOCK PLD INPUT BUS MACROCELL OUT TO MCU GLOBAL CLOCK CK CL CLOCK SELECT SELECT Q D/T/JK FF SELECT COMB. /REG SELECT CPLD OUTPUT PDR MACROCELL TO I/O PORT ALLOC. INPUT Q DIR REG. D WR PT CLEAR PT OUTPUT ENABLE (OE) MACROCELL FEEDBACK INPUT MACROCELLS MUX I/O PORT INPUT ALE MUX PT INPUT LATCH GATE/CLOCK Q D Q D G AI06602 23.4 Output macrocell (OMC) Eight of the Output Macrocells (OMC) are connected to Ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in PSDsoft, the Macrocell Allocator block assigns it to either Port A or B. The same is true for a McellBC output on Port B or C. Table 92 shows the macrocells and port assignment. The Output Macrocell (OMC) architecture is shown in Figure 59. As shown in the figure, there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other Output Macrocells (OMC). The polarity of the product term is controlled by the XOR gate. The Output Macrocell (OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR type in PSDsoft. The flip-flop’s clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip- 130/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PLDs flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms. Table 92. Output Macrocell Output macrocell port and data bit assignments Port Assignment (1,2) Native Product Terms Max. Borrowed Product Terms Data Bit for Loading or Reading McellAB0 Port A0, B0 3 6 D0 McellAB1 Port A1, B1 3 6 D1 McellAB2 Port A2, B2 3 6 D2 McellAB3 Port A3, B3 3 6 D3 McellAB4 Port A4, B4 3 6 D4 McellAB5 Port A5, B5 3 6 D5 McellAB6 Port A6, B6 3 6 D6 McellAB7 Port A7, B7 3 6 D7 McellBC0 Port B0 4 5 D0 McellBC1 Port B1 4 5 D1 McellBC2 Port B2, C2 4 5 D2 McellBC3 Port B3, C3 4 5 D3 McellBC4 Port B4, C4 4 6 D4 McellBC5 Port B5 4 6 D5 McellBC6 Port B6 4 6 D6 McellBC7 Port B7, C7 4 6 D7 1. McellAB0-McellAB7 can only be assigned to Port B in the 52-pin package 2. Port PC0, PC1, PC5, and PC6 are assigned to JTAG pins and are not available as Macrocell outputs. 23.5 Product term allocator The CPLD has a Product Term Allocator. PSDsoft uses the Product Term Allocator to borrow and place product terms from one macrocell to another. The following list summarizes how product terms are allocated: ● McellAB0-McellAB7 all have three native product terms and may borrow up to six more ● McellBC0-McellBC3 all have four native product terms and may borrow up to five more ● McellBC4-McellBC7 all have four native product terms and may borrow up to six more. Each macrocell may only borrow product terms from certain other macrocells. Product terms already in use by one macrocell are not available for another macrocell. If an equation requires more product terms than are available to it, then “external” product terms are required, which consume other Output Macrocells (OMC). If external product terms are used, extra delay is added for the equation that required the extra product terms. This is called product term expansion. PSDsoft Express performs this expansion as needed. 131/189 PLDs 23.5.1 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Loading and Reading the Output Macrocells (OMC) The Output Macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP block (see Section 24: I/O ports (PSD module)). The flipflops in each of the 16 Output Macrocells (OMC) can be loaded from the data bus by a MCU. Loading the Output Macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data can be loaded to the Output Macrocells (OMC) on the trailing edge of WRITE Strobe (WR, edge loading) or during the time that WRITE Strobe (WR) is active (level loading). The method of loading is specified in PSDsoft Express Configuration. Figure 59. CPLD output macrocell MASK REG. MACROCELL CS MCU DATA BUS D[ 7:0] RD PT ALLOCATOR WR DIRECTION REGISTER ENABLE (.OE) AND ARRAY PLD INPUT BUS PRESET(.PR) COMB/REG SELECT PT PT DIN PR MUX PT LD POLARITY SELECT Q I/O PIN MACROCELL ALLOCATOR IN CLEAR (.RE) CLR PORT DRIVER PROGRAMMABLE FF (D/T/JK /SR) PT CLK MUX CLKIN FEEDBACK (.FB) PORT INPUT INPUT MACROCELL AI06617 23.5.2 OMC mask register There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Output Macrocells (OMC). The default value for the Mask Registers is 00h, which allows loading of the Output Macrocells (OMC). When a given bit in a Mask Register is set to a '1,' the MCU is blocked from writing to the associated Output Macrocells (OMC). For example, suppose McellAB0McellAB3 are being used for a state machine. You would not want a MCU write to McellAB to overwrite the state machine registers. Therefore, you would want to load the Mask Register for McellAB (Mask Macrocell AB) with the value 0Fh. 23.5.3 Output enable of the OMC The Output Macrocells (OMC) block can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the 132/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PLDs AND Array, ORed with the Direction Register output. The pin is enabled upon Power-up if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft Express. If the Output Macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array. Input macrocells (IMC) The CPLD has 20 Input Macrocells (IMC), one for each pin on Ports A and B, and 4 on Port C. The architecture of the Input Macrocells (IMC) is shown in Figure 60. The Input Macrocells (IMC) are individually configurable, and can be used as a latch, register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the Input Macrocells (IMC) can be read by the MCU through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe (ALE). Each product term output is used to latch or clock four Input Macrocells (IMC). Port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the Input Macrocells (IMC) are specified by equations written in PSDsoft (see Application Note AN1171). Outputs of the Input Macrocells (IMC) can be read by the MCU via the IMC buffer. See Section 24: I/O ports (PSD module). Figure 60. Input macrocell MCU DATA BUS D[7:0] INPUT MACROCELL _ RD DIRECTION REGISTER ENABLE (.OE) AND ARRAY PT PLD INPUT BUS 23.6 OUTPUT MACROCELLS BC AND MACROCELL AB I/O PIN PT PORT DRIVER MUX Q D PT MUX ALE D FF FEEDBACK Q D G LATCH INPUT MACROCELL AI06603 133/189 I/O ports (PSD module) 24 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV I/O ports (PSD module) There are four programmable I/O ports: Ports A, B, C, and D in the PSD module. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express Configuration or by the MCU writing to on-chip registers in the CSIOP space. Port A is not available in the 52-pin package. The topics discussed in this section are: 24.1 ● General Port architecture ● Port operating modes ● Port Configuration Registers (PCR) ● Port Data Registers ● Individual Port functionality. General port architecture The general architecture of the I/O Port block is shown in Figure 61. Individual Port architectures are shown in Figure 63 to Figure 66. In general, once the purpose for a port pin has been defined, that pin is no longer available for other purposes. Exceptions are noted. As shown in Figure 61, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft Express Configuration. Inputs to the multiplexer include the following: ● Output data from the Data Out register ● Latched address outputs ● CPLD macrocell output ● External Chip Select (ECS1-ECS2) from the CPLD. The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and can be read by the MCU. The Data Out and macrocell outputs, Direction and Control Registers, and port pin input are all connected to the Port Data Buffer (PDB). 134/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV I/O ports (PSD module) Figure 61. General I/O port architecture DATA OUT REG. D Q D Q DATA OUT WR ADDRESS ALE ADDRESS PORT PIN OUTPUT MUX G MACROCELL OUTPUTS EXT CS READ MUX MCU DATA BUS P OUTPUT SELECT D DATA IN B CONTROL REG. D Q ENABLE OUT WR DIR REG. D Q WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD-INPUT AI06604 The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDsoft, then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers. Ports A, B, and C have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE) or a product term from the PLD AND Array. The outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the MCU. See Figure 60. 24.2 Port operating modes The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft, some by the MCU writing to the Control Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input, and Peripheral I/O modes are the only modes that must be defined before programming the device. All other modes can be changed by the MCU at run-time. See Application Note AN1171 for more detail. Table 93 summarizes which modes are available on each port. Table 96 shows how and where the different modes are configured. Each of the port operating modes are described in the following sections. 135/189 I/O ports (PSD module) 24.3 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV MCU I/O mode In the MCU I/O mode, the MCU uses the I/O Ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD module are mapped into the MCU address space. The addresses of the ports are listed in Table 84. A port pin can be put into MCU I/O mode by writing a '0' to the corresponding bit in the Control Register. The MCU I/O direction may be changed by writing to the corresponding bit in the Direction Register, or by the output enable product term. See Section 24.6: Peripheral I/O mode. When the pin is configured as an output, the content of the Data Out Register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer. See Figure 61. Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They can be used for PLD I/O if equations are written for them in PSDabel. 24.4 PLD I/O mode The PLD I/O mode uses a port as an input to the CPLD’s Input Macrocells (IMC), and/or as an output from the CPLD’s Output Macrocells (OMC). The output can be tri-stated with a control signal. This output enable control signal can be defined by a product term from the PLD, or by resetting the corresponding bit in the Direction Register to '0.' The corresponding bit in the Direction Register must not be set to '1' if the pin is defined for a PLD input signal in PSDsoft. The PLD I/O mode is specified in PSDsoft by declaring the port pins, and then writing an equation assigning the PLD I/O to a port. 24.5 Address Out mode Address Out mode can be used to drive latched MCU addresses on to the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction Register and Control Register must be set to a '1' for pins to use Address Out mode. This must be done by the MCU at run-time. See Table 95 for the address output pin assignments on Ports A and B for various MCUs. 24.6 Peripheral I/O mode Peripheral I/O mode can be used to interface with external peripherals. In this mode, all of Port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is enabled by setting Bit 7 of the VM Register to a '1.' Figure 62 shows how Port A acts as a bidirectional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for PSEL0 and/or PSEL1 must be written in PSDsoft. The buffer is tri-stated when PSEL0 or PSEL1 is low (not active). The PSEN signal should be “ANDed” in the PSEL equations to disable the buffer when PSEL resides in the data space. 24.7 JTAG in-system programming (ISP) Port C is JTAG compliant, and can be used for In-System Programming (ISP). For more information on the JTAG Port, see Section 27: Programming in-circuit using the JTAG serial interface. 136/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV I/O ports (PSD module) Figure 62. Peripheral I/O mode RD PSEL0 PSEL PSEL1 D0 - D7 VM REGISTER BIT 7 PA0 - PA7 DATA BUS WR AI02886 Table 93. Port operating modes Port A(1) Port B Port C Port D Yes Yes Yes Yes Yes No No Yes Yes No No Yes(2) No No No Yes Yes Yes Yes Yes Address Out Yes (A7 – 0) Yes (A7 – 0) No No Peripheral I/O Yes No No No Port mode MCU I/O PLD I/O McellAB Outputs McellBC Outputs Additional Ext. CS Outputs PLD Inputs JTAG ISP No (3) No No Yes 1. Port A is not available in the 52-pin package. 2. On pins PC2, PC3, PC4, and PC7 only. 3. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins. Table 94. Port operating mode settings Mode Control Register Setting(1) Defined in PSDsoft Direction Register Setting(1) VM Register Setting(1) MCU I/O Declare pins only 0 1 = output, 0 = input (Note 2) N/A PLD I/O Logic equations N/A (Note 2) N/A Address Out (Port A,B) Declare pins only 1 1 (Note 2) N/A Peripheral I/O (Port A) Logic equations (PSEL0 & 1) N/A N/A PIO Bit = 1 1. N/A = Not Applicable 2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product term (.oe) from the CPLD AND Array. Table 95. I/O port latched address output assignments Port A (PA3-PA0) Port A (PA7-PA4) Port B (PB3-PB0) Port B (PB7-PB4) Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4 137/189 I/O ports (PSD module) 24.8 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Port configuration registers (PCR) Each Port has a set of Port Configuration Registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in Table 84. The addresses in Table 84 are the offsets in hexadecimal from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three Port Configuration Registers (PCR), shown in Table 96, are used for setting the Port configurations. The default Power-up state for each register in Table 96 is 00h. 24.8.1 Control register Any bit reset to '0' in the Control Register sets the corresponding port pin to MCU I/O mode, and a '1' sets it to Address Out mode. The default mode is MCU I/O. Only Ports A and B have an associated Control Register. 24.8.2 Direction register The Direction Register, in conjunction with the output enable (except for Port D), controls the direction of data flow in the I/O Ports. Any bit set to '1' in the Direction Register causes the corresponding pin to be an output, and any bit set to '0' causes it to be an input. The default mode for all port pins is input. Figure 63 and Figure 64 show the Port Architecture diagrams for Ports A/B and C, respectively. The direction of data flow for Ports A, B, and C are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, the Direction Register has sole control of a given pin’s direction. An example of a configuration for a Port with the three least significant bits set to output and the remainder set to input is shown in Table 99. Since Port D only contains two pins (shown in Figure 66), the Direction Register for Port D has only two bits active. 24.8.3 Drive Select register The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a '1.' The default pin drive is CMOS. Note: The slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive Register is set to '1.' The default rate is slow slew. Table 100 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for. 138/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 96. Port configuration registers (PCR) Register Name Port Control Direction Drive Select I/O ports (PSD module) (1) MCU Access A,B WRITE/READ A,B,C,D WRITE/READ A,B,C,D WRITE/READ Note: 1. See Table 100 for Drive Register Bit definition. Table 97. Table 98. Direction Register Bit Port Pin mode 0 Input 1 Output Port pin direction control, output enable P.T. defined Direction Register Bit Output Enable P.T. Port Pin mode 0 0 Input 0 1 Output 1 0 Output 1 1 Output Table 99. 24.9 Port pin direction control, output enable P.T. not defined Port direction assignment example Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 1 1 1 Port data registers The Port Data Registers, shown in Table 101, are used by the MCU to write data to or read data from the ports. Table 101 shows the register name, the ports having each register type, and MCU access for each register type. The registers are described below. 24.9.1 Data In Port pins are connected directly to the Data In buffer. In MCU I/O Input mode, the pin input is read through the Data In buffer. 24.9.2 Data Out register Stores output data written by the MCU in the MCU I/O Output mode. The contents of the Register are driven out to the pins if the Direction Register or the output enable product term is set to '1.' The contents of the register can also be read back by the MCU. 24.9.3 Output macrocells (OMC) The CPLD Output Macrocells (OMC) occupy a location in the MCU’s address space. The MCU can read the output of the Output Macrocells (OMC). If the OMC Mask Register Bits 139/189 I/O ports (PSD module) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV are not set, writing to the macrocell loads data to the macrocell flip-flops. See Section 23: PLDs. 24.9.4 OMC mask register Each OMC Mask Register Bit corresponds to an Output Macrocell (OMC) flip-flop. When the OMC Mask Register Bit is set to a '1,' loading data into the Output Macrocell (OMC) flip-flop is blocked. The default value is '0' or unblocked. 24.9.5 Input macrocells (IMC) The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See Section 23: PLDs. 24.9.6 Enable out The Enable Out register can be read by the MCU. It contains the output enable values for a given port. A '1' indicates the driver is in output mode. A '0' indicates the driver is in tri-state and the pin is in input mode. Table 100. Drive register pin assignment Drive Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port A Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Slew Rate Slew Rate Port B Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Slew Rate Slew Rate Port C Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Port D NA(1) NA(1) NA(1) NA(1) NA(1) Slew Rate Slew Rate NA(1) 1. NA = Not Applicable. Table 101. Port data registers Register Name 140/189 Port MCU Access Data In A,B,C,D READ – input on pin Data Out A,B,C,D WRITE/READ Output Macrocell A,B,C READ – outputs of macrocells WRITE – loading macrocells flip-flop Mask Macrocell A,B,C WRITE/READ – prevents loading into a given macrocell Input Macrocell A,B,C READ – outputs of the Input Macrocells Enable Out A,B,C READ – the output enable control of the port driver UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 24.10 I/O ports (PSD module) Ports A and B – functionality and structure Ports A and B have similar functionality and structure, as shown in Figure 63. The two ports can be configured to perform one or more of the following functions: ● MCU I/O mode ● CPLD Output – Macrocells McellAB7-McellAB0 can be connected to Port A or Port B. McellBC7-McellBC0 can be connected to Port B or Port C. ● CPLD Input – Via the Input Macrocells (IMC). ● Latched Address output – Provide latched address output as per Table 95. ● Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain mode. ● Peripheral mode – Port A only (80-pin package) Figure 63. Port A and Port B structure DATA OUT REG. D Q D Q DATA OUT WR ADDRESS ALE PORT A OR B PIN ADDRESS A[ 7:0] G OUTPUT MUX MACROCELL OUTPUTS READ MUX MCU DATA BUS P OUTPUT SELECT D DATA IN B CONTROL REG. D Q ENABLE OUT WR DIR REG. D Q WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD- INPUT AI06605 24.11 Port C – functionality and structure Port C can be configured to perform one or more of the following functions (see Figure 64): ● MCU I/O mode ● CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C. ● CPLD Input – via the Input Macrocells (IMC) ● In-System Programming (ISP) – JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins for device programming. (See Section 27: Programming in-circuit using the JTAG serial interface, for more information on JTAG programming.) ● Open Drain – Port C pins can be configured in Open Drain mode Port C does not support Address Out mode, and therefore no Control Register is required. 141/189 I/O ports (PSD module) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 64. Port C structure DATA OUT REG. D DATA OUT Q WR SPECIAL FUNCTION PORT C PIN 1 OUTPUT MUX MCELLBC[ 7:0] MCU DATA BUS READ MUX P OUTPUT SELECT D DATA IN B ENABLE OUT DIR REG. D Q WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD - INPUT SPECIAL FUNCTION 1 CONFIGURATION BIT AI06618 Note: 1. ISP 24.12 Port D – functionality and structure Port D has two I/O pins (only one pin, PD1, in the 52-pin package). See Figure 65 and Figure 66. This port does not support Address Out mode, and therefore no Control Register is required. Of the eight bits in the Port D registers, only Bits 2 and 1 are used to configure pins PD2 and PD1. Port D can be configured to perform one or more of the following functions: ● MCU I/O mode ● CPLD Output – External Chip Select (ECS1-ECS2) ● CPLD Input – direct input to the CPLD, no Input Macrocells (IMC) ● Slew rate – pins can be set up for fast slew rate Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions: 142/189 ● CLKIN (PD1) as input to the macrocells flip-flops and APD counter ● PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory, SRAM and CSIOP. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV I/O ports (PSD module) Figure 65. Port D structure DATA OUT REG. DATA OUT D Q WR PORT D PIN OUTPUT MUX ECS[ 2:1] MCU DATA BUS READ MUX OUTPUT SELECT P D DATA IN B ENABLE PRODUCT TERM (.OE) DIR REG. D WR 24.13 Q CPLD-INPUT AI06606 External chip select The CPLD also provides two External Chip Select (ECS1-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS1-ECS2) consists of one product term that can be configured active High or Low. The output enable of the pin is controlled by either the output enable product term or the Direction register. (See Figure 66.) 143/189 I/O ports (PSD module) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 66. Port D external chip select signals ENABLE (.OE) ENABLE (.OE) PT2 DIRECTION REGISTER ECS2 POLARITY BIT 144/189 PD1 PIN ECS1 POLARITY BIT CPLD AND ARRAY PLD INPUT BUS PT1 DIRECTION REGISTER PD2 PIN AI06607 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 25 Power management Power management All PSD modules offer configurable power saving options. These options may be used individually or in combinations, as follows: ● The primary and secondary Flash memory, and SRAM blocks are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into Standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory “wakes up,” changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve Memory Standby mode when no inputs are changing—it happens automatically. ● The PLD sections can also achieve Standby mode when its inputs are not changing, as described in the sections on the Power Management mode Registers (PMMR). ● As with the Power Management mode, the Automatic Power Down (APD) block allows the PSD module to reduce to Standby current automatically. The APD Unit can also block MCU address/data signals from reaching the memories and PLDs. ● Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD Unit initiates Power-down mode (if enabled). Once in Power-down mode, all address/data signals are blocked from reaching memory and PLDs, and the memories are deselected internally. This allows the memory and PLDs to remain in Standby mode even if the address/data signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of Standby mode, but not the memories. ● PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories, placing them in Standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD Unit. There is a slight penalty in memory access time when PSD Chip Select Input (CSI, PD2) makes its initial transition from deselected to selected. ● The PMMRs can be written by the MCU at run-time to manage power. The PSD module supports “blocking bits” in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure Figure 70 and Figure 71). Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations. 145/189 Power management UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 67. APD unit APD EN PMMR0 BIT 1=1 TRANSITION DETECTION DISABLE BUS INTERFACE ALE CLR PD CSIOP SELECT APD COUNTER RESET FLASH SELECT EDGE DETECT CSI CLKIN PD PLD SRAM SELECT POWER DOWN (PDN) SELECT DISABLE FLASH/SRAM AI06608 The PSD module has a Turbo Bit in PMMR0. This bit can be set to turn the Turbo mode off (the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo mode is on. When the Turbo mode is on, there is a significant DC current component and the AC component is higher. Automatic Power-down (APD) Unit and Power-down mode The APD Unit, shown in Figure 67, puts the PSD module into Power-down mode by monitoring the activity of Address Strobe (ALE). If the APD Unit is enabled, as soon as activity on Address Strobe (ALE) stops, a four-bit counter starts counting. If Address Strobe (ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down (PDN) goes High, and the PSD module enters Power-down mode, as discussed next. Power-down mode By default, if you enable the APD Unit, Power-down mode is automatically enabled. The device enters Power-down mode if Address Strobe (ALE) remains inactive for fifteen periods of CLKIN (PD1). The following should be kept in mind when the PSD module is in Power-down mode: Note: 146/189 ● If Address Strobe (ALE) starts pulsing again, the PSD module returns to normal Operating mode. The PSD module also returns to normal Operating mode if either PSD Chip Select Input (CSI, PD2) is Low or the RESET input is High. ● The MCU address/data bus is blocked from all memory and PLDs. ● Various signals can be blocked (prior to Power-down mode) from entering the PLDs by setting the appropriate bits in the PMMR registers. The blocked signals include MCU control signals and the common CLKIN (PD1). Blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit. ● All memories enter Standby mode and are drawing standby current. However, the PLD and I/O ports blocks do not go into Standby mode because you don’t want to have to wait for the logic and I/O to “wake-up” before their outputs can change. See Table 102 for Power-down mode effects on PSD module ports. ● Typical standby current is of the order of microamperes. These standby current values assume that there are no transitions on any PLD input. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Power management Other power-saving options The PSD module offers other reduced power saving options that are independent of the Power-down mode. Except for the PSD Chip Select Input (CSI, PD2) features, they are enabled by setting bits in PMMR0 and PMMR2. Figure 68. Enable Power-down flowchart RESET Enable APD Set PMMR0 Bit 1 = 1 OPTIONAL Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits 2 through 6. No ALE idle for 15 CLKIN clocks? Yes PSD Module in Power Down Mode AI06609 Table 102. Power-down mode’s effect on ports Port Function 25.1 Pin Level MCU I/O No Change PLD Out No Change Address Out Undefined Peripheral I/O Tri-State PLD power management The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified Standby current when the inputs are not switching for an extended time of 70 ns. The propagation delay time is increased by 10 ns (for a 5 V device) after the Turbo Bit is set to '1' (turned off) when the inputs change at a composite frequency of less than 15MHz. When the Turbo Bit is reset to '0' (turned on), the PLDs run at full power and speed. The Turbo Bit affects the PLD’s DC power, AC power, and propagation delay. When the Turbo mode is off, the UPSD323xx devices’ input clock frequency is reduced by 5 MHz from the maximum rated clock frequency. Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power consumption. 147/189 Power management 25.2 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PSD chip select input (CSI, PD2) PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select Input (CSI). When Low, the signal selects and enables the PSD module Flash memory, SRAM, and I/O blocks for READ or WRITE operations. A High on PSD Chip Select Input (CSI, PD2) disables the Flash memory, and SRAM, and reduces power consumption. However, the PLD and I/O signals remain operational when PSD Chip Select Input (CSI, PD2) is High. 25.3 Input clock CLKIN (PD1) can be turned off, to the PLD to save AC power consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output Macrocells (OMC). During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from the PLD AND Array or the Macrocells block by setting Bits 4 or 5 to a '1' in PMMR0. 25.4 Input control signals The PSD module provides the option to turn off the MCU signals (WR, RD, PSEN, and Address Strobe (ALE)) to the PLD to save AC power consumption. These control signals are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting Bits 2, 3, 4, 5, and 6 to a '1' in PMMR2. Table 103. Power management mode registers (PMMR0) Bit 0 X Bit 1 APD Enable Bit 2 Bit 3 Bit 4 Not used, and should be set to zero. 0 = off Automatic Power-down (APD) is disabled. 1 = on Automatic Power-down (APD) is enabled. 0 Not used, and should be set to zero. 0 = on PLD Turbo mode is on 1 = off PLD Turbo mode is off, saving power. UPSD323xx devices operate at 5MHz below the maximum rated clock frequency 0 = on CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN (PD1) Powers-up the PLD when Turbo Bit is '0.' 1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power. PLD Turbo PLD Array clk 0 = on CLKIN (PD1) input to the PLD macrocells is connected. PLD MCell clk 1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero. Bit 5 148/189 X 0 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Power management Table 104. Power management mode registers (PMMR2) Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero. PLD Array WR 0 = on WR input to the PLD AND Array is connected. Bit 2 1 = off WR input to PLD AND Array is disconnected, saving power. PLD Array RD 0 = on RD input to the PLD AND Array is connected. 1 = off RD input to PLD AND Array is disconnected, saving power. PLD Array PSEN 0 = on PSEN input to the PLD AND Array is connected. 1 = off PSEN input to PLD AND Array is disconnected, saving power. PLD Array ALE 0 = on ALE input to the PLD AND Array is connected. 1 = off ALE input to PLD AND Array is disconnected, saving power. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero. Bit 3 Bit 4 Bit 5 1. The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers. Table 105. APD counter operatio APD Enable Bit ALE Level APD Counter 0 X Not Counting 1 Pulsing Not Counting 1 0 or 1 Counting (Generates PDN after 15 Clocks) 149/189 RESET timing and device status at reset 26 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV RESET timing and device status at reset Upon Power-up, the PSD module requires a Reset (RESET) pulse of duration tNLNH-PO after VCC is steady. During this period, the device loads internal configurations, clears some of the registers and sets the Flash memory into operating mode. After the rising edge of Reset (RESET), the PSD module remains in the Reset mode for an additional period, tOPR, before the first memory access is allowed. The Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must all be Low, WRITE Strobe (WR, CNTL0) High, during Poweron RESET for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of WRITE Strobe (WR). Any Flash memory WRITE cycle initiation is prevented automatically when VCC is below VLKO. 26.1 Warm RESET Once the device is up and running, the PSD module can be reset with a pulse of a much shorter duration, tNLNH. The same tOPR period is needed before the device is operational after a Warm RESET. Figure 69 shows the timing of the Power-up and Warm RESET. 26.2 I/O pin, register and PLD status at RESET Table 106 shows the I/O pin, register and PLD status during Power-on RESET, Warm RESET, and Power-down mode. PLD outputs are always valid during Warm RESET, and they are valid in Power-on RESET once the internal Configuration bits are loaded. This loading is completed typically long before the VCC ramps up to operating level. Once the PLD is active, the state of the outputs are determined by the PLD equations. 26.3 Reset of Flash Memory Erase and Program Cycles A Reset (RESET) also resets the internal Flash memory state machine. During a Flash memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the Flash memory to the READ mode within a period of tNLNH-A. Figure 69. Reset (RESET) timing VCC VCC(min) tNLNH-PO Power-On Reset tOPR tNLNH tNLNH-A tOPR Warm Reset RESET AI02866b 150/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV RESET timing and device status at reset Table 106. Status during Power-on RESET, Warm RESET and Power-down mode Port Configuration Power-On RESET Warm RESET MCU I/O Input mode PLD Output Valid after internal PSD configuration bits are Valid loaded Depends on inputs to PLD (addresses are blocked in PD mode) Address Out Tri-stated Tri-stated Not defined Peripheral I/O Tri-stated Tri-stated Tri-stated Register Power-On RESET Input mode Power-down mode Warm RESET Unchanged Power-down mode PMMR0 and PMMR2 Cleared to '0' Unchanged Unchanged Macrocells flip-flop status Cleared to '0' by internal Power-on RESET Depends on .re and .pr equations Depends on .re and .pr equations VM Register Initialized, based on the Initialized, based on the selection in PSDsoft selection in PSDsoft Unchanged Configuration menu Configuration menu All other registers Cleared to '0' (1) Cleared to '0' Unchanged 1. The SR_cod and Periphmode Bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET. 151/189 Programming in-circuit using the JTAG serial interface UPSD3234A, UPSD3234BV, UPSD3233B, 27 Programming in-circuit using the JTAG serial interface The JTAG Serial Interface pins (TMS, TCK, TDI, and TDO) are dedicated pins on Port C (see Table 107). All memory blocks (primary and secondary Flash memory), PLD logic, and PSD module Configuration Register Bits may be programmed through the JTAG Serial Interface block. A blank device can be mounted on a printed circuit board and programmed using JTAG. The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and Erase cycles. By default, on a blank device (as shipped from the factory or after erasure), four pins on Port C are the basic JTAG signals TMS, TCK, TDI, and TDO. 27.1 Standard JTAG Signals At power-up, the standard JTAG pins are inputs, waiting for a JTAG serial command from an external JTAG controller device (such as FlashLINK or Automated Test Equipment). When the enabling command is received, TDO becomes an output and the JTAG channel is fully functional. The same command that enables the JTAG channel may optionally enable the two additional JTAG signals, TSTAT and TERR. The RESET input to the uPS3200 should be active during JTAG programming. The active RESET puts the MCU module into RESET mode while the PSD module is being programmed. See Application Note AN1153 for more details on JTAG In-System Programming (ISP). UPSD323xx devices support JTAG In-System-Configuration (ISC) commands, but not Boundary Scan. The PSDsoft Express software tool and FlashLINK JTAG programming cable implement the JTAG In-System-Configuration (ISC) commands. Table 107. JTAG port signals 27.2 Port C Pin JTAG Signals Description PC0 TMS Mode Select PC1 TCK Clock PC3 TSTAT Status (optional) PC4 TERR Error Flag (optional) PC5 TDI Serial Data In PC6 TDO Serial Data Out JTAG extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status on uPDS signals instead of having to 152/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Programming in-circuit using the JTAG scan the status out serially using the standard JTAG channel. See Application Note AN1153. TERR indicates if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal goes Low (active) when an Error condition occurs, and stays Low until an “ISC_CLEAR” command is executed or a chip Reset (RESET) pulse is received after an “ISC_DISABLE” command. TSTAT behaves the same as Ready/Busy described in Section 22.2.1: Ready/Busy (PC3). TSTAT is High when the PSD module device is in READ mode (primary and secondary Flash memory contents can be read). TSTAT is Low when Flash memory Program or Erase cycles are in progress, and also when data is being written to the secondary Flash memory. TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE” command. 27.3 Security and Flash memory protection When the Security Bit is set, the device cannot be read on a Device Programmer or through the JTAG Port. When using the JTAG Port, only a Full Chip Erase command is allowed. All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the part to a non-secured blank state. The Security Bit can be set in PSDsoft Express Configuration. All primary and secondary Flash memory sectors can individually be sector protected against erasures. The sector protect bits can be set in PSDsoft Express Configuration. 153/189 Initial delivery state 28 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Initial delivery state When delivered from ST, the UPSD323xx devices have all bits in the memory and PLDs set to '1.' The code, configuration, and PLD logic are loaded using the programming procedure. Information for programming the device is available directly from ST. Please contact your local sales representative. 154/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV AC/DC parameters These tables describe the AD and DC parameters of the UPSD323xx devices: ● DC Electrical Specification ● AC Timing Specification ● PLD Timing ● – Combinatorial Timing – Synchronous Clock mode – Asynchronous Clock mode – Input Macrocell Timing MCU module Timing – READ Timing – WRITE Timing – Power-down and RESET Timing The following are issues concerning the parameters presented: ● In the DC specification the supply current is given for different modes of operation. ● The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 70 and Figure 71 show the PLD mA/MHz as a function of the number of Product Terms (PT) used. ● In the PLD timing parameters, add the required delay when Turbo Bit is '0.' Figure 70. PLD ICC/frequency consumption (5 V range) 110 100 VCC = 5V %) 90 BO TUR 80 ON (100 70 FF ) BO TUR O O 60 RB 50 ON (25% TU ICC – (mA) 29 AC/DC parameters 40 30 F 20 BO OF PT 100% PT 25% R TU 10 0 0 5 10 15 20 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) 25 AI02894 155/189 AC/DC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 71. PLD ICC/frequency consumption (3 V range) 60 VCC = 3V TUR ON (1 40 O FF 30 5%) (2 O ON TU RB O ICC – (mA) ) 00% BO 50 20 TURB 10 PT 100% PT 25% F BO OF R TU 0 0 5 10 15 20 25 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) AI03100 Table 108. PSD module example, typ. power calculation at VCC = 5.0 V (Turbo mode off) Conditions MCU clock frequency = 12 MHz Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) = 8 MHz = 2 MHz % Flash memory access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational modes % Normal = 40% % Power-down mode = 60% Number of product terms used 156/189 (from fitter report) = 45 PT % of total product terms = 45/182 = 24.7% Turbo mode = Off UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV AC/DC parameters Table 108. PSD module example, typ. power calculation at VCC = 5.0 V (Turbo mode off) (continued) Conditions Calculation (using typical values) = ICC(MCUactive) x %MCUactive + ICC(PSDactive) x %PSDactive + IPD(pwrdown) x %pwrdown ICC(MCUactive) = 20mA IPD(pwrdown) = 250µA ICC(PSDactive) = ICC(ac) + ICC(dc) = %flash x 2.5mA/MHz x Freq ALE + %SRAM x 1.5mA/MHz x Freq ALE ICC total + % PLD x (from graph using Freq PLD) = 0.8 x 2.5mA/MHz x 2MHz + 0.15 x 1.5mA/MHz x 2MHz + 24mA = (4 + 0.45 + 24) mA = 28.45mA ICC total = 20mA x 40% + 28.45mA x 40% + 250µA x 60% = 8mA + 11.38mA + 150µA = 19.53mA This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation is based on all I/O pins being disconnected and IOUT = 0mA. 157/189 Maximum ratings 30 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Maximum ratings Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 109. Absolute maximum ratings Symbol Parameter TSTG Storage Temperature TLEAD Lead Temperature during Soldering (20 seconds max.)(1) Max. Unit –65 125 °C 235 °C VIO Input and Output Voltage (Q = VOH or Hi-Z) –0.5 6.5 V VCC Supply Voltage –0.5 6.5 V VPP Device Programmer Supply Voltage –0.5 14.0 V VESD Electrostatic Discharge Voltage (Human Body Model) 2 –2000 2000 V 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω) 158/189 Min. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 31 EMC characteristics EMC characteristics Susceptibility test are performed on a sample basis during product characterization. 31.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). 31.1.1 ESD Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 Standard. 31.1.2 FTB A burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 Standard. A device reset allows normal operations to be resumed. The test results are given in Table 110, based on the EMS levels and classes defined in Application Note AN1709. 31.2 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore, it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for the user’s application. 31.2.1 Software recommendations The software flowchart must include the management of ‘runaway’ conditions, such as: 31.2.2 ● Corrupted program counter ● Unexpected reset ● Critical data corruption (e.g., control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see Application Note AN1015). 159/189 EMC characteristics 31.3 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU, and DLU) and using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the Application Note AN1181. 31.3.1 Electro-static discharge (ESD) Electro-Static discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). The Human Body Model is simulated (Table 111). This test complies with the JESD22-A114A Standard. Table 110. EMS test results Symbol Parameter Level/Class (1) Conditions Voltage limits to be applied on any VDD = 4V; TA = 25°C; fOSC = I/O pin to induce a functional 40MHz; WDT off complies with disturbance IEC 1000-4-2 VFESD 3C 1. Data based on characterization results, not tested in production. Table 111. ESD absolute maximum ratings Symbol Parameter Conditions Max. Value(1) Unit VESD(HBM) Electro-static discharge voltage (Human Body Model) TA = 25°C 2000 V 1. Data based on characterization results, not tested in production 31.3.2 Latch-up 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output, and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC Latch-up Standard (see Table 112). For more details, refer to the Application Note, AN1181. 31.3.3 Dynamic latch-up Electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro, and the component is put in reset mode. This test conforms to the IEC 1000-4-2 and SAEJ1752/3 Standards (see Table 112). For more details, refer to the Application Note, AN1181. Table 112. Latch-up and dynamic latch-up electrical sensitivities Symbol LU DLU Parameter Conditions Level/class (1) Static latch-up class TA = 25°C A Dynamic latch-up class VDD = 5 V; TA = 25°C; fOSC = 40 MHz A 1. Class description: A Class is an STMicroelectronics internal specification. All of its limits are higher than the JEDEC specifications. This means when a device belongs to “Class A,” it exceeds the JEDEC standard. “Class B” strictly covers all of the JEDEC criteria (International standards). 160/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 32 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 113. Operating conditions (5 V devices) Symbol Parameter VCC TA Min. Max. Unit Supply voltage 4.5 5.5 V Ambient operating temperature (industrial) –40 85 °C 0 70 °C Min. Max. Unit Supply voltage 3.0 3.6 V Ambient operating temperature (industrial) –40 85 °C 0 70 °C Ambient operating temperature (commercial) Table 114. Operating conditions (3 V devices) Symbol Parameter VCC TA Ambient operating temperature (commercial) Table 115. AC signal letters for timing A Address C Clock D Input Data I Instruction L ALE N RESET Input or Output P PSEN signal Q Output Data R RD signal W WR signal M Output Macrocell 1. Example: tAVLX = Time from Address Valid to ALE Invalid. 161/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 116. AC signal behavior symbols for timing t Time L Logic Level Low or ALE H Logic Level High V Valid X No Longer a Valid Logic Level Z Float PW Pulse Width 1. Example: tAVLX = Time from Address Valid to ALE Invalid. Figure 72. Switching waveforms – key WAVEFORMS INPUTS OUTPUTS STEADY INPUT STEADY OUTPUT MAY CHANGE FROM HI TO LO WILL BE CHANGING FROM HI TO LO MAY CHANGE FROM LO TO HI WILL BE CHANGING LO TO HI DON'T CARE CHANGING, STATE UNKNOWN OUTPUTS ONLY CENTER LINE IS TRI-STATE AI03102 Table 117. Major parameters Parameters/conditions/ comments 5 V test conditions 5.0 V value 3.3 V test conditions 3.3 V value Unit Operating voltage – 4.5 to 5.5 – 3.0 to 3.6 V Operating temperature – –40 to 85 – –40 to 85 °C MCU frequency 12 MHz (min) for USB; 8 MHz (min) for I2C – 1 Min, 40 Max – 1 Min, 24 Max MHz 72 12 MHz MCU clock, 6 MHz PLD input frequency, 2 MHz ALE 21 mA 25 12 MHz MCU clock, 1 MHz PLD input frequency 7 mA Active current, typical (25°C operation; 80% Flash and 15% SRAM accesses, 45 PLD product terms used; PLD Turbo mode Off) Idle current, typical (CPU halted but some peripherals active; 25°C operation; 45 PLD product terms used; PLD Turbo mode Off) 162/189 24 MHz MCU clock, 12 MHz PLD input frequency, 4 MHz ALE 24 MHz MCU clock, 12 MHz PLD input frequency UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Table 117. Major parameters (continued) Parameters/conditions/ comments 5 V test conditions 5.0 V value 3.3 V test conditions 3.3 V value Unit Standby current, typical (Power-down mode, requires reset to exit mode; without Low-Voltage Detect (LVD) Supervisor) 180 µA with LVD 110 100 µA with LVD 60 µA I/O sink/source current Ports A, B, C, and D VOL = 0.25 V (max); VOH = 3.9 V (min) IOL = 8 (max); IOH = –2 (min) VOL = 0.15 V (max); VOH = 2.6 V (min) IOL = 4 (max); IOH = –1 (min) mA PLD macrocells (For registered or combinatorial logic) – 16 – 16 – PLD inputs (Inputs from pins, macrocell feedback, or MCU addresses) – 69 – 69 – PLD outputs (Output to pins or internal feedback) – 16 – 16 – PLD propagation delay, typical (PLD input to output, Turbo mode) – 15 – 22 ns 163/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 118. DC characteristics (5 V devices) Symbol Parameter Test conditions (in addition to those in Table 113) Min. VIH Input high voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], XTAL1, RESET) 4.5 V < VCC < 5.5 V VIH1 Input high voltage (Ports A, B, C, D, 4[Bit 2], USB+, USB–) VIL VIL1 VOL Unit 0.7 VCC VCC + 0.5 V 4.5 V < VCC < 5.5 V 2.0 VCC + 0.5 V Input low voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], XTAL1, RESET) 4.5 V < VCC < 5.5 V VSS– 0.5 Input low voltage (Ports A, B, C, D, 4[Bit 2]) 4.5 V < VCC < 5.5 V –0.5 0.8 V Input low voltage (USB+, USB–) 4.5 V < VCC < 5.5 V VSS– 0.5 0.8 V 0.3 VC V C IOL = 20 µA VCC = 4.5 V 0.01 0.1 V IOL = 8 mA VCC = 4.5 V 0.25 0.45 V VOL1 Output low voltage (Ports 1,2,3,4, WR, RD) IOL = 1.6 mA 0.45 V VOL2 Output low voltage (Port 0, ALE, PSEN) IOL = 3.2 mA 0.45 V VOH Output high voltage (Ports A,B,C,D) VOH2 Output high voltage (Port 0 in ext. Bus mode, ALE, PSEN) VLVR Low Voltage RESET VOP XTAL open bias voltage (XTAL1, XTAL2) VLKO VCC(min) for Flash Erase and Program IOH = –20 µA VCC = 4.5 V 4.4 4.49 V IOH = –2 mA VCC = 4.5 V 2.4 3.9 V IOH = –800 µA 2.4 V IOH = –80 µA 4.05 V 0.1 V hysteresis 3.75 IOL = 3.2 mA 4.0 4.25 V 2.0 3.0 V 2.5 4.2 V IIL Logic '0' input current (Ports 1,2,3,4) VIN = 0.45 V (0 V for Port 4[pin 2]) –10 –50 µA ITL Logic 1-to-0 transition current (Ports 1,2,3,4) VIN = 3.5 V (2.5 V for Port 4[pin 2]) –65 –650 µA VIN = VSS –10 –55 µA IRST 164/189 Max. Output low voltage (Ports A,B,C,D) Typ. Reset pin pull-up current (RESET) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Table 118. DC characteristics (5 V devices) (continued) Symbol Parameter Test conditions (in addition to those in Table 113) Min. Typ. Max. Unit IFR XTAL feedback resistor current (XTAL1) XTAL1 = VCC XTAL2 = VSS –20 –50 µA ILI Input leakage current VSS < VIN < VCC –1 1 µA ILO Output leakage current 0.45 < VOUT < VCC –10 10 µA 250 µA Power-down mode VCC = 5.5 V LVD logic disabled LVD logic enabled 380 µA 20 30 mA 8 10 mA 30 38 mA 15 20 mA 40 62 mA 20 30 mA IPD(1) Active (12 MHz) VCC = 5 V Idle (12 MHz) ICC_CPU (2,3,6) Active (24 MHz) VCC = 5 V Idle (24 MHz) Active (40 MHz) VCC = 5 V Idle (40 MHz) PLD_TURBO = Off, f = 0 MHz(4) 0 PLD_TURBO = On, f = 0 MHz 400 700 µA/PT During Flash memory WRITE/Erase Only 15 30 mA Read-only, f = 0 MHz 0 0 mA f = 0 MHz 0 0 mA µA/PT(5) PLD Only ICC_PSD (DC)(6) Operating supply current Flash memory SRAM PLD AC Base ICC_PSD (AC)(6) Note 5 Flash memory AC adder 2.5 3.5 mA/MHz SRAM AC adder 1.5 3.0 mA/MHz 1. IPD (Power-down mode) is measured with: XTAL1=VSS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all other pins are disconnected. PLD not in Turbo mode. 2. ICC_CPU (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS+0.5 V, VIH = Vcc – 0.5 V, XTAL2 = not connected; RESET=VSS; Port 0=VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). 3. ICC_CPU (Idle mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS+0.5 V, VIH = VCC– 0.5 V, XTAL2 = not connected; Port 0 = VCC; 4. RESET=VCC; all other pins are disconnected. 5. PLD is in non-Turbo mode and none of the inputs are switching. 6. See Figure 70 for the PLD current calculation. 7. I/O current = 0 mA, all I/O pins are disconnected. 165/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 119. DC characteristics (3 V devices) Symbol Parameter Test conditions (in addition to those in Table 114) Min. VIH Input high voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], A, B, C, D, XTAL1, RESET) 3.0 V < VCC < 3.6 V VIH1 Input high voltage (Port 4[Bit 2]) VIL VIL1 VOL 166/189 Max. Unit 0.7VCC VCC + 0.5 V 3.0 V < VCC < 3.6 V 2.0 VCC + 0.5 V Input high voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], XTAL1, RESET) 3.0 V < VCC < 3.6 V VSS– 0.5 0.3 VCC V Input low voltage (Ports A, B, C, D) 3.0 V < VCC < 3.6 V –0.5 0.8 V Input low voltage (Port 4[Bit 2]) 3.0 V < VCC < 3.6 V VSS– 0.5 0.8 V Output low voltage (Ports A,B,C,D) VOL1 Output low voltage (Ports 1,2,3,4, WR, RD) VOL2 Output low voltage (Port 0, ALE, PSEN) VOH Output high voltage (Ports A,B,C,D) VOH2 Output high voltage (Port 0 in ext. Bus mode, ALE, PSEN) VLVR Low voltage reset VOP XTAL open bias voltage (XTAL1, XTAL2) VLKO VCC(min) for Flash Erase and Program Typ. IOL = 20 µA VCC = 3.0 V 0.01 0.1 V IOL = 4 mA VCC = 3.0 V 0.15 0.45 V IOL = 1.6 mA 0.45 V IOL = 100 µA 0.3 V IOL = 3.2 mA 0.45 V IOL = 200 µA 0.3 V IOH = –20 µA VCC = 3.0 V 2.9 2.99 V IOH = –1 mA VCC = 3.0 V 2.4 2.6 V IOH = –800 µA 2.0 V IOH = –80 µA 2.7 V 0.1 V hysteresis 2.3 IOL = 3.2 mA 2.5 2.7 V 1.0 2.0 V 1.5 2.2 V IIL Logic '0' input current (Ports 1,2,3,4) VIN = 0.45 V (0 V for Port 4[pin 2]) –1 –50 µA ITL Logic 1-to-0 transition current (Ports 1,2,3,4) VIN = 3.5 V (2.5 V for Port 4[pin 2]) –25 –250 µA VIN = VSS –10 –55 µA XTAL1 = VCC XTAL2 = VSS –20 –50 µA IRST Reset pin pull-up current (RESET) IFR XTAL feedback resistor current (XTAL1) ILI Input leakage current ILO Output leakage current VSS < VIN < VCC –1 1 µA 0.45 < VOUT < VCC –10 10 µA UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Table 119. DC characteristics (3 V devices) (continued) Symbol IPD(1) Parameter Test conditions (in addition to those in Table 114) Min. Typ. VCC = 3.6 V LVD logic disabled Power-down mode LVD logic enabled Active (12 MHz) ICC_CPU (2,3,6) VCC = 3.6 V Idle (12 MHz) Active (24 MHz) VCC = 3.6 V Idle (24 MHz) PLD Only ICC_PSD (DC)(6) Operating supply current Flash memory Unit 110 µA 180 µA 8 10 mA 4 5 mA 15 20 mA 8 10 mA PLD_TURBO = Off, f = 0 MHz(4) 0 PLD_TURBO = On, f = 0 MHz 200 400 µA/PT During Flash memory WRITE/Erase Only 10 25 mA Read-only, f = 0 MHz 0 0 mA f = 0 MHz 0 0 mA SRAM PLD AC base ICC_PSD (AC)(6) Max. µA/PT (5) Note 5 Flash memory AC adder 1.5 2.0 mA/MHz SRAM AC adder 0.8 1.5 mA/MHz 1. IPD (Power-down mode) is measured with: XTAL1=VSS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all other pins are disconnected. PLD not in Turbo mode. 2. ICC_CPU (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS+0.5 V, VIH = Vcc – 0.5 V, XTAL2 = not connected; RESET=VSS; Port 0=VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1 mA). 3. ICC_CPU (Idle mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS+0.5 V, VIH = VCC– 0.5 V, XTAL2 = not connected; Port 0 = VCC; 4. RESET = VCC; all other pins are disconnected. 5. PLD is in non-Turbo mode and none of the inputs are switching. 6. See Figure 70 for the PLD current calculation. 7. I/O current = 0 mA, all I/O pins are disconnected. 167/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 73. External program memory Read cycle tLLPL tLHLL ALE tAVLL tPLPH tLLIV tPLIV PSEN tPXAV tLLAX tPXIZ tAZPL PORT 0 INSTR IN A0-A7 tAVIV A0-A7 tPXIX A8-A11 PORT 2 A8-A11 AI06848 Table 120. External program memory AC characteristics (with the 5 V MCU module) Symbol Parameter(1) 40 MHz oscillator Min. Max. Variable oscillator 1/tCLCL = 24 to 40 MHz Min. Unit Max. tLHLL ALE pulse width 35 2 tCLCL – 15 ns tAVLL Address set-up to ALE 10 tCLCL – 15 ns tLLAX Address hold after ALE 10 tCLCL – 15 ns tLLIV ALE Low to valid instruction in tLLPL ALE to PSEN 10 tCLCL – 15 ns tPLPH PSEN pulse width 60 3 tCLCL – 15 ns tPLIV PSEN to valid instruction in tPXIX Input instruction hold after PSEN tPXIZ(2) Input instruction float after PSEN tPXAV(2) Address valid after PSEN tAVIV Address to valid instruction in tAZPL Address float to PSEN 55 4 tCLCL – 45 30 0 3 tCLCL – 45 0 15 20 –5 ns ns tCLCL – 10 tCLCL – 5 70 ns ns ns 5 tCLCL – 55 –5 ns ns 1. Conditions (in addition to those in Table 113, VCC = 4.5 to 5.5 V): VSS = 0 V; CL for Port 0, ALE and PSEN output is 100 pF; CL for other outputs is 80 pF 2. Interfacing the UPSD323xx devices to devices with float times up to 20 ns is permissible. This limited bus contention does not cause any damage to Port 0 drivers. 168/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Table 121. External program memory AC characteristics (with the 3 V MCU module) Symbol Parameter (1) 24 MHz oscillator Min. Variable oscillator 1/tCLCL = 8 to 24 MHz Max. Min. Unit Max. tLHLL ALE pulse width 43 2 tCLCL – 40 ns tAVLL Address set-up to ALE 17 tCLCL – 25 ns tLLAX Address hold after ALE 17 tCLCL – 25 ns tLLIV ALE Low to valid instruction in tLLPL ALE to PSEN 22 tCLCL – 20 ns tPLPH PSEN pulse width 95 3 tCLCL – 30 ns tPLIV PSEN to valid instruction in tPXIX Input instruction hold after PSEN tPXIZ(2) Input instruction float after PSEN tPXAV(2) Address valid after PSEN tAVIV Address to valid instruction in tAZPL Address float to PSEN 80 4 tCLCL – 87 60 ns 3 tCLCL – 65 0 ns 0 ns 32 tCLCL – 10 37 ns tCLCL – 5 148 ns 5 tCLCL – 60 –10 ns –10 ns 1. Conditions (in addition to those in Table 114, VCC = 3.0 to 3.6 V): VSS = 0 V; CL for Port 0, ALE and PSEN output is 100 pF, for 5 V devices, and 50 pF for 3 V devices; CL for other outputs is 80 pF, for 5 V devices, and 50 pF for 3 V devices) 2. Interfacing the UPSD323xx devices to devices with float times up to 35 ns is permissible. This limited bus contention does not cause any damage to Port 0 drivers. Table 122. External clock drive (with the 5 V MCU module) Parameter(1) Symbol 40 MHz oscillator Min. Max. Variable oscillator 1/tCLCL = 24 to 40 MHz Min. Max. Unit tRLRH Oscillator period 25 41.7 ns tWLWH High time 10 tCLCL – tCLCX ns tLLAX2 Low time 10 tCLCL – tCLCX ns tRHDX Rise time 10 ns tRHDX Fall time 10 ns 1. Conditions (in addition to those in Table 113, VCC = 4.5 to 5.5 V): VSS = 0 V; CL for Port 0, ALE and PSEN output is 100 pF; CL for other outputs is 80 pF 169/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 123. External clock drive (with the 3 V MCU module) Symbol Parameter 24 MHz oscillator (1) Min. Max. Variable oscillator 1/tCLCL = 8 to 24 MHz Unit Min. Max. 41.7 125 ns tRLRH Oscillator period tWLWH High time 12 tCLCL – tCLCX ns tLLAX2 Low time 12 tCLCL – tCLCX ns tRHDX Rise time 12 ns tRHDX Fall time 12 ns 1. Conditions (in addition to those in Table 114, VCC = 3.0 to 3.6 V): VSS = 0 V; CL for Port 0, ALE and PSEN output is 100 pF, for 5 V devices, and 50 pF for 3 V devices; CL for other outputs is 80 pF, for 5 V devices, and 50 pF for 3 V devices) Figure 74. External data memory Read cycle ALE tLHLL tWHLH PSEN tLLDV tLLWL tRLRH RD tRLDV tAVLL tLLAX2 tRLAZ A0-A7 from RI or DPL PORT 0 tRHDZ tRHDX DATA IN A0-A7 from PCL INSTR IN tAVWL tAVDV PORT 2 P2.0 to P2.3 or A8-A11 from DPH A8-A11 from PCH AI07088 Figure 75. External data memory Write cycle ALE tLHLL tWHLH PSEN tLLWL tWLWH WR tQVWX tAVLL tLLAX PORT 0 A0-A7 from RI or DPL tWHQX tQVWH DATA OUT A0-A7 from PCL INSTR IN tAVWL PORT 2 P2.0 to P2.3 or A8-A11 from DPH A8-A11 from PCH AI07089 170/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Table 124. External data memory AC characteristics (with the 5 V MCU module) Symbol Parameter (1) 40 MHz oscillator Min. Max. Variable oscillator 1/tCLCL = 24 to 40 MHz Min. Unit Max. tRLRH RD pulse width 120 6 tCLCL – 30 ns tWLWH WR pulse width 120 6 tCLCL – 30 ns tLLAX2 Address hold after ALE 10 tCLCL – 15 ns tRHDX RD to valid data in tRHDX Data hold after RD tRHDZ Data float after RD 38 2 tCLCL – 12 ns tLLDV ALE to valid data in 150 8 tCLCL – 50 ns tAVDV Address to valid data in 150 9 tCLCL – 75 ns tLLWL ALE to WR or RD 60 tCLCL + 15 ns tAVWL Address valid to WR or RD 70 tWHLH WR or RD High to ALE High 10 tQVWX Data valid to WR transition 5 tCLCL – 20 ns tQVWH Data set-up before WR 125 7 tCLCL – 50 ns tWHQX Data hold after WR 5 tCLCL – 20 ns tRLAZ Address float after RD 75 0 5 tCLCL – 50 0 90 3 tCLCL – 15 ns 4 tCLCL – 30 40 0 tCLCL – 15 ns ns tCLCL + 15 0 ns ns 1. Conditions (in addition to those in Table 113, VCC = 4.5 to 5.5 V): VSS = 0 V; CL for Port 0, ALE and PSEN output is 100 pF; CL for other outputs is 80 pF 171/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 125. External data memory AC characteristics (with the 3 V MCU module) Symbol Parameter (1) Variable oscillator 1/tCLCL = 8 to 24 MHz 24 MHz oscillator Min. Max. Min. Unit Max. tRLRH RD pulse width 180 6 tCLCL – 70 ns tWLWH WR pulse width 180 6 tCLCL – 70 ns tLLAX2 Address hold after ALE 56 2 tCLCL – 27 ns tRHDX RD to valid data in tRHDX Data hold after RD tRHDZ Data float after RD 63 2 tCLCL – 20 ns tLLDV ALE to valid data in 200 8 tCLCL – 133 ns tAVDV Address to valid data in 220 9 tCLCL – 155 ns tLLWL ALE to WR or RD 75 tCLCL + 50 ns tAVWL Address valid to WR or RD 67 tWHLH WR or RD High to ALE High 17 tQVWX Data valid to WR transition 5 tCLCL – 37 ns tQVWH Data set-up before WR 170 7 tCLCL – 122 ns tWHQX Data hold after WR 15 tCLCL – 27 ns tRLAZ Address float after RD 118 5 tCLCL – 90 0 0 175 3 tCLCL – 50 ns 4 tCLCL – 97 67 tCLCL – 25 0 ns ns tCLCL + 25 0 ns ns 1. Conditions (in addition to those in Table 114, VCC = 3.0 to 3.6 V): VSS = 0 V; CL for Port 0, ALE and PSEN output is 100 pF, for 5 V devices, and 50 pF for 3 V devices; CL for other outputs is 80 pF, for 5 V devices, and 50 pF for 3 V devices) Table 126. A/D analog specification Symbol Test condition Min. Typ. Max. Unit AVREF Analog power supply input voltage range VSS VCC V VAN Analog input voltage range VSS – 0.3 AVREF + 0.3 V IAVDD Current following between VCC and VSS 200 µA CAIN Overall accuracy ±2 l.s.b. NNLE Non-linearity error ±2 l.s.b. NDNLE Differential non-linearity error ±2 l.s.b. NZOE Zero-offset error ±2 l.s.b. NFSE Full scale error ±2 l.s.b. NGE Gain error ±2 l.s.b. 20 µs tCONV 172/189 Parameter Conversion time at 8 MHz clock UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Figure 76. Input to output disable / enable INPUT tER tEA INPUT TO OUTPUT ENABLE/DISABLE AI02863 Table 127. CPLD combinatorial timing (5 V devices) Symbol Parameter Conditions Min. Max. tPD(2) CPLD input pin/feedback to CPLD combinatorial output 20 tEA CPLD input to CPLD output enable tER PT Turbo Slew Unit aloc off rate(1) + 10 –2 ns 21 + 10 –2 ns CPLD input to CPLD output disable 21 + 10 –2 ns tARP CPLD register clear or preset delay 21 + 10 –2 ns tARPW CPLD register clear or preset pulse width tARD CPLD array delay +2 10 Any macrocell + 10 11 ns +2 ns 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) Table 128. CPLD combinatorial timing (3 V devices) Symbol Parameter Conditions Min. Max. tPD(2) CPLD input pin/feedback to CPLD combinatorial output 40 tEA CPLD input to CPLD output enable tER PT Turbo Slew Unit aloc off rate(1) + 20 –6 ns 43 + 20 –6 ns CPLD input to CPLD output disable 43 + 20 –6 ns tARP CPLD register clear or preset delay 40 + 20 –6 ns tARPW CPLD register clear or preset pulse width tARD CPLD array delay +4 25 Any macrocell + 20 25 ns +4 ns 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) 173/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 77. Synchronous clock mode timing – PLD tCH tCL CLKIN tS tH INPUT tCO REGISTERED OUTPUT AI02860 Table 129. CPLD macrocell synchronous clock mode timing (5 V devices) Symbol Parameter Maximum frequency external feedback fMAX Max. PT Turbo Slew Unit Aloc Off rate(1) 1/(tS+tCO) 40.0 MHz 1/(tS+tCO–10) 66.6 MHz 1/(tCH+tCL) 83.3 MHz Conditions Maximum frequency internal feedback (fCNT) Maximum frequency pipelined data Min. tS Input setup time 12 tH Input hold time 0 ns tCH Clock high time Clock input 6 ns tCL Clock low time Clock input 6 ns tCO Clock to output delay Clock input 13 tARD CPLD array delay Any macrocell 11 tMIN Minimum clock period (2) tCH+tCL 12 +2 + 10 ns –2 +2 ns ns ns 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL. 174/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Table 130. CPLD macrocell synchronous clock mode timing (3 V devices) Symbol Parameter Maximum frequency external feedback fMAX Maximum frequency internal feedback (fCNT) Maximum frequency pipelined data Conditions Min. Max. PT aloc Turbo Slew Unit off rate (1) 1/(tS+tCO) 22.2 MHz 1/(tS+tCO–10) 28.5 MHz 1/(tCH+tCL) 40.0 MHz tS Input setup time 20 tH Input hold time 0 ns tCH Clock high time Clock input 15 ns tCL Clock low time Clock input 10 ns tCO Clock to output delay Clock input 25 tARD CPLD array delay Any macrocell 25 tMIN Minimum clock period (2) tCH+tCL +4 + 20 ns –6 +4 25 ns ns ns 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL. Figure 78. Asynchronous Reset / Preset tARPW RESET/PRESET INPUT tARP REGISTER OUTPUT AI02864 Figure 79. Asynchronous clock mode timing (product term clock) tCHA tCLA CLOCK tSA tHA INPUT tCOA REGISTERED OUTPUT AI02859 175/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 131. CPLD macrocell asynchronous clock mode timing (5 V devices) Symbol fMAXA Parameter Conditions Min Max PT Turbo Slew Unit aloc off rate Maximum frequency external feedback 1/(tSA+tCOA) 38.4 MHz Maximum frequency internal feedback (fCNTA) 1/(tSA+tCOA– 10) 62.5 MHz Maximum frequency pipelined data 1/(tCHA+tCLA) 71.4 MHz tSA Input setup time 7 +2 tHA Input hold time 8 tCHA Clock input high time 9 + 10 ns tCLA Clock input low time 9 + 10 ns tCOA Clock to output delay ns tARDA CPLD array delay tMINA Minimum clock period ns 21 Any macrocell 1/fCNTA + 10 11 + 10 –2 +2 ns ns 16 ns Table 132. CPLD macrocell asynchronous clock mode timing (3 V devices) Symbol fMAXA 176/189 Parameter Conditions Min. Max. PT aloc Turbo off Slew rate Unit Maximum frequency external feedback 1/(tSA+tCOA) 21.7 MHz Maximum frequency internal feedback (fCNTA) 1/(tSA+tCOA– 10) 27.8 MHz Maximum frequency pipelined data 1/(tCHA+tCLA) 33.3 MHz tSA Input setup time 10 +4 tHA Input hold time 12 tCHA Clock input high time 17 + 20 ns tCLA Clock input low time 13 + 20 ns tCOA Clock to output delay tARD CPLD array delay tMINA Minimum clock period 1/fCNTA 25 36 ns ns 36 Any macrocell + 20 + 20 +4 –6 ns ns ns UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Figure 80. Input macrocell timing (product term clock) t INH t INL PT CLOCK t IS t IH INPUT OUTPUT t INO AI03101 Table 133. Input macrocell timing (5 V devices) Symbol Parameter Conditions Min. Max. PT aloc Turbo Unit Off tIS Input setup time (Note 1) 0 ns tIH Input hold time (Note 1) 15 tINH NIB input high time (Note 1) 9 ns tINL NIB input low time (Note 1) 9 ns tINO NIB input to combinatorial delay (Note 1) + 10 34 +2 ns + 10 ns 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX. Table 134. Input macrocell timing (3 V devices) Symbol Parameter Conditions Min. Max. PT aloc Turbo Off Unit tIS Input setup time (Note 1) 0 ns tIH Input hold time (Note 1) 25 tINH NIB input high time (Note 1) 12 ns tINL NIB input low time (Note 1) 12 ns tINO NIB input to combinatorial delay (Note 1) + 20 46 +4 ns + 20 ns 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. 177/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 135. Program, Write and Erase times (5 V devices) Symbol Parameter Min. Flash Program Typ. Max. Unit 8.5 (1) Flash Bulk Erase (pre-programmed) 3 Flash Bulk Erase (not pre-programmed) 5 tWHQV3 Sector Erase (pre-programmed) 1 tWHQV2 Sector Erase (not pre-programmed) 2.2 tWHQV1 Byte Program 14 Program / Erase Cycles (per Sector) tWHWLO Sector Erase Time-Out tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)(2) s 30 s s 30 s s 150 100,000 µs cycles 100 µs 30 ns 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Table 136. Program, Write and Erase times (3 V devices) Symbol Parameter Min. Flash Program Flash Bulk Erase(1) Typ. Max. Unit 8.5 (pre-programmed) 3 Flash Bulk Erase (not pre-programmed) 5 tWHQV3 Sector Erase (pre-programmed) 1 tWHQV2 Sector Erase (not pre-programmed) 2.2 tWHQV1 Byte Program 14 Program / Erase Cycles (per Sector) tWHWLO Sector Erase Time-Out tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)(2) s 30 s s 30 s s 150 100,000 µs cycles 100 µs 30 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. 178/189 ns UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Figure 81. Peripheral I/O Read timing ALE ADDRESS A/D BUS DATA VALID tAVQV (PA) tSLQV (PA) CSI tRLQV (PA) tRHQZ (PA) RD tDVQV (PA) DATA ON PORT A AI06610 Table 137. Port A peripheral data mode Read timing (5 V devices) Symbol Parameter tAVQV–PA Address valid to data valid tSLQV–PA CSI valid to data valid tRLQV–PA RD to data valid tDVQV–PA tRHQZ–PA Condition s Min. (Note 1) (Note 2) Max. Turbo off Unit 37 + 10 ns 27 + 10 ns 32 ns Data in to data out valid 22 ns RD to data high-Z 23 ns 1. Any input used to select Port A Data Peripheral mode. 2. Data is already stable on Port A. Table 138. Port A peripheral data mode Read timing (3 V devices) Symbol Parameter tAVQV–PA Address valid to data valid tSLQV–PA CSI valid to data valid tRLQV–PA RD to data valid tDVQV–PA tRHQZ–PA Conditions (Note 1) (Note 2) Min. Max. Turbo off Unit 50 + 20 ns 37 + 20 ns 45 ns Data in to data out valid 38 ns RD to data high-Z 36 ns 1. Any input used to select Port A Data Peripheral mode. 2. Data is already stable on Port A. 179/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 82. Peripheral I/O Write timing ALE ADDRESS A / D BUS DATA OUT tWLQV tWHQZ (PA) (PA) WR tDVQV (PA) PORT A DATA OUT AI06611 Table 139. Port A peripheral data mode Write timing (5 V devices) Symbol Parameter Conditions tWLQV–PA WR to Data Propagation Delay tDVQV–PA Data to Port A Data Propagation Delay tWHQZ–PA WR Invalid to Port A Tri-state Min. Max. Unit 25 ns 22 ns 20 ns Max. Unit 42 ns 38 ns 33 ns (Note 1) 1. Data stable on Port 0 pins to data on Port A. Table 140. Port A peripheral data mode Write timing (3 V devices) Symbol Parameter Conditions tWLQV–PA WR to data propagation delay tDVQV–PA Data to Port A data propagation delay tWHQZ–PA WR invalid to Port A tri-state Min. (Note 1) 1. Data stable on Port 0 pins to data on Port A. Figure 83. Reset (RESET) timing VCC VCC(min) tNLNH-PO Power-On Reset tOPR tNLNH tNLNH-A tOPR Warm Reset RESET AI02866b 180/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Table 141. Reset (RESET) timing (5 V devices) Symbol tNLNH tNLNH–PO tNLNH–A tOPR Parameter Conditions Min. RESET active low time(1) Power-on reset active low time Warm RESET (2) Max. Unit 150 ns 1 ms 25 μs RESET high to operational device 120 ns 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ mode. Table 142. Reset (RESET) timing (3 V devices) Symbol tNLNH tNLNH–PO tNLNH–A tOPR Parameter Conditions Min. RESET active low time(1) Max. Unit 300 ns Power-on reset active low time 1 ms Warm RESET (2) 25 μs RESET high to operational device 300 ns 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ mode. Figure 84. ISC timing t ISCCH TCK t ISCCL t ISCPSU t ISCPH TDI/TMS t ISCPZV t ISCPCO ISC OUTPUTS/TDO t ISCPVZ ISC OUTPUTS/TDO AI02865 181/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 143. ISC timing (5 V devices) Symbol Parameter Conditions Min. Max. Unit tISCCF Clock (TCK, PC1) frequency (except for PLD) (Note 1) 20 MHz tISCCH Clock (TCK, PC1) high time (except for PLD) (Note 1) 23 ns tISCCL Clock (TCK, PC1) low time (except for PLD) (Note 1) 23 ns tISCCFP Clock (TCK, PC1) frequency (PLD only) (Note 2) tISCCHP Clock (TCK, PC1) high time (PLD only) (Note 2) 240 ns tISCCLP Clock (TCK, PC1) low time (PLD only) (Note 2) 240 ns 7 ns 5 ns tISCPSU ISC port set-up time tISCPH ISC port hold-up time 2 MHz tISCPCO ISC port clock to output 21 ns tISCPZV ISC port high-impedance to valid output 21 ns tISCPVZ ISC port valid output to high-impedance 21 ns Max. Unit 12 MHz 1. For non-PLD Programming, Erase or in ISC By-pass mode. 2. For Program or Erase PLD only. Table 144. ISC timing (3 V devices) Symbol Parameter Conditions tISCCF Clock (TCK, PC1) frequency (except for PLD) (Note 1) tISCCH Clock (TCK, PC1) high time (except for PLD) (Note 1) 40 ns tISCCL Clock (TCK, PC1) low time (except for PLD) (Note 1) 40 ns tISCCFP Clock (TCK, PC1) frequency (PLD only) (Note 2) tISCCHP Clock (TCK, PC1) high time (PLD only) Min. 2 (Note 2) 240 ns (Note 2) 240 ns tISCPSU ISC port set-up time 12 ns tISCPH 5 ns tISCCLP Clock (TCK, PC1) low time (PLD only) ISC port hold-up time tISCPCO ISC port clock to output 30 ns tISCPZV ISC port high-impedance to valid output 30 ns tISCPVZ ISC port valid output to high-impedance 30 ns 1. For non-PLD Programming, Erase or in ISC By-pass mode. 2. For Program or Erase PLD only. Figure 85. MCU module AC measurement I/O waveform VCC – 0.5V 0.2 VCC + 0.9V Test Points 0.2 VCC – 0.1V 0.45V AI06650 1. AC inputs during testing are driven at VCC–0.5 V for a logic '1,' and 0.45 V for a logic '0.' 2. Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0'. 182/189 MHz UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DC and AC parameters Figure 86. PSD module AC float I/O waveform VOH – 0.1V VLOAD + 0.1V Test Reference Points VLOAD – 0.1V 0.2 VCC – 0.1V VOL + 0.1V AI06651 1. For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH or VOL level occurs 2. IOL and IOH ≥ 20mA Figure 87. External clock cycle Figure 88. Recommended oscillator circuits 1. C1, C2 = 30 pF ± 10 pF for crystals 2. For ceramic resonators, contact resonator manufacturer 3. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator 4. have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Figure 89. PSD module AC measurement I/O waveform 3.0V Test Point 1.5V 0V AI03103b 183/189 DC and AC parameters UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 90. PSD module AC measurement load circuit 2.01 V 195 Ω Device Under Test CL = 30 pF (Including Scope and Jig Capacitance) AI03104b Table 145. Capacitance Symbol CIN COUT Parameter Input capacitance (for input pins) Output capacitance (for input/output pins) Test conditions (1) Typ.(2) Max. Unit VIN = 0 V 4 6 pF VOUT = 0 V 8 12 pF 1. Sampled only, not 100% tested. 2. Typical values are for TA = 25°C and nominal supply voltages. 184/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 33 Package mechanical information Package mechanical information Figure 91. LQFP52 – 52-lead plastic thin, quad, flat package outline Seating plane A2 A c A1 ddd C D 0.25 mm .010 inch Gage plane D1 D2 27 39 L k L1 40 26 b E2 E1 E 14 52 Pin 1 identification 13 1 e DC_ME 1. Drawing is not to scale. Table 146. LQFP52 – 52-lead plastic thin, quad, flat package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ Min 1.60 Max 0.063 A1 0.05 0.15 0.002 0.0059 A2 1.35 1.45 0.0531 0.0571 b 0.22 0.38 0.0087 0.015 C 0.09 0.2 0.0035 0.0079 0.0177 0.0295 0° 7° D 12 0.4724 D1 10 0.3937 D2 7.8 0.3071 E 12 0.4724 E1 10 0.3937 E2 7.8 0.3071 e 0.65 0.0256 L L1 0.45 0.75 1 0.0394 k 0° ddd 0.100 7° 0.0039 1. Values in inches are converted from mm and rounded to 4 decimal digits. 185/189 Package mechanical information UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 92. LQFP80 – 80-lead plastic thin, quad, flat package outline D D1 D3 A2 41 60 61 40 e E3 E1 E b 21 80 Pin 1 identification 1 20 A ccc L1 c A1 k L 9X_ME 1. Drawing is not to scale. Table 147. LQFP80 – 80-lead plastic thin, quad, flat package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ 1.600 A1 0.050 0.150 Max 0.0630 0.0020 0.0059 A2 1.400 1.350 1.450 0.0551 0.0531 0.0571 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 0.090 0.200 0.0035 0.0079 0.0177 0.0295 0° 7° C D 14.000 0.5512 D1 12.000 0.4724 D3 9.500 0.3740 E 14.000 0.5512 E1 12.000 0.4724 E3 9.500 0.3740 e 0.500 0.0197 L 0.600 L1 1.000 k ccc 0.450 0.750 0.0236 0.0394 0° 7° 0.080 1. Values in inches are converted from mm and rounded to 4 decimal digits. 186/189 Min 0.0031 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 34 Part numbering Part numbering Table 148. Ordering information scheme Example: Device type UPSD = Microcontroller PSD UPSD 3 2 3 4 B V – 24 U 6 T Family 3 = 8032 core PLD size 2 = 16 Macrocells SRAM Size 3 = 8 Kbytes Main Flash memory size 2 = 64 Kbytes 3 = 128 Kbytes 4 = 256 Kbytes IP mix A = USB, I2C, PWM, DDC, ADC, (2) UARTs, Supervisor (Reset Out, Reset In, LVD, WD) B = I2C, PWM, DDC, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) Operating voltage blank = VCC = 4.5 to 5.5 V V = VCC = 3.0 to 3.6 V Speed –24 = 24 MHz –40 = 40 MHz Package T = 52-pin LQFP U = 80-pin LQFP Temperature range 1 = 0 to 70°C 6 = –40 to 85°C Shipping options F = ECOPACK® Package, Tape & Reel Packing For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. 187/189 Revision history 35 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Revision history Table 149. Document revision history 188/189 Date Revision Changes November 2002 1.0 First Issue 27-Feb-03 1.1 Updates: product information (Figure 3, 4, Table 1, 2); port information (Figure 17, 18, Table 30); interface information (Figure 30, Table 44); remove programming guide; PSD module information (Figure 50, 51, Table 85); PLD information (Figure 58, 59, Table 91, 92, 93); electrical characteristics (Table 118, 119, 135, 136) 03-Sep-03 1.2 Update references for Product Catalog, disclaimer 04-Feb-04 2.0 Reformatted; corrected mechanical dimensions (Table 148) 05-Jul-04 3.0 Reformatted; added EMC characteristics (Table Table 109, 110, 111) 04-Nov-04 4.0 Updates according to data brief change requests (Figure 3, 4; Table 1, 2, 116) 21-Jan-2009 5 Removed battery backup feature and related SRAM Standby mode information. Added ECOPACK® information and updated Section 33: Package mechanical information on page 185. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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