UPSD3354D-40U6T

uPSD33xx Turbo Series Fast 8032 MCU with Programmable Logic PRELIMINARY DATA FEATURES SUMMARY ■ ■ ■ ■ ■ FAST 8-BIT TURBO 8032 MCU, 40MHz – Advanced core, 4-clocks per instruction – 10 MIPs peak performance at 40MHz (5V) – JTAG Debug and In-System Programming – Branch Cache & 6 instruction Prefetch Queue – Dual XDATA pointers with auto incr & decr – Compatible with 3rd party 8051 tools DUAL FLASH MEMORIES WITH MEMORY MANAGEMENT – Place either memory into 8032 program address space or data address space – READ-while-WRITE operation for InApplication Programming and EEPROM emulation – Single voltage program and erase – 100K guaranteed erase cycles, 15-year retention CLOCK, RESET, AND SUPPLY MANAGEMENT – SRAM is Battery Backup capable – Flexible 8-level CPU clock divider register – Normal, Idle, and Power Down Modes – Power-on and Low Voltage reset supervisor – Programmable Watchdog Timer PROGRAMMABLE LOGIC, GENERAL PURPOSE – 16 macrocells – Create shifters, state machines, chipselects, glue-logic to keypads, panels, LCDs, others COMMUNICATION INTERFACES – I2C Master/Slave controller, 833KHz – SPI Master controller, 10MHz – Two UARTs with independent baud rate – IrDA protocol support up to 115K baud – Up to 46 I/O, 5V tolerant on 3.3V uPSD33xxV Figure 1. Packages TQFP52 (T) 52-lead, Thin, Quad, Flat TQFP80 (U) 80-lead, Thin, Quad, Flat ■ ■ ■ A/D CONVERTER – Eight Channels, 10-bit resolution, 6µs TIMERS AND INTERRUPTS – Three 8032 standard 16-bit timers – Programmable Counter Array (PCA), six 16-bit modules for PWM, CAPCOM, and timers – 8/10/16-bit PWM operation – 11 Interrupt sources with two external interrupt pins OPERATING VOLTAGE SOURCE (±10%) – 5V devices use both 5.0V and 3.3V sources – 3.3V devices use only 3.3V source January 2005 1/231 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. uPSD33xx Table 1. Device Summary Part Number uPSD3312D-40T6 uPSD3312DV-40T6 uPSD3333D-40T6 uPSD3333DV-40T6 uPSD3333D-40U6 uPSD3333DV-40U6 uPSD3334D-40U6 uPSD3334DV-40U6 uPSD3354D-40T6 uPSD3354DV-40T6 uPSD3354D-40U6 uPSD3354DV-40U6 1st Flash (bytes) 64K 64K 128K 128K 128K 128K 256K 256K 256K 256K 256K 256K 2nd Flash (bytes) 16K 16K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K SRAM (bytes) 2K 2K 8K 8K 8K 8K 8K 8K 32K 32K 32K 32K GPIO 37 37 37 37 46 46 46 46 37 37 46 46 8032 Bus No No No No Yes Yes Yes Yes No No Yes Yes VCC 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V VDD 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V Pkg. Temp. TQFP52 –40°C to 85°C TQFP52 –40°C to 85°C TQFP52 –40°C to 85°C TQFP52 –40°C to 85°C TQFP80 –40°C to 85°C TQFP80 –40°C to 85°C TQFP80 –40°C to 85°C TQFP80 –40°C to 85°C TQFP52 –40°C to 85°C TQFP52 –40°C to 85°C TQFP80 –40°C to 85°C TQFP80 –40°C to 85°C 2/231 uPSD33xx TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 uPSD33xx HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Internal Memory (MCU Module, Standard 8032 Memory: DATA, IDATA, SFR) . . . . . . . . . . . . 16 External Memory (PSD Module: Program memory, Data memory). . . . . . . . . . . . . . . . . . . . . . 16 8032 MCU CORE PERFORMANCE ENHANCEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pre-Fetch Queue (PFQ) and Branch Cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PFQ Example, Multi-cycle Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Aggregate Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8032 MCU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program Counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 B Register (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General Purpose Registers (R0 - R7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPECIAL FUNCTION REGISTERS (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8032 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 External Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 External Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Absolute Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Long Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 uPSD33xx INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3/231 uPSD33xx DUAL DATA POINTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Data Pointer Control Register, DPTC (85h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Data Pointer Mode Register, DPTM (86h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DEBUG UNIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Individual Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 MCU CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 MCU_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PERIPH_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Reduced Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 OSCILLATOR AND EXTERNAL COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I/O PORTS of MCU MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MCU Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Bus Read Cycles (PSEN or RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Bus Write Cycles (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Controlling the PFQ and BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SUPERVISORY FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 External Reset Input Pin, RESET_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Low VCC Voltage Detect, LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power-up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 JTAG Debug Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Watchdog Timer, WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STANDARD 8032 TIMER/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Standard Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFR, TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFR, TMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0 and Timer 1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 . . . . 69 . . . . 71 . . . . 71 . . . . 71 . . . . 74 SERIAL UART INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 UART Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4/231 uPSD33xx Serial Port Control Registers . . . . . . . . . . . . . . . . UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . More About UART Mode 0 . . . . . . . . . . . . . . . . . . More About UART Mode 1 . . . . . . . . . . . . . . . . . . More About UART Modes 2 and 3 . . . . . . . . . . . . ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 82 . . . . 84 . . . . 85 . . . . 87 . . . . 89 IrDA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Pulse Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I2C Interface Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Communication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Serial I/O Engine (SIOE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 I2C Interface Control Register (S1CON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 I2C Interface Status Register (S1STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 I2C Data Shift Register (S1DAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I2C Address Register (S1ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I2C START Sample Setting (S1SETUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 I2C Operating Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SPI (SYNCHRONOUS PERIPHERAL INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SPI Bus Features and Communication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Bus-Level Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SPI SFR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Dynamic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Port 1 ADC Channel Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PROGRAMMABLE COUNTER ARRAY (PCA) WITH PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PCA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PCA Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Operation of TCM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Toggle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 PWM Mode - (X8), Fixed Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 PWM Mode - (X8), Programmable Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 PWM Mode - Fixed Frequency, 16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5/231 uPSD33xx PWM Mode - Fixed Frequency, 10-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writing to Capture/Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... ...... ...... . . . 129 . . . 129 . . . 129 . . . 132 PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 PSD Module Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Runtime Control Register Definitions (csiop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 PSD Module Detailed Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 PSD Module Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 6/231 uPSD33xx SUMMARY DESCRIPTION The Turbo uPSD33xx Series combines a powerful 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix to form an ideal embedded controller. At its core is a fast 4-cycle 8032 MCU with a 6-byte instruction prefetch queue (PFQ) and a 4-entry fully associative branching cache (BC) to maximize MCU performance, enabling loops of code in smaller localities to execute extremely fast. Code development is easily managed without a hardware In-Circuit Emulator by using the serial JTAG debug interface. JTAG is also used for InSystem Programming (ISP) in as little as 10 seconds, perfect for manufacturing and lab development. The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize the 8032 memory structure, offering two independent Figure 2. Block Diagram uPSD33xx (3) 16-bit Timer/ Counters (2) External Interrupts Turbo 8032 Core PFQ & BC 1st Flash Memory: 64K, 128K, or 256K Bytes banks of Flash memory that can be placed at virtually any address within 8032 program or data address space, and easily paged beyond 64K bytes using on-chip programmable decode logic. Dual Flash memory banks provide a robust solution for remote product updates in the field through In-Application Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating the need for external EEPROM chips. General purpose programmable logic (PLD) is included to build an endless variety of glue-logic, saving external logic devices. The PLD is configured using the software development tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge. The uPSD33xx also includes supervisor functions such as a programmable watchdog timer and low-voltage reset. Programmable Decode and Page Logic P3.0:7 I2C 2nd Flash Memory: 16K or 32K Bytes SRAM: 2K, 8K, or 32K Bytes UART0 (8) GPIO, Port A (80-pin only) (8) GPIO, Port 3 General Purpose Programmable Logic, 16 Macrocells (8) GPIO, Port B (2) GPIO, Port D (4) GPIO, Port C PA0:7 PB0:7 PD1:2 (8) 10-bit ADC Optional IrDA Encoder/Decoder SYSTEM BUS P1.0:7 (8) GPIO, Port 1 PC0:7 JTAG ICE and ISP 8032 Address/Data/Control Bus (80-pin device only) Supervisor: Watchdog and Low-Voltage Reset VCC, VDD, GND, Reset, Crystal In UART1 SPI 16-bit PCA (6) PWM, CAPCOM, TIMER MCU Bus P4.0:7 (8) GPIO, Port 4 Dedicated Pins AI08875 7/231 uPSD33xx PIN DESCRIPTIONS Figure 3. TQFP52 Connections 40 P1.6/SPITXD(2)/ADC6 41 P1.7/SPISEL(2)/ADC7 47 AVCC/VREF(3) 44 RESET_IN 45 GND 46 PB5 43 PB6 42 PB7 52 PB0 51 PB1 50 PB2 49 PB3 48 PB4 PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 DEBUG 5 3.3V VCC 6 PC4/TERR 7 VDD(1) 8 GND 9 PC3/TSTAT 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13 39 P1.5/SPIRXD(2)/ADC5 38 P1.4/SPICLK(2)/ADC4 37 P1.3/TXD1(IrDA)(2)/ADC3 36 P1.2/RXD1(IrDA)(2)/ADC2 35 P1.1/T2X(2)/ADC1 34 P1.0/T2(2)/ADC0 33 VDD(1) 32 XTAL2 31 XTAL1 30 P3.7/SCL 29 P3.6/SDA 28 P3.5/C1 27 P3.4/C0 SPISEL(2)/PCACLK1/P4.7 14 SPITXD(2)/TCM5/P4.6 15 SPIRXD(2)/TCM4/P4.5 16 SPICLK(2)/TCM3/P4.4 17 TXD1(IrDA)(2)/PCACLK0/P4.3 18 GND 19 20 T2X(2)/TCM1/P4.1 21 T2(2)/TCM0/P4.0 22 RXD0/P3.0 23 TXD0/P3.1 24 EXTINT0/TG0/P3.2 25 RXD1(IrDA)(2)/TCM2/P4.2 EXTINT1/TG1/P3.3 26 AI07822 Note: 1. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1. 3. VREF and 3.3V AV CC are shared in the 52-pin package only. ADC channels must use AVCC as VREF for the 52-pin package. 8/231 uPSD33xx Figure 4. TQFP80 Connections 61 P1.6/SPITXD(2)/ADC6 64 P1.7/SPISEL(2)/ADC7 79 P3.2/EXINT0/TG0 75 P3.0/RXD0 77 P3.1/TXD0 68 RESET_IN 63 PSEN 72 AVCC 70 VREF 69 GND 80 PB0 78 PB1 76 PB2 74 PB3 73 PB4 71 PB5 67 PB6 66 PB7 62 WR 65 RD PD2/CSI 1 P3.3/TG1/EXINT1 2 PD1/CLKIN 3 ALE 4 PC7 5 JTAG TDO 6 JTAG TDI 7 DEBUG 8 PC4/TERR 9 3.3V VCC 10 NC 11 VDD(1) 12 GND 13 PC3/TSTAT 14 PC2/VSTBY 15 JTAG TCK 16 NC 17 SPISEL(2)/PCACLK1/P4.7 18 SPITXD(2)/TCM5/P4.6 19 JTAG TMS 20 60 P1.5/SPIRXD(2)/ADC5 59 P1.4/SPICLK(2)/ADC4 58 P1.3/TXD1(IrDA)(2)/ADC3 57 MCU A11 56 P1.2/RXD1(IrDA)(2)/ADC2 55 MCU A10 54 P1.1/T2X(2)/ADC1 53 MCU A9 52 P1.0/T2(2)/ADC0 51 MCU A8 50 VDD(1) 49 XTAL2 48 XTAL1 47 MCU AD7 46 P3.7/SCL 45 MCU AD6 44 P3.6/SDA 43 MCU AD5 42 P3.5/C1 41 MCU AD4 PA7 21 PA6 22 SPIRXD(2)/TCM4/P4.5 23 PA5 24 SPICLK(2)/TCM3/P4.4 25 PA4 26 TXD1(IrDA)(2)/PCACLK0/P4.3 27 PA3 28 GND 29 RXD1(IrDA)(2)/TCM2/P4.2 30 T2X(2)/TCM1/P4.1 31 PA2 32 T2(2)/TCM0/P4.0 33 PA1 34 PA0 35 MCU AD0 36 MCU AD1 37 MCU AD2 38 MCU AD3 39 P3.4/C0 40 AI07823 Note: NC = Not Connected Note: 1. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1. 9/231 uPSD33xx Table 2. Pin Definitions Port Pin MCUAD0 MCUAD1 MCUAD2 MCUAD3 MCUAD4 MCUAD5 MCUAD6 MCUAD7 MCUA8 MCUA9 MCUA10 MCUA11 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 Signal Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 T2 ADC0 T2X ADC1 RxD1 ADC2 TXD1 ADC3 SPICLK ADC4 SPIRxD ADC6 SPITXD ADC6 SPISEL ADC7 RxD0 TXD0 EXINT0 TGO INT1 C0 80-Pin 52-Pin In/Out No. No.(1) 36 37 38 39 41 43 45 47 51 53 55 57 52 54 56 58 59 60 61 64 75 77 79 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 34 35 36 37 38 39 40 41 23 24 25 I/O I/O I/O I/O I/O I/O I/O I/O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Basic External Bus Multiplexed Address/ Data bus A0/D0 Multiplexed Address/ Data bus A1/D1 Multiplexed Address/ Data bus A2/D2 Multiplexed Address/ Data bus A3/D3 Multiplexed Address/ Data bus A4/D4 Multiplexed Address/ Data bus A5/D5 Multiplexed Address/ Data bus A6/D6 Multiplexed Address/ Data bus A7/D7 External Bus, Addr A8 External Bus, Addr A9 External Bus, Addr A10 External Bus, Addr A11 General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin Timer 2 Count input (T2) Timer 2 Trigger input (T2X) UART1 or IrDA Receive (RxD1) UART or IrDA Transmit (TxD1) SPI Clock Out (SPICLK) SPI Receive (SPIRxD) SPI Transmit (SPITxD) SPI Slave Select (SPISEL) UART0 Receive (RxD0) UART0 Transmit (TxD0) Interrupt 0 input (EXTINT0)/Timer 0 gate control (TG0) Interrupt 1 input (EXTINT1)/Timer 1 gate control (TG1) Counter 0 input (C0) ADC Channel input (ADC0) ADC Channel input (ADC1) ADC Channel input (ADC2) ADC Channel input (ADC3) ADC Channel input (ADC4) ADC Channel input (ADC5) ADC Channel input (ADC6) ADC Channel input (ADC7) 0 1 2 3 4 5 6 7 Alternate 1 Alternate 2 P3.3 P3.4 2 40 26 27 I/O I/O General I/O port pin General I/O port pin 10/231 uPSD33xx Port Pin P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 VREF RD WR PSEN ALE RESET_IN XTAL1 XTAL2 DEBUG PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Signal Name C1 SDA SCL T2 TCM0 T2X TCM1 RXD1 TCM2 TXD1 PCACLK0 SPICLK TCM3 SPIRXD TCM4 SPITXD SPISEL PCACLK1 80-Pin 52-Pin In/Out No. No.(1) Basic 42 28 I/O General I/O port pin 44 46 33 31 30 27 25 23 19 18 70 65 62 63 4 68 48 49 8 35 34 32 28 26 24 22 21 29 30 22 21 20 18 17 16 15 14 N/A N/A N/A N/A N/A 44 31 32 5 N/A N/A N/A N/A N/A N/A N/A N/A I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O O O O I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin Reference Voltage input for ADC READ Signal, external bus WRITE Signal, external bus PSEN Signal, external bus Address Latch signal, external bus Active low reset input Oscillator input pin for system clock Oscillator output pin for system clock I/O to the MCU Debug Unit General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin Function Alternate 1 Counter 1 input (C1) I2C Bus serial data (I2CSDA) I2C Bus clock (I2CSCL) Program Counter Array0 PCA0-TCM0 PCA0-TCM1 PCA0-TCM2 PCACLK0 Program Counter Array1 PCA1-TCM3 PCA1-TCM4 PCA1-TCM5 PCACLK1 Alternate 2 Timer 2 Count input (T2) Timer 2 Trigger input (T2X) UART1 or IrDA Receive (RxD1) UART1 or IrDA Transmit (TxD1) SPI Clock Out (SPICLK) SPI Receive (SPIRxD) SPI Transmit (SPITxD) SPI Slave Select (SPISEL) All Port A pins support: 1. PLD Macro-cell outputs, or 2. PLD inputs, or 3. Latched Address Out (A0-A7), or 4. Peripheral I/O Mode 11/231 uPSD33xx Port Pin PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 JTAGTMS JTAGTCK PC2 PC3 PC4 JTAGTDI JTAGTDO PC7 PD1 CLKIN Signal Name 80-Pin 52-Pin In/Out No. No.(1) 80 78 76 74 73 71 67 66 20 16 15 14 9 7 6 5 3 52 51 50 49 48 46 43 42 13 12 11 10 7 4 3 2 1 I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I O I/O I/O Function Basic General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin JTAG pin (TMS) JTAG pin (TCK) General I/O port pin General I/O port pin General I/O port pin JTAG pin (TDI) JTAG pin (TDO) General I/O port pin General I/O port pin PLD, Macrocell output, or PLD input 1. PLD I/O 2. Clock input to PLD and APD 1. PLD I/O 2. Chip select ot PSD Module SRAM Standby voltage input (VSTBY) Optional JTAG Status (TSTAT) Optional JTAG Status (TERR) Alternate 1 Alternate 2 All Port B pins support: 1. PLD Macro-cell outputs, or 2. PLD inputs, or 3. Latched Address Out (A0-A7) TMS TCK VSTBY TSTAT TERR TDI TDO PLD Macrocell output, or PLD input PLD, Macrocell output, or PLD input PLD, Macrocell output, or PLD input PD2 3.3V-VCC AVCC VDD 3.3V or 5V VDD 3.3V or 5V GND GND GND NC NC CSI 1 10 72 12 N/A 6 47 8 I/O General I/O port pin VCC - MCU Module Analog VCC Input VDD - PSD Module VDD - 3.3V for 3V VDD - 5V for 5V VDD - PSD Module VDD - 3.3V for 3V VDD - 5V for 5V 50 13 29 69 11 17 33 9 19 45 N/A N/A Note: 1. N/A = Signal Not Available on 52-pin package. 12/231 uPSD33xx uPSD33xx HARDWARE DESCRIPTION The uPSD33xx has a modular architecture built from a stacked die process. There are two die, one is designated “MCU Module” in this document, and the other is designated “PSD Module” (see Figure 5., page 14). In all cases, the MCU Module die operates at 3.3V with 5V tolerant I/O. The PSD Module is either a 3.3V die or a 5V die, depending on the uPSD33xx device as described below. The MCU Module consists of a fast 8032 core, that operates with 4 clocks per instruction cycle, and has many peripheral and system supervisor functions. The PSD Module provides the 8032 with multiple memories (two Flash and one SRAM) for program and data, programmable logic for address decoding and for general-purpose logic, and additional I/O. The MCU Module communicates with the PSD Module through internal address and data busses (A8 – A15, AD0 – AD7) and control signals (RD, WR , PSEN, ALE, RESET). There are slightly different I/O characteristics for each module. I/Os for the MCU module are designated as Ports 1, 3, and 4. I/Os for the PSD Module are designated as Ports A, B, C, and D. For all 5V uPSD33xx devices, a 3.3V MCU Module is stacked with a 5V PSD Module. In this case, a 5V uPSD33xx device must be supplied with 3.3VCC for the MCU Module and 5.0VDD for the PSD Module. Ports 3 and 4 of the MCU Module are 3.3V ports with tolerance to 5V devices (they can be directly driven by external 5V devices and they can directly drive external 5V devices while producing a VOH of 2.4V min and VCC max). Ports A, B, C, and D of the PSD Module are true 5V ports. For all 3.3V uPSD33xxV devices, a 3.3V MCU Module is stacked with a 3.3V PSD Module. In this case, a 3.3V uPSD33xx device needs to be supplied with a single 3.3V voltage source at both VCC and VDD. I/O pins on Ports 3 and 4 are 5V tolerant and can be connected to external 5V peripherals devices if desired. Ports A, B, C, and D of the PSD Module are 3.3V ports, which are not tolerant to external 5V devices. Refer to Table 3 for port type and voltage source requirements. 80-pin uPSD33xx devices provide access to 8032 address, data, and control signals on external pins to connect external peripheral and memory devices. 52-pin uPSD33xx devices do not provide access to the 8032 system bus. All non-volatile memory and configuration portions of the uPSD33xx device are programmed through the JTAG interface and no special programming voltage is needed. This same JTAG port is also used for debugging of the 8032 core at runtime providing breakpoint, single-step, display, and trace features. A non-volatile security bit may be programmed to block all access via JTAG interface for security. The security bit is defeated only by erasing the entire device, leaving the device blank and ready to use again. Table 3. Port Type and Voltage Source Combinations Device Type 5V: uPSD33xx 3.3V: uPSD33xxV VCC for MCU Module 3.3V 3.3V VDD for PSD Module 5.0V 3.3V Ports 3 and 4 on MCU Module 3.3V but 5V tolerant 3.3V but 5V tolerant Ports A, B, C, and D on PSD Module 5V 3.3V. NOT 5V tolerant 13/231 uPSD33xx Figure 5. uPSD33xx Functional Modules Port 3 - UART0, Intr, Timers Port 1 - T imer, ADC, SPI Port 4 - PCA, PWM, UART1 Port 3 I2C MCU Module Port 3 Port 1 T urbo 8032 Core Dual UARTs Interrupt 3T imer / Counters 256 Byte SRAM XT AL Clock Unit 10-bit ADC SPI PCA PWM Counters IC Unit 2 VCC P ins 3.3V Dedicated Memory Interface Prefetch, Branch Cache 8-Bit Die-to-Die Bus Enhanced MCU Interface PSD Page Register 8032 Internal Bus Ext. Bus Reset Input LVD JT AG DEBUG Internal Reset Reset Logic WDT Reset Pin Main Flash Decode PLD Secondary Flash PSD Reset SRAM PSD Module PSD Internal Bus JT ISP AG CPLD - 16 MACROCELLS VDD P ins 3.3V or 5V uPSD33XX Port C JTAG and GPIO Port A,B,C PLD I/O and GPIO Port D GPIO AI07842 14/231 uPSD33xx MEMORY ORGANIZATION The 8032 MCU core views memory on the MCU module as “internal” memory and it views memory on the PSD module as “external” memory, see Figure 6. Internal memory on the MCU Module consists of DATA, IDATA, and SFRs. These standard 8032 memories reside in 384 bytes of SRAM located at a fixed address space starting at address 0x0000. External memory on the PSD Module consists of four types: main Flash (64K, 128K, or 256K bytes), a smaller secondary Flash (16K, or 32K), SRAM (2K, 8K, or 32K bytes), and a block of PSD Module control registers called CSIOP (256 bytes). These external memories reside at programmable address ranges, specified using the software tool PSDsoft Express. See the PSD Module section of this document for more details on these memories. External memory is accessed by the 8032 in two separate 64K byte address spaces. One address space is for program memory and the other adFigure 6. uPSD33xx Memories Internal SRAM on MCU Module External Memory on PSD Module dress space is for data memory. Program memory is accessed using the 8032 signal, PSEN . Data memory is accessed using the 8032 signals, RD and WR. If the 8032 needs to access more than 64K bytes of external program or data memory, it must use paging (or banking) techniques provided by the Page Register in the PSD Module. Note: W hen referencing program and data memory spaces, it has nothing to do with 8032 internal SRAM areas of DATA, IDATA, and SFR on the MCU Module. Program and data memory spaces only relate to the external memories on the PSD Module. External memory on the PSD Module can overlap the internal SRAM memory on the MCU Module in the same physical address range (starting at 0x0000) without interference because the 8032 core does not assert the RD or WR signals when accessing internal SRAM. Fixed Addresses FF Indirect Addressing Main Flash 384 Bytes SRAM 128 Bytes • External memories may be placed at virtually any address using software tool PSDsoft Express. • The SRAM and Flash memories may be placed in 8032 Program Space or Data Space using PSDsoft Express. • Any memory in 8032 Data Space is XDATA. IDATA 80 128 Bytes 7F SFR Direct Addressing 64KB, 128KB, or 256KB Secondary Flash SRAM 128 Bytes DATA 0 Direct or Indirect Addressing 16KB or 32KB 2KB, 8KB, or 32KB CSIOP 256 Bytes AI07843 15/231 uPSD33xx Internal Memory (MCU Module, Standard 8032 Memory: DATA, IDATA, SFR) DATA Memory. The first 128 bytes of internal SRAM ranging from address 0x0000 to 0x007F are called DATA, which can be accessed using 8032 direct or indirect addressing schemes and are typically used to store variables and stack. Four register banks, each with 8 registers (R0 – R7), occupy addresses 0x0000 to 0x001F. Only one of these four banks may be enabled at a time. The next 16 locations at 0x0020 to 0x002F contain 128 directly addressable bit locations that can be used as software flags. SRAM locations 0x0030 and above may be used for variables and stack. IDATA Memory. The next 128 bytes of internal SRAM are named IDATA and range from address 0x0080 to 0x00FF. IDATA can be accessed only through 8032 indirect addressing and is typically used to hold the MCU stack as well as data variables. The stack can reside in both DATA and IDATA memories and reach a size limited only by the available space in the combined 256 bytes of these two memories (since stack accesses are always done using indirect addressing, the boundary between DATA and IDATA does not exist with regard to the stack). SFR Memory. Special Function Registers (Table 5., page 24) occupy a separate physical memory, but they logically overlap the same 128 bytes as IDATA, ranging from address 0x0080 to 0x00FF. SFRs are accessed only using direct addressing. There 86 active registers used for many functions: changing the operating mode of the 8032 MCU core, controlling 8032 peripherals, controlling I/O, and managing interrupt functions. The remaining unused SFRs are reserved and should not be accessed. 16 of the SFRs are both byte- and bit-addressable. Bit-addressable SFRs are those whose address ends in “0” or “8” hex. External Memory (PSD Module: Program memory, Data memory) The PSD Module has four memories: main Flash, secondary Flash, SRAM, and CSIOP. See the PSD MODULE section for more detailed information on these memories. Memory mapping in the PSD Module is implemented with the Decode PLD (DPLD) and optionally the Page Register. The user specifies decode equations for individual segments of each of the memories using the software tool PSDsoft Express. This is a very easy point-and-click process allowing total flexibility in mapping memories. Additionally, each of the memories may be placed in various combinations of 8032 program address space or 8032 data address space by using the software tool PSDsoft Express. Program Memory. External program memory is addressed by the 8032 using its 16-bit Program Counter (PC) and is accessed with the 8032 signal, PSEN. Program memory can be present at any address in program space between 0x0000 and 0xFFFF. After a power-up or reset, the 8032 begins program execution from location 0x0000 where the reset vector is stored, causing a jump to an initialization routine in firmware. At address 0x0003, just following the reset vector are the interrupt service locations. Each interrupt is assigned a fixed interrupt service location in program memory. An interrupt causes the 8032 to jump to that service location, where it commences execution of the service routine. External Interrupt 0 (EXINT0), for example, is assigned to service location 0x0003. If EXINT0 is going to be used, its service routine must begin at location 0x0003. Interrupt service locations are spaced at 8-byte intervals: 0x0003 for EXINT0, 0x000B for Timer 0, 0x0013 for EXINT1, and so forth. If an interrupt service routine is short enough, it can reside entirely within the 8-byte interval. Longer service routines can use a jump instruction to somewhere else in program memory. Data Memory. External data is referred to as XDATA and is addressed by the 8032 using Indirect Addressing via its 16-bit Data Pointer Register (DPTR) and is accessed by the 8032 signals, RD and WR. XDATA can be present at any address in data space between 0x0000 and 0xFFFF. Note: the uPSD33xx has dual data pointers (source and destination) making XDATA transfers much more efficient. Memory Placement. PSD Module architecture allows the placement of its external memories into different combinations of program memory and data memory spaces. This means the main Flash, the secondary Flash, and the SRAM can be viewed by the 8032 MCU in various combinations of program memory or data memory as defined by PSDsoft Express. As an example of this flexibility, for applications that require a great deal of Flash memory in data space (large lookup tables or extended data recording), the larger main Flash memory can be placed in data space and the smaller secondary Flash memory can be placed in program space. The opposite can be realized for a different application if more Flash memory is needed for code and less Flash memory for data. 16/231 uPSD33xx By default, the SRAM and CSIOP memories on the PSD Module must always reside in data memory space and they are treated by the 8032 as XDATA. However, the SRAM may optionally reside in program space in addition to data space if it is desired to execute code from SRAM. The main Flash and secondary Flash memories may reside in program space, data space, or both. These memory placement choices specified by PSDsoft Express are programmed into non-volatile sections of the uPSD33xx, and are active at power-up and after reset. It is possible to override these initial settings during runtime for In-Application Programming (IAP). Standard 8032 MCU architecture cannot write to its own program memory space to prevent accidental corruption of firmware. However, this becomes an obstacle in typical 8032 systems when a remote update to firmware in Flash memory is required using IAP. The PSD module provides a solution for remote updates by allowing 8032 firmware to temporarily “reclassify” Flash memory to reside in data space during a remote update, then returning Flash memory back to program space when finished. See the VM Register (Table 78., page 143) in the PSD Module section of this document for more details. 8032 MCU CORE PERFORMANCE ENHANCEMENTS Before describing performance features of the uPSD33xx, let us first look at standard 8032 architecture. The clock source for the 8032 MCU creates a basic unit of timing called a machine-cycle, which is a period of 12 clocks for standard 8032 MCUs. The instruction set for traditional 8032 MCUs consists of 1, 2, and 3 byte instructions that execute in different combinations of 1, 2, or 4 machine-cycles. For example, there are one-byte instructions that execute in one machine-cycle (12 clocks), one-byte instructions that execute in four machine-cycles (48 clocks), two-byte, two-cycle instructions (24 clocks), and so on. In addition, standard 8032 architecture will fetch two bytes from program memory on almost every machinecycle, regardless if it needs them or not (dummy fetch). This means for one-byte, one-cycle instructions, the second byte is ignored. These one-byte, one-cycle instructions account for half of the 8032's instructions (126 out of 255 opcodes). There are inefficiencies due to wasted bus cycles and idle bus times that can be eliminated. The uPSD33xx 8032 MCU core offers increased performance in a number of ways, while keeping the exact same instruction set as the standard 8032 (all opcodes, the number of bytes per instruction, and the native number a machine-cycles per instruction are identical to the original 8032). The first way performance is boosted is by reducing the machine-cycle period to just 4 MCU clocks as compared to 12 MCU clocks in a standard 8032. This shortened machine-cycle improves the instruction rate for one-byte, one-cycle instructions by a factor of three (Figure 7., page 18) compared to standard 8051 architectures, and significantly improves performance of multiple-cycle instruction types. The example in Figure 7 shows a continuous execution stream of one-byte, one-cycle instructions. The 5V uPSD33xx will yield 10 MIPS peak performance in this case while operating at 40MHz clock rate. In a typical application however, the effective performance will be lower since programs do not use only one-cycle instructions, but special techniques are implemented in the uPSD33xx to keep the effective MIPS rate as close as possible to the peak MIPS rate at all times. This is accomplished with an instruction Pre-Fetch Queue (PFQ) and a Branch Cache (BC) as shown in Figure 8., page 18. 17/231 uPSD33xx Figure 7. Comparison of uPSD33xx with Standard 8032 Performance 1-byte, 1-Cycle Instructions Instruction A Turbo uPSD33XX Execute Instruction and Pre-Fetch Next Instruction Instruction B Execute Instruction and Pre-Fetch Next Instruction Instruction C Execute Instruction and Pre-Fetch Next Instruction 4 clocks (one machine cycle) one machine cycle one machine cycle MCU Clock 12 clocks (one machine cycle) Instruction A Standard 8032 Fetch Byte for Instruction A Execute Instruction A and Fetch a Second Dummy Byte Dummy Byte is Ignored (wasted bus access) Turbo uPSD33XX executes instructions A, B, and C in the same amount of time that a standard 8032 executes only instruction A. AI08808 Figure 8. Instruction Pre-Fetch Queue and Branch Cache Branch 4 Code Branch Cache (BC) Branch 4 Code Branch 4 Code Branch 4 Code Branch 4 Code Branch 4 Code Previous Branch 4 Compare Branch 3 Branch 3 Branch 3 Branch 3 Branch 3 Branch 3 Previous Code Code Code Code Code Code Branch 3 Branch 2 Branch 2 Branch 2 Branch 2 Branch 2 Branch 2 Previous Code Branch 2 Code Code Code Code Code Branch 1 Code Branch 1 Code Branch 1 Code Branch 1 Code Branch 1 Code Branch 1 Code Previous Branch 1 Address Load on Branch Address Match Current Branch Address Instruction Byte Program Memory on PSD Module 8 Instruction Byte 8 8032 MCU Address 16 6 Bytes of Instruction Address 16 Wait Instruction Pre-Fetch Queue (PFQ) Stall AI08809 18/231 uPSD33xx Pre-Fetch Queue (PFQ) and Branch Cache (BC) The PFQ is always working to minimize the idle bus time inherent to 8032 MCU architecture, to eliminate wasted memory fetches, and to maximize memory bandwidth to the MCU. The PFQ does this by running asynchronously in relation to the MCU, looking ahead to pre-fetch code from program memory during any idle bus periods. Only necessary bytes will be fetched (no dummy fetches like standard 8032). The PFQ will queue up to six code bytes in advance of execution, which significantly optimizes sequential program performance. However, when program execution becomes non-sequential (program branch), a typical pre-fetch queue will empty itself and reload new code, causing the MCU to stall. The Turbo uPSD33xx diminishes this problem by using a Branch Cache with the PFQ. The BC is a four-way, fully associative cache, meaning that when a program branch occurs, it's branch destination address is compared simultaneously with four recent previous branch destinations stored in the BC. Each of the four cache entries contain up to six bytes of code related to a branch. If there is a hit (a match), then all six code bytes of the matching program branch are transferred immediately and simultaneously from the BC to the PFQ, and execution on that branch continues with minimal delay. This greatly reduces the chance that the MCU will stall from an empty PFQ, and improves performance in embedded control systems where it is quite common to branch and loop in relatively small code localities. By default, the PFQ and BC are enabled after power-up or reset. The 8032 can disable the PFQ and BC at runtime if desired by writing to a specific SFR (BUSCON). The memory in the PSD module operates with variable wait states depending on the value specified in the SFR named BUSCON. For example, a 5V uPSD33xx device operating at a 40MHz crystal frequency requires four memory wait states (equal to four MCU clocks). In this example, once the PFQ has one or more bytes of code, the wait states become transparent and a full 10 MIPS is achieved when the program stream consists of sequential one-byte, one machine-cycle instructions as shown in Figure 7., page 18 (transparent because a machine-cycle is four MCU clocks which equals the memory pre-fetch wait time that is also four MCU clocks). But it is also important to understand PFQ operation on multi-cycle instructions. PFQ Example, Multi-cycle Instructions Let us look at a string of two-byte, two-cycle instructions in Figure 9., page 20. There are three instructions executed sequentially in this example, instructions A, B, and C. Each of the time divisions in the figure is one machine-cycle of four clocks, and there are six phases to reference in this discussion. Each instruction is pre-fetched into the PFQ in advance of execution by the MCU. Prior to Phase 1, the PFQ has pre-fetched the two instruction bytes (A1 and A2) of instruction A. During Phase one, both bytes are loaded into the MCU execution unit. Also in Phase 1, the PFQ is prefetching the first byte (B1) of instruction B from program memory. In Phase 2, the MCU is processing Instruction A internally while the PFQ is pre-fetching the second byte (B2) of Instruction B. In Phase 3, both bytes of instruction B are loaded into the MCU execution unit and the PFQ begins to pre-fetch bytes for the third instruction C. In Phase 4 Instruction B is processed and the prefetching continues, eliminating idle bus cycles and feeding a continuous flow of operands and opcodes to the MCU execution unit. The uPSD33xx MCU instructions are an exact 1/3 scale of all standard 8032 instructions with regard to number of cycles per instruction. Figure 10., page 20 shows the equivalent instruction sequence from the example above on a standard 8032 for comparison. Aggregate Performance The stream of two-byte, two-cycle instructions in Figure 9., page 20, running on a 40MHz, 5V, uPSD33xx will yield 5 MIPs. And we saw the stream of one-byte, one-cycle instructions in Figure 7., page 18, on the same MCU yield 10 MIPs. Effective performance will depend on a number of things: the MCU clock frequency; the mixture of instructions types (bytes and cycles) in the application; the amount of time an empty PFQ stalls the MCU (mix of instruction types and misses on Branch Cache); and the operating voltage. A 5V uPSD33xx device operates with four memory wait states, but a 3.3V device operates with five memory wait states yielding 8 MIPS peak compared to 10 MIPs peak for 5V device. The same number of wait states will apply to both program fetches and to data READ/WRITEs unless otherwise specified in the SFR named BUSCON. In general, a 3X aggregate performance increase is expected over any standard 8032 application running at the same clock frequency. 19/231 uPSD33xx Figure 9. PFQ Operation on Multi-cycle Instructions Three 2-byte, 2-cycle Instructions on uPSD33XX Pre-Fetch Inst A Pre-Fetch Inst B Pre-Fetch Inst C PFQ Inst A, Byte 1 Inst A, Byte 2 Inst B, Byte 1 Inst B, Byte 2 Inst C, Byte 1 Inst C, Byte 2 4-clock Macine Cycle Continue to Pre-Fetch Phase 1 MCU Execution Previous Instruction A1 A2 Phase 2 Process A Phase 3 B1 B2 Phase 4 Process B Phase 5 C1 C2 Phase 6 Process C Next Inst Instruction A Instruction B Instruction C AI08810 Figure 10. uPSD33xx Multi-cycle Instructions Compared to Standard 8032 Three 2-byte, 2-cycle Instructions, uPSD33XX vs. Standard 8032 24 Clocks Total (4 clocks per cycle) uPSD33XX A1 A2 Inst A B1 B2 Inst B C1 C2 Inst C 1 Cycle 72 Clocks (12 clocks per cycle) Std 8032 Byte 1 Byte 2 Process Inst A 1 Cycle AI08811 Byte 1 Byte 2 Process Inst B Byte 1 Byte 2 Process Inst C 20/231 uPSD33xx MCU MODULE DISCRIPTION This section provides a detail description of the MCU Module system functions and peripherals, including: ■ 8032 MCU Registers ■ Special Function Registers ■ 8032 Addressing Modes ■ uPSD33xx Instruction Set Summary ■ Dual Data Pointers ■ Debug Unit ■ Interrupt System ■ MCU Clock Generation ■ Power Saving Modes ■ Oscillator and External Components I/O Ports MCU Bus Interface ■ Supervisory Functions ■ Standard 8032 Timer/Counters ■ Serial UART Interfaces ■ IrDA Interface ■ I2C Interface ■ SPI Interface ■ Analog to Digital Converter ■ Programmable Counter Array (PCA) Note: A full description of the 8032 instruction set may be found in the uPSD33xx Programmers Guide. ■ ■ 8032 MCU REGISTERS The uPSD33xx has the following 8032 MCU core registers, also shown in Figure 11. Figure 11. 8032 MCU Registers A B SP PCH PCL PSW R0-R7 DPTR(DPH) AI06636 Accumulator B Register Stack Pointer Program Counter Program Status Word General Purpose Register (Bank0-3) Data Pointer Register DPTR(DPL) Stack Pointer (SP) The SP is an 8-bit register which holds the current location of the top of the stack. It is incremented before a value is pushed onto the stack, and decremented after a value is popped off the stack. The SP is initialized to 07h after reset. This causes the stack to begin at location 08h (top of stack). To avoid overlapping conflicts, the user must initialize the top of the stack to 20h if all four banks of registers R0 - R7 are used, and the user must initialize the top of stack to 30h if all of the 8032 bit memory locations are used. Data Pointer (DPTR) DPTR is a 16-bit register consisting of two 8-bit registers, DPL and DPH. The DPTR Register is used as a base register to create an address for indirect jumps, table look-up operations, and for external data transfers (XDATA). When not used for addressing, the DPTR Register can be used as a general purpose 16-bit data register. Very frequently, the DPTR Register is used to access XDATA using the External Direct addressing mode. The uPSD33xx has a special set of SFR registers (DPTC, DPTM) to control a secondary DPTR Register to speed memory-to-memory XDATA transfers. Having dual DPTR Registers allows rapid switching between source and destination addresses (see details in DUAL DATA POINTERS, page 37). Program Counter (PC) The PC is a 16-bit register consisting of two 8-bit registers, PCL and PCH. This counter indicates the address of the next instruction in program memory to be fetched and executed. A reset forces the PC to location 0000h, which is where the reset jump vector is stored. Accumulator (ACC) This is an 8-bit general purpose register which holds a source operand and receives the result of arithmetic operations. The ACC Register can also be the source or destination of logic and data movement operations. For MUL and DIV instructions, ACC is combined with the B Register to hold 16-bit operands. The ACC is referred to as “A” in the MCU instruction set. B Register (B) The B Register is a general purpose 8-bit register for temporary data storage and also used as a 16bit register when concatenated with the ACC Register for use with MUL and DIV instructions. 21/231 uPSD33xx General Purpose Registers (R0 - R7) There are four banks of eight general purpose 8bit registers (R0 - R7), but only one bank of eight registers is active at any given time depending on the setting in the PSW word (described next). R0 R7 are generally used to assist in manipulating values and moving data from one memory location to another. These register banks physically reside in the first 32 locations of 8032 internal DATA SRAM, starting at address 00h. At reset, only the first bank of eight registers is active (addresses 00h to 07h), and the stack begins at address 08h. Program Status Word (PSW) The PSW is an 8-bit register which stores several important bits, or flags, that are set and cleared by many 8032 instructions, reflecting the current state of the MCU core. Figure 12., page 22 shows the individual flags. Carry Flag (CY). This flag is set when the last arithmetic operation that was executed results in a carry (addition) or borrow (subtraction). It is cleared by all other arithmetic operations. The CY flag is also affected by Shift and Rotate Instructions. Auxiliary Carry Flag (AC). This flag is set when the last arithmetic operation that was executed results in a carry into (addition) or borrow from (subtraction) the high-order nibble. It is cleared by all other arithmetic operations. Figure 12. Program Status Word (PSW) Register MSB PSW Carry Flag Auxillary Carry Flag General Purpose Flag Register Bank Select Flags (to select Bank0-3) AI06639 General Purpose Flag (F0). This is a bit-addressable, general-purpose flag for use under software control. Register Bank Select Flags (RS1, RS0). These bits select which bank of eight registers is used during R0 - R7 register accesses (see Table 4) Overflow Flag (OV). The OV flag is set when: an ADD, ADDC, or SUBB instruction causes a sign change; a MUL instruction results in an overflow (result greater than 255); a DIV instruction causes a divide-by-zero condition. The OV flag is cleared by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. The CLRV instruction will clear the OV flag at any time. Parity Flag (P). The P flag is set if the sum of the eight bits in the Accumulator is odd, and P is cleared if the sum is even. Table 4. .Register Bank Select Addresses RS1 0 0 1 1 RS0 0 1 0 1 Register Bank 0 1 2 3 8032 Internal DATA Address 00h - 07h 08h - 0Fh 10h - 17h 18h - 1Fh LSB P Reset Value 00h Parity Flag Bit not assigned Overflow Flag CY AC FO RS1 RS0 OV 22/231 uPSD33xx SPECIAL FUNCTION REGISTERS (SFR) A group of registers designated as Special Function Register (SFR) is shown in Table 5., page 24. SFRs control the operating modes of the MCU core and also control the peripheral interfaces and I/O pins on the MCU Module. The SFRs can be accessed only by using the Direct Addressing method within the address range from 80h to FFh of internal 8032 SRAM. Sixteen addresses in SFR address space are both byte- and bit-addressable. The bit-addressable SFRs are noted in Table 5. 86 of a possible 128 SFR addresses are occupied. The remaining unoccupied SFR addresses (designated as “RESERVED” in Table 5) should not be written. Reading unoccupied locations will return an undefined value. Note: There is a separate set of control registers for the PSD Module, designated as csiop, and they are described in the PSD MODULE, page 133. The I/O pins, PLD, and other functions on the PSD Module are NOT controlled by SFRs. SFRs are categorized as follows: ■ MCU core registers: IP, A, B, PSW, SP, DPTL, DPTH, DPTC, DPTM ■ MCU Module I/O Port registers: P1, P3, P4, P1SFS0, P1SFS1, P3SFS, P4SFS0, P4SFS1 ■ Standard 8032 Timer registers TCON, TMOD, T2CON, TH0, TH1, TH2, TL0, TL1, TL2, RCAP2L, RCAP2H ■ Standard Serial Interfaces (UART) ■ ■ ■ ■ ■ ■ ■ ■ ■ SCON0, SBUF0, SCON1, SBUF1 Power, clock, and bus timing registers PCON, CCON0, BUSCON Hardware watchdog timer registers WDKEY, WDRST Interrupt system registers IP, IPA, IE, IEA Prog. Counter Array (PCA) control registers PCACL0, PCACH0, PCACON0, PCASTA, PCACL1, PCACH1, PCACON1, CCON2, CCON3 PCA capture/compare and PWM registers CAPCOML0, CAPCOMH0, TCMMODE0, CAPCOML1, CAPCOMH1, TCMMODE2, CAPCOML2, CAPCOMH2, TCMMODE2, CAPCOML3, CAPCOMH3, TCMMODE3, CAPCOML4, CAPCOMH4, TCMMODE4, CAPCOML5, CAPCOMH5, TCMMODE5, PWMF0, PMWF1 SPI interface registers SPICLKD, SPISTAT, SPITDR, SPIRDR, SPICON0, SPICON1 I2C interface registers S1SETUP, S1CON, S1STA, S1DAT, S1ADR Analog to Digital Converter registers ACON, ADCPS, ADAT0, ADAT1 IrDA interface register IRDACON 23/231 uPSD33xx Table 5. SFR Memory Map with Direct Address and Reset Value SFR Addr (hex) 80 SFR Name Bit Name and 7 6 5 4 3 2 1 0 Reset Reg. Value Descr. (hex) with Link RESERVED Stack Pointer (SP), page 21 Data Pointer (DPTR), p age 21 81 SP SP[7:0] 07 82 83 84 85 DPL DPH DPL[7:0] DPH[7:0] RESERVED 00 00 DPTC – AT – – – DPSEL[2:0] 00 Table 13., page 37 Table 14., page 38 Table 24., page 50 Table 39., page 70 Table 40., page 72 Standard Timer SFRs, pag e 69 Table 29., page 60 Table 30., page 60 Table 25., page 57 Table 28., page 60 Table 32., page 61 Table 33., page 61 86 DPTM – – – – MD1[1:0] MD0[1:0] 00 87 PCON SMOD0 SMOD1 – POR RCLK1 TCLK1 PD IDLE 00 88(1) TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 89 8A 8B 8C 8D 8E TMOD TL0 TL1 TH0 TH1 P1SFS0 GATE C/T M1 M0 TL0[7:0] TL1[7:0] TH0[7:0] TH1[7:0] GATE C/T M1 M0 00 00 00 00 00 00 P1SFS0[7:0] 8F P1SFS1 P1SFS1[7:0] 00 90(1) P1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 FF 91 P3SFS P3SFS[7:0] 00 92 P4SFS0 P4SFS0[7:0] 00 93 P4SFS1 P4SFS1[7:0] 00 24/231 uPSD33xx SFR Addr (hex) 94 SFR Name Bit Name and 7 – 6 – 5 – 4 – 3 ADCCE 2 1 ADCPS[2:0] 0 Reset Reg. Value Descr. (hex) with Link 00 Table 64., page 122 Table 65., page 122 Table 66., page 122 Table 63., page 121 Table 45., page 82 Figure 25., page 79 ADCPS 95 ADAT0 ADATA[7:0] 00 96 ADAT1 – – – – – – ADATA[9:8] 00 97 ACON AINTF AINTEN ADEN ADS[2:0] ADST ADSF 00 98(1) SCON0 SM0 SM1 SM2 REN TB8 RB8 TI RI 00 99 9A 9B 9C 9D 9E 9F A0 A1 A2 SBUF0 SBUF0[7:0] RESERVED RESERVED RESERVED 00 BUSCON EPFQ EBC WRW1 WRW0 RDW1 RDW0 CW1 CW0 EB Table 35., page 63 RESERVED RESERVED RESERVED RESERVED PCACL0 PCACL0[7:0] 00 Table 67., page 124 Table 67., page 124 Table 70., page 129 Table 72., page 131 Table 38., page 68 Table 18., page 44 A3 PCACH0 PCACH0[7:0] 00 A4 PCACON0 EN_ALL EN_PCA EOVF1 PCA_IDL – – CLK_SEL[1:0] 00 A5 PCASTA OVF1 INTF5 INTF4 INTF3 OVF0 INTF2 INTF1 INTF0 00 A6 WDTRST WDTRST[7:0] 00 A7 IEA EADC ESPI EPCA ES1 – – EI2C – 00 25/231 uPSD33xx SFR Addr (hex) A8(1) SFR Name Bit Name and 7 EA 6 – 5 ET2 4 ES0 3 ET1 2 EX1 1 0 Reset Reg. Value Descr. (hex) with Link 00 Table 17., page 43 IE ET0 EX0 PWM[1:0] PWM[1:0] PWM[1:0] A9 AA AB AC AD TCMMODE EINTF 0 TCMMODE EINTF 1 TCMMODE EINTF 2 CAPCOML 0 CAPCOMH 0 WDTKEY E_COMP CAP_PE E_COMP CAP_PE E_COMP CAP_PE CAP_NE MATCH TOGGLE CAP_NE MATCH TOGGLE CAP_NE MATCH TOGGLE CAPCOML0[7:0] CAPCOMH0[7:0] 00 00 00 00 00 Table 67., page 124 Table 37., page 68 Table 67., page 124 Table 26., page 58 Table 73., page 132 AE WDTKEY[7:0] 55 AF CAPCOML 1 P3.7 P3.6 P3.5 CAPCOML1[7:0] 00 B0(1) P3 CAPCOMH 1 CAPCOML 2 CAPCOMH 2 PWMF0 P3.4 P3.3 P3.2 P3.1 P3.0 FF B1 B2 B3 B4 B5 B6 B7 CAPCOMH1[7:0] CAPCOML2[7:0] CAPCOMH2[7:0] PWMF0[7:0] RESERVED RESERVED 00 00 00 00 Table 67., page 124 IPA PADC PSPI PPCA PS1 – – PI2C – 00 Table 20., page 45 Table 19., page 44 B8(1) B9 BA BB BC IP – – PT2 PS0 PT1 PX1 PT0 PX0 00 RESERVED PCACL1 PCACH1 PCACON1 – EN_PCA EOVF1 PCACL1[7:0] PCACH1[7:0] PCA_IDL – – CLK_SEL[1:0] 00 00 00 Table 67., page 124 Table 71., page 130 26/231 uPSD33xx SFR Addr (hex) BD BE BF SFR Name Bit Name and 7 6 5 4 3 2 1 0 Reset Reg. Value Descr. (hex) with Link 00 00 00 Table 27., page 58 Table 73., page 132 TCMMODE EINTF 3 TCMMODE EINTF 4 TCMMODE EINTF 5 P4 CAPCOML 3 CAPCOMH 3 CAPCOML 4 CAPCOMH 4 CAPCOML 5 CAPCOMH 5 PWMF1 T2CON TF2 P4.7 E_COMP CAP_PE E_COMP CAP_PE E_COMP CAP_PE P4.6 P4.5 CAP_NE MATCH TOGGLE CAP_NE MATCH TOGGLE CAP_NE MATCH TOGGLE P4.4 P4.3 P4.2 PWM[1:0] PWM[1:0] PWM[1:0] P4.1 P4.0 C0(1) FF C1 C2 C3 C4 C5 C6 C7 C8(1) C9 CA CB CC CD CE CAPCOML3[7:0] CAPCOMH3[7:0] CAPCOML4[7:0] CAPCOMH4[7:0] CAPCOML5[7:0] CAPCOMH5[7:0] PWMF1[7:0] EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/ RL2 00 00 00 00 00 00 00 00 Table 41., page 75 Table 67., page 124 RESERVED RCAP2L RCAP2H TL2 TH2 IRDACON – IRDA_EN BIT_PULS RCAP2L[7:0] RCAP2H[7:0] TL2[7:0] TH2[7:0] CDIV4 CDIV3 CDIV2 CDIV1 CDIV0 00 00 00 00 0F Table 48., page 93 Program Status Word (PSW), pa ge 22 Standard Timer SFRs, pag e 69 D0(1) PSW CY AC F0 RS[1:0] OV – P 00 D1 D2 SPICLKD RESERVED SPICLKD[5:0] – – 04 Table 61., page 118 Table 62., page 119 D3 SPISTAT – – – BUSY TEISF RORISF TISF RISF 02 27/231 uPSD33xx SFR Addr (hex) D4 D5 D6 SFR Name SPITDR SPIRDR SPICON0 – TE RE Bit Name and 7 6 5 4 SPITDR[7:0] SPIRDR[7:0] SPIEN SSEL FLSB SPO – 3 2 1 0 Reset Reg. Value Descr. (hex) with Link 00 00 00 Table 62., page 119 Table 59., page 117 Table 60., page 118 Table 46., page 83 Figure 25., page 79 D7 SPICON1 – – – – TEIE RORIE TIE RIE 00 D8(1) SCON1 SM0