UPSD3432E-40U6T

uPSD34xx Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic Features summary ■ Figure 1. Packages Fast 8-bit Turbo 8032 MCU, 40 MHz – Advanced core, 4-clocks per instruction – 10 MIPs peak performance at 40MHz (5V) – JTAG Debug and In-System Programming – 16-bit internal instruction path fetches double-byte instruction in a single memory cycle – Branch Cache & 4 instruction Prefetch Queue – Dual XDATA pointers with automatic increment and decrement – Compatible with 3rd party 8051 tools Dual Flash memories with memory management – Place either memory into 8032 program address space or data address space – READ-while-WRITE operation for InApplication Programming and EEPROM emulation – Single voltage program and erase – 100K guaranteed erase cycles, 15-year retention Clock, reset, and power supply management – SRAM is Battery Backup capable – Flexible 8-level CPU clock divider register – Normal, Idle, and Power Down Modes – Power-on and Low Voltage reset supervisor – Programmable Watchdog Timer Programmable logic, general purpose – 16 macrocells for logic applications (e.g., shifters, state machines, chip-selects, gluelogic to keypads, and LCDs) A/D converter – Eight Channels, 10-bit resolution, 6µs TQFP52 (T), 52-lead, Thin, Quad, Flat TQFP80 (U), 80-lead, Thin, Quad, Flat ■ ■ Communication interfaces – USB v2.0 Full Speed (12Mbps) – 10 endpoint pairs (In/Out), each endpoint with 64-byte FIFO (supports Control, Intr, and Bulk transfer types) – I2C Master/Slave controller, 833kHz – SPI Master controller, 10MHz – Two UARTs with independent baud rate – IrDA Potocol: up to 115 kbaud – Up to 46 I/O, 5V tolerant uPSD34xxV Timers and interrupts – Three 8032 standard 16-bit timers – Programmable Counter Array (PCA), six 16-bit modules for PWM, CAPCOM, and timers – 8/10/16-bit PWM operation – 12 Interrupt sources with two external interrupt pins Operating voltage source (±10%) – 5V Devices: 5.0V and 3.3V sources – 3.3V Devices: 3.3V source ■ ■ ■ ■ ■ July 2006 Rev 4 1/293 www.st.com 293 uPSD34xx Table 1. Device Summary Max MHz 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 1st Flash 2nd Flash (bytes) uPSD3422E-40T6 uPSD3422EV-40T6 uPSD3422E-40U6 uPSD3422EV-40U6 uPSD3433E-40T6 uPSD3433EV-40T6 uPSD3433E-40U6 uPSD3433EV-40U6 uPSD3434E-40T6 uPSD3434EV-40T6 uPSD3434E-40U6 uPSD3434EV-40U6 uPSD3454E-40T6 uPSD3454EV-40T6 uPSD3454E-40U6 uPSD3454EV-40U6 uPSD3422EB40T6 uPSD3422EVB40T6 uPSD3422EB40U6 uPSD3422EVB40U6 uPSD3433EB40T6 uPSD3433EVB40T6 uPSD3433EB40U6 uPSD3433EVB40U6 uPSD3434EB40T6 uPSD3434EVB40T6 uPSD3434EB40U6 uPSD3434EVB40U6 uPSD3454EB40T6 uPSD3454EVB40T6 uPSD3454EB40U6 uPSD3454EVB40U6 64K 64K 64K 64K 128K 128K 128K 128K 256K 256K 256K 256K 256K 256K 256K 256K 64K 64K 64K 64K 128K 128K 128K 128K 256K 256K 256K 256K 256K 256K 256K 256K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 8K 8K 8K 8K 8K 8K 8K 8K 32K 32K 32K 32K 4K 4K 4K 4K 8K 8K 8K 8K 8K 8K 8K 8K 32K 32K 32K 32K 35 35 46 46 35 35 46 46 35 35 46 46 35 35 46 46 35 35 46 46 35 35 46 46 35 35 46 46 35 35 46 46 No No Yes Yes No No Yes Yes No No Yes Yes No No Yes Yes No No Yes Yes No No Yes Yes No No Yes Yes No No Yes Yes 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 SRAM GPIO 8032 Bus VCC VDD Pkg. Part Number Note: 2/293 Operating temperature is in the Industrial range (–40°C to 85°C). uPSD34xx Contents Contents 1 2 3 4 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 4.2 Internal memory (MCU module, standard 8032 memory: DATA, IDATA, SFR) 20 External memory (PSD module: program memory, data memory) . . . . . 20 5 8032 MCU core performance enhancements . . . . . . . . . . . . . . . . . . . . 23 5.1 5.2 5.3 Pre-fetch queue (PFQ) and branch cache (BC) . . . . . . . . . . . . . . . . . . . . 24 PFQ example, multi-cycle instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Aggregate performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 7 MCU module description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8032 MCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Data pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 B register (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 General purpose registers (R0 - R7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program status word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 9 Special function registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8032 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 9.2 9.3 9.4 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3/293 Contents uPSD34xx 9.5 9.6 9.7 9.8 9.9 9.10 9.11 External Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 External Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Absolute Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Long Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 11 uPSD34xx instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Dual data pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1 11.2 Data pointer control register, DPTC (85h) . . . . . . . . . . . . . . . . . . . . . . . . 47 Data pointer mode register, DPTM (86h) . . . . . . . . . . . . . . . . . . . . . . . . . 48 12 13 Debug unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.1 Individual interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14 MCU clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 14.1 14.2 MCU_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PERIPH_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 15.1 15.2 15.3 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Reduced Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16 17 Oscillator and external components . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I/O ports of mcu module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 17.1 MCU port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 18 MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.1 18.2 PSEN bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 READ or WRITE bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4/293 uPSD34xx Contents 18.3 18.4 18.5 Connecting external devices to the MCU bus . . . . . . . . . . . . . . . . . . . . . 78 Programmable bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Controlling the PFQ and BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 19 Supervisory functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 19.1 19.2 19.3 19.4 19.5 External reset input pin, RESET_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Low VCC voltage detect, LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 JTAG debug reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Watchdog timer, WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 20 Standard 8032 timer/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 20.1 20.2 20.3 20.4 20.5 20.6 Standard timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SFR, TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SFR, TMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Timer 0 and Timer 1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 21 Serial UART interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 21.1 21.2 21.3 21.4 21.5 21.6 UART operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Serial port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 UART baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 More about UART mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 More about UART mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 More About UART Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 22 IrDA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 22.1 22.2 Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Pulse width selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 23 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 23.1 23.2 23.3 I2C interface main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5/293 Contents uPSD34xx 23.4 23.5 23.6 23.7 23.8 23.9 Bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 General call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Serial I/O engine (SIOE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 I2C interface control register (S1CON) . . . . . . . . . . . . . . . . . . . . . . . . . . 121 I2C interface status register (S1STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 23.10 I2C data shift register (S1DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 23.11 I2C address register (S1ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 23.12 I2C START sample setting (S1SETUP) . . . . . . . . . . . . . . . . . . . . . . . . . 125 23.13 I2C operating sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 24 SPI (synchronous peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . 134 24.1 24.2 24.3 24.4 24.5 24.6 SPI bus features and communication flow . . . . . . . . . . . . . . . . . . . . . . . 135 Full-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Bus-level activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SPI SFR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Dynamic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 25 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 25.1 25.2 25.3 25.4 25.5 Basic USB concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Types of transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Endpoint FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 USB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Typical connection to USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 26 Analog-to-digital convertor (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 26.1 Port 1 ADC channel selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 27 Programmable counter array (PCA) with PWM . . . . . . . . . . . . . . . . . 175 27.1 27.2 27.3 27.4 PCA block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 PCA Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Operation of TCM modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6/293 uPSD34xx Contents 27.5 27.6 27.7 27.8 27.9 Timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Toggle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 PWM mode - (x8), fixed frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 PWM mode - (x8), programmable frequency . . . . . . . . . . . . . . . . . . . . . 179 PWM mode - fixed frequency, 16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 27.10 PWM mode - fixed frequency, 10-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 27.11 Writing to capture/compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 27.12 Control register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 27.13 TCM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 28 PSD module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 28.1 28.2 28.3 28.4 28.5 28.6 PSD module functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 PSD module data bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Runtime control register definitions (csiop) . . . . . . . . . . . . . . . . . . . . . . 199 PSD module detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 PSD module reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 29 30 31 32 33 34 AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 34.1 34.2 34.3 34.4 34.5 34.6 USB interrupts with idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 USB Reset Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 USB Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 USB FIFO Accessibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Erroneous Resend of Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 7/293 Contents uPSD34xx 34.7 34.8 34.9 IN FIFO Pairing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 OUT FIFO Pairing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Missing ACK to host retransmission of SETUP packet . . . . . . . . . . . . . 289 34.10 MCU JTAG ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 34.11 PORT 1 Not 5-volt IO Tolerant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 34.12 Incorrect Code Execution when Code Banks are Switched . . . . . . . . . . 291 34.13 9th Received Data Bit Corrupted in UART Modes 2 and 3 . . . . . . . . . . 291 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 8/293 uPSD34xx Summary description 1 Summary description The Turbo Plus uPSD34xx Series combines a powerful 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix to form an ideal embedded controller. At its core is a fast 4-cycle 8032 MCU with a 4-byte instruction prefetch queue (PFQ) and a 4-entry fully associative branching cache (BC). The MCU is connected to a 16-bit internal instruction path to maximize performance, enabling loops of code in smaller localities to execute extremely fast. The 16-bit wide instruction path in the Turbo Plus Series allows double-byte instructions to be fetched from memory in a single memory cycle. This keeps the average performance near its peak performance (peak performance for 5V, 40MHz Turbo Plus uPSD34xx is 10 MIPS for single-byte instructions, and average performance will be approximately 9 MIPS for mix of single- and multi-byte instructions). USB 2.0 (full speed, 12Mbps) is included, providing 10 endpoints, each with its own 64-byte FIFO to maintain high data throughput. Endpoint 0 (Control Endpoint) uses two of the 10 endpoints for In and Out directions, the remaining eight endpoints may be allocated in any mix to either type of transfers: Bulk or Interrupt. Code development is easily managed without a hardware In-Circuit Emulator by using the serial JTAG debug interface. JTAG is also used for In-System Programming (ISP) in as little as 10 seconds, perfect for manufacturing and lab development. The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize the 8032 memory structure, offering two independent banks of Flash memory that can be placed at virtually any address within 8032 program or data address space, and easily paged beyond 64K bytes using onchip programmable decode logic. Dual Flash memory banks provide a robust solution for remote product updates in the field through In-Application Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating the need for external EEPROM chips. General purpose programmable logic (PLD) is included to build an endless variety of gluelogic, saving external logic devices. The PLD is configured using the software development tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge. The uPSD34xx also includes supervisor functions such as a programmable watchdog timer and low-voltage reset. Note: For a list of known limitations of the uPSD34xx devices, please refer to Section 34: Important notes. 9/293 Summary description Figure 2. Block Diagram uPSD34xx (3) 16-bit Timer/ Counters (2) External Interrupts Turbo 8032 Core PFQ & BC uPSD34xx Programmable Decode and Page Logic 1st Flash Memory: 64K, 128K, or 256K Bytes 2nd Flash Memory: 32K Bytes SRAM: 4K, 8K or 32K Bytes P3.0:7 I2C UART0 (8) GPIO, Port A (80-pin only) (8) GPIO, Port 3 General Purpose Programmable Logic, 16 Macrocells (8) GPIO, Port B (2) GPIO, Port D (4) GPIO, Port C PA0:7 PB0:7 PD1:2 (8) 10-bit ADC Optional IrDA Encoder/Decoder SYSTEM BUS P1.0:7 (8) GPIO, Port 1 PC0:7 JTAG ICE and ISP 8032 Address/Data/Control Bus (80-pin device only) Supervisor: Watchdog and Low-Voltage Reset VCC, VDD, GND, Reset, Crystal In UART1 SPI 16-bit PCA (6) PWM, CAPCOM, TIMER MCU Bus P4.0:7 USB+, USB– (8) GPIO, Port 4 Dedicated Pins USB v2.0, Full Speed 10 FIFOs AI09695b 10/293 uPSD34xx Pin descriptions 2 Pin descriptions Figure 3. TQFP52 connections 40 P1.6/SPITXD(2)/ADC6 41 P1.7/SPISEL(2)/ADC7 47 AVCC/AVREF(3) 46 PB5 44 RESET_IN 45 GND 43 PB6 42 PB7 52 PB0 51 PB1 50 PB2 49 PB3 48 PB4 PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 DEBUG 5 3.3V VCC 6 USB+ 7 VDD(1) 8 GND 9 USB– 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13 39 P1.5/SPIRXD(2)/ADC5 38 P1.4/SPICLK(2)/ADC4 37 P1.3/TXD1(IrDA)(2)/ADC3 36 P1.2/RXD1(IrDA)(2)/ADC2 35 P1.1/T2X(2)/ADC1 34 P1.0/T2(2)/ADC0 33 VDD(1) 32 XTAL2 31 XTAL1 30 P3.7/SCL 29 P3.6/SDA 28 P3.5/C1 27 P3.4/C0 SPISEL(2)/PCACLK1/P4.7 14 SPITXD(2)/TCM5/P4.6 15 SPIRXD(2)/TCM4/P4.5 16 SPICLK(2)/TCM3/P4.4 17 TXD1(IrDA)(2)/PCACLK0/P4.3 18 GND 19 RXD1(IrDA)(2)/TCM2/P4.2 20 T2X(2)/TCM1/P4.1 21 T2(2)/TCM0/P4.0 22 RXD0/P3.0 23 TXD0/P3.1 24 EXTINT0/TG0/P3.2 25 EXTINT1/TG1/P3.3 26 AI09696b Note: 1 2 3 For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1. AVREF and 3.3V AVCC are shared in the 52-pin package only. ADC channels must use 3.3V as AVREF for the 52-pin package. 11/293 Pin descriptions Figure 4. TQFP80 connections 61 P1.6/SPITXD(3)/ADC6 64 P1.7/SPISEL(3)/ADC7 79 P3.2/EXINT0/TG0 uPSD34xx 75 P3.0/RXD0 77 P3.1/TXD0 68 RESET_IN 70 AVREF 69 GND 63 PSEN 72 AVCC 80 PB0 78 PB1 76 PB2 74 PB3 73 PB4 71 PB5 67 PB6 66 PB7 62 WR 65 RD PD2/CSI 1 P3.3/TG1/EXINT1 2 PD1/CLKIN 3 ALE 4 PC7 5 JTAG TDO 6 JTAG TDI 7 DEBUG 8 PC4/TERR 9 3.3V VCC 10 USB+(1) 11 VDD(2) 12 GND 13 USB– 14 PC3/TSTAT 15 PC2/VSTBY 16 JTAG TCK 17 SPISEL(2)/PCACLK1/P4.7 18 SPITXD(2)/TCM5/P4.6 19 JTAG TMS 20 60 P1.5/SPIRXD(3)/ADC5 59 P1.4/SPICLK(3)/ADC4 58 P1.3/TXD1(IrDA)(3)/ADC3 57 NC 56 P1.2/RXD1(IrDA)(3)/ADC2 55 NC 54 P1.1/T2X(3)/ADC1 53 NC 52 P1.0/T2(3)/ADC0 51 NC 50 VDD(1) 49 XTAL2 48 XTAL1 47 MCU AD7 46 P3.7/SCL 45 MCU AD6 44 P3.6/SDA 43 MCU AD5 42 P3.5/C1 41 MCU AD4 PA7 21 PA6 22 SPIRXD(2)/TCM4/P4.5 23 PA5 24 SPICLK(2)/TCM3/P4.4 25 PA4 26 TXD1(IrDA)(2)/PCACLK0/P4.3 27 PA3 28 GND 29 RXD1(IrDA)(2)/TCM2/P4.2 30 T2X(2)/TCM1/P4.1 31 PA2 32 T2(2)/TCM0/P4.0 33 PA1 34 PA0 35 MCU AD0 36 MCU AD1 37 MCU AD2 38 MCU AD3 39 P3.4/C0 40 AI09697b Note: Note: 1 2 3 NC = Not Connected The USB+ pin needs a 1.5kΩ pull-up resistor. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1. 12/293 uPSD34xx Table 2. Port Pin Pin descriptions Pin definitions Signal Name 80-Pin 52-Pin In/Out No. No.(1) Function Basic External Bus Multiplexed Address/Data bus A0/D0 Multiplexed Address/Data bus A1/D1 Multiplexed Address/Data bus A2/D2 Multiplexed Address/Data bus A3/D3 Multiplexed Address/Data bus A4/D4 Multiplexed Address/Data bus A5/D5 Multiplexed Address/Data bus A6/D6 Multiplexed Address/Data bus A7/D7 General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin Timer 2 Count input ADC Channel 0 (T2) input (ADC0) Timer 2 Trigger input (T2X) UART1 or IrDA Receive (RxD1) UART or IrDA Transmit (TxD1) SPI Clock Out (SPICLK) SPI Receive (SPIRxD) SPI Transmit (SPITxD) SPI Slave Select (SPISEL) ADC Channel 1 input (ADC1) ADC Channel 2 input (ADC2) ADC Channel 3 input (ADC3) ADC Channel 4 input (ADC4) ADC Channel 5 input (ADC5) ADC Channel 6 input (ADC6) ADC Channel 7 input (ADC7) Alternate 1 Alternate 2 MCUAD0 AD0 36 N/A I/O MCUAD1 AD1 37 N/A I/O MCUAD2 AD2 38 N/A I/O MCUAD3 AD3 39 N/A I/O MCUAD4 AD4 41 N/A I/O MCUAD5 AD5 43 N/A I/O MCUAD6 AD6 45 N/A I/O MCUAD7 AD7 T2 ADC0 T2X ADC1 RxD1 ADC2 TXD1 ADC3 SPICLK ADC4 SPIRxD ADC5 SPITXD ADC6 SPISEL ADC7 47 N/A I/O P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 52 54 56 58 59 60 61 64 34 35 36 37 38 39 40 41 I/O I/O I/O I/O I/O I/O I/O I/O 13/293 Pin descriptions Table 2. Port Pin uPSD34xx Pin definitions Signal Name RxD0 TXD0 EXINT0 TGO 80-Pin 52-Pin In/Out No. No.(1) 75 77 23 24 I/O I/O Function Basic General I/O port pin General I/O port pin Alternate 1 UART0 Receive (RxD0) UART0 Transmit (TxD0) Alternate 2 P3.0 P3.1 P3.2 79 25 I/O Interrupt 0 input General I/O port pin (EXTINT0)/Timer 0 gate control (TG0) Interrupt 1 input General I/O port pin (EXTINT1)/Timer 1 gate control (TG1) General I/O port pin Counter 0 input (C0) General I/O port pin Counter 1 input (C1) General I/O port pin General I/O port pin General I/O port pin I2C Bus serial data (I2CSDA) I2C Bus clock (I2CSCL) Program Counter Timer 2 Count input Array0 PCA0-TCM0 (T2) Timer 2 Trigger input (T2X) UART1 or IrDA Receive (RxD1) UART1 or IrDA Transmit (TxD1) P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 INT1 C0 C1 SDA SCL T2 TCM0 T2X TCM1 RXD1 TCM2 TXD1 PCACLK0 SPICLK TCM3 SPIRXD TCM4 SPITXD SPISEL PCACLK1 2 40 42 44 46 33 31 30 27 25 23 19 18 26 27 28 29 30 22 21 20 18 17 16 15 14 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General I/O port pin PCA0-TCM1 General I/O port pin PCA0-TCM2 General I/O port pin PCACLK0 General I/O port pin Program Counter SPI Clock Out Array1 PCA1-TCM3 (SPICLK) SPI Receive (SPIRxD) SPI Transmit (SPITxD) SPI Slave Select (SPISEL) General I/O port pin PCA1-TCM4 General I/O port pin PCA1-TCM5 General I/O port pin PCACLK1 Reference Voltage input for ADC. Connect AVREF to VCC if the ADC is not used. READ Signal, external bus WRITE Signal, external bus AVREF 70 N/A I RD WR 65 62 N/A N/A O O 14/293 uPSD34xx Table 2. Port Pin Pin descriptions Pin definitions Signal Name 80-Pin 52-Pin In/Out No. No.(1) 63 4 68 48 49 8 35 34 32 28 26 24 22 21 80 78 76 74 73 71 67 66 TMS TCK VSTBY 20 17 16 N/A N/A 44 31 32 5 N/A N/A N/A N/A N/A N/A N/A N/A 52 51 50 49 48 46 43 42 13 12 11 O O I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O Function Basic PSEN Signal, external bus Address Latch signal, external bus Active low reset input Oscillator input pin for system clock Oscillator output pin for system clock I/O to the MCU Debug Unit General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin JTAG pin (TMS) JTAG pin (TCK) General I/O port pin SRAM Standby voltage input (VSTBY) Optional JTAG Status (TSTAT) Optional JTAG Status (TERR) PLD Macrocell output, or PLD input PLD, Macrocell output, or PLD input PLD, Macrocell output, or PLD input All Port B pins support: 1. PLD Macrocell outputs, or 2. PLD inputs, or 3. Latched Address Out (A0-A7 or A8-A15) All Port A pins support: 1. PLD Macrocell outputs, or 2. PLD inputs, or 3. Latched Address Out (A0-A7), or 4. Peripheral I/O Mode Alternate 1 Alternate 2 PSEN ALE RESET_IN XTAL1 XTAL2 DEBUG PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 JTAGTMS JTAGTCK PC2 PC3 PC4 TSTAT TERR 15 9 N/A N/A I/O I/O General I/O port pin General I/O port pin 15/293 Pin descriptions Table 2. Port Pin JTAGTDI JTAGTDO PC7 uPSD34xx Pin definitions Signal Name TDI TDO 80-Pin 52-Pin In/Out No. No.(1) 7 6 5 4 3 2 I O I/O Function Basic JTAG pin (TDI) JTAG pin (TDO) General I/O port pin PLD, Macrocell output, or PLD input 1. 2. 1. 2. PLD I/O Clock input to PLD and APD PLD I/O Chip select ot PSD Module Alternate 1 Alternate 2 PD1 CLKIN 3 1 I/O General I/O port pin PD2 CSI 1 N/A I/O General I/O port pin USB D+ pin; 1.5kΩ pull-up resistor is required. USB D– pin VCC - MCU Module. Connect AVCC to VCC if the ADC is not used. Analog VCC Input VDD - PSD Module VDD - 3.3V for 3V VDD - 5V for 5V VDD - PSD Module VDD - 3.3V for 3V VDD - 5V for 5V USB+ USB– 11 14 7 10 I/O I/O 3.3V-VCC 10 6 AVCC VDD 3.3V or 5V VDD 3.3V or 5V GND GND GND NC NC NC NC 72 12 47 8 50 13 29 69 51 53 55 57 33 9 19 45 N/A N/A N/A N/A Note: 1 N/A = Signal Not Available on 52-pin package. 16/293 uPSD34xx Hardware description 3 Hardware description The uPSD34xx has a modular architecture built from a stacked die process. There are two die, one is designated “MCU Module” in this document, and the other is designated “PSD Module” (see Figure 5 on page 18). In all cases, the MCU Module die operates at 3.3V with 5V tolerant I/O. The PSD Module is either a 3.3V die or a 5V die, depending on the uPSD34xx device as described below. The MCU Module consists of a fast 8032 core, that operates with 4 clocks per instruction cycle, and has many peripheral and system supervisor functions. The PSD Module provides the 8032 with multiple memories (two Flash and one SRAM) for program and data, programmable logic for address decoding and for general-purpose logic, and additional I/O. The MCU Module communicates with the PSD Module through internal address and data busses (AD0 – AD15) and control signals (RD, WR, PSEN, ALE, RESET). There are slightly different I/O characteristics for each module. I/Os for the MCU module are designated as Ports 1, 3, and 4. I/Os for the PSD Module are designated as Ports A, B, C, and D. For all 5V uPSD34xx devices, a 3.3V MCU Module is stacked with a 5V PSD Module. In this case, a 5V uPSD34xx device must be supplied with 3.3VCC for the MCU Module and 5.0VDD for the PSD Module. Ports 3 and 4 of the MCU Module are 3.3V ports with tolerance to 5V devices (they can be directly driven by external 5V devices and they can directly drive external 5V devices while producing a VOH of 2.4V min and VCC max). Ports A, B, C, and D of the PSD Module are true 5V ports. For all 3.3V uPSD34xxV devices, a 3.3V MCU Module is stacked with a 3.3V PSD Module. In this case, a 3.3V uPSD34xx device needs to be supplied with a single 3.3V voltage source at both VCC and VDD. I/O pins on Ports 3 and 4 are 5V tolerant and can be connected to external 5V peripherals devices if desired. Ports A, B, C, and D of the PSD Module are 3.3V ports, which are not tolerant to external 5V devices. Refer to Table 3 for port type and voltage source requirements. 80-pin uPSD34xx devices provide access to 8032 address, data, and control signals on external pins to connect external peripheral and memory devices. 52-pin uPSD34xx devices do not provide access to the 8032 system bus. All non-volatile memory and configuration portions of the uPSD34xx device are programmed through the JTAG interface and no special programming voltage is needed. This same JTAG port is also used for debugging of the 8032 core at runtime providing breakpoint, single-step, display, and trace features. A non-volatile security bit may be programmed to block all access via JTAG interface for security. The security bit is defeated only by erasing the entire device, leaving the device blank and ready to use again. Table 3. Device Type 5V: uPSD34xx 3.3V: uPSD34xxV Port type and voltage source combinations VCC for MCU Module 3.3V 3.3V VDD for PSD Module 5.0V 3.3V Ports 1, 3, and 4 on MCU Module 3.3V (Ports 3 and 4 are 5V tolerant) 3.3V (Ports 3 and 4 are 5V tolerant) Ports A, B, C, and D on PSD Module 5V 3.3V. NOT 5V tolerant 17/293 Hardware description Figure 5. Functional modules Port 3 - UART0, Intr, Timers Port 1 - T imer, ADC, SPI Port 4 - PCA, PWM, UART1 Port 3 I 2C USB pins uPSD34xx MCU Module Port 3 Port 1 T urbo 8032 Core Dual UARTs Interrupt 3T imer / Counters 256 Byte SRAM XT AL Clock Unit 10-bit ADC SPI PCA PWM Counters I2C Unit USB and Transceiver VCC P ins 3.3V Dedicated Memory Interface Prefetch, Branch Cache 8-Bit/16-Bit Die-to-Die Bus Enhanced MCU Interface PSD Page Register 8032 Internal Bus Ext. Bus Reset Input LVD JT AG DEBUG Internal Reset Reset Logic WDT Reset Pin Main Flash Decode PLD Secondary Flash PSD Reset SRAM PSD Module PSD Internal Bus JT ISP AG CPLD - 16 MACROCELLS VDD P ins 3.3V or 5V uPSD34xx Port C JTAG and GPIO Port A,B,C PLD I/O and GPIO Port D GPIO AI10409 18/293 uPSD34xx Memory organization 4 Memory organization The 8032 MCU core views memory on the MCU module as “internal” memory and it views memory on the PSD module as “external” memory, see Figure 6 Internal memory on the MCU Module consists of DATA, IDATA, and SFRs. These standard 8032 memories reside in 384 bytes of SRAM located at a fixed address space starting at address 0x0000. External memory on the PSD Module consists of four types: main Flash (64K, 128K, or 256K bytes), a smaller secondary Flash (32K), SRAM (4K, 8K or 32Kbytes), and a block of PSD Module control registers called csiop (256 bytes). These external memories reside at programmable address ranges, specified using the software tool PSDsoft Express. See the PSD Module section of this document for more details on these memories. External memory is accessed by the 8032 in two separate 64K byte address spaces. One address space is for program memory and the other address space is for data memory. Program memory is accessed using the 8032 signal, PSEN. Data memory is accessed using the 8032 signals, RD and WR. If the 8032 needs to access more than 64K bytes of external program or data memory, it must use paging (or banking) techniques provided by the Page Register in the PSD Module. Note: When referencing program and data memory spaces, it has nothing to do with 8032 internal SRAM areas of DATA, IDATA, and SFR on the MCU Module. Program and data memory spaces only relate to the external memories on the PSD Module. External memory on the PSD Module can overlap the internal SRAM memory on the MCU Module in the same physical address range (starting at 0x0000) without interference because the 8032 core does not assert the RD or WR signals when accessing internal SRAM. Figure 6. uPSD34xx memories Internal SRAM on MCU Module External Memory on PSD Module Fixed Addresses FF Indirect Addressing Main Flash 384 Bytes SRAM 128 Bytes • External memories may be placed at virtually any address using software tool PSDsoft Express. • The SRAM and Flash memories may be placed in 8032 Program Space or Data Space using PSDsoft Express. • Any memory in 8032 Data Space is XDATA. IDATA 80 128 Bytes 7F SFR Direct Addressing 128 Bytes 64KB or 128KB or 256KB Secondary Flash SRAM 4KB or 8KB or 32KB AI10410b DATA 0 Direct or Indirect Addressing 32KB 19/293 Memory organization uPSD34xx 4.1 4.1.1 Internal memory (MCU module, standard 8032 memory: DATA, IDATA, SFR) DATA memory The first 128 bytes of internal SRAM ranging from address 0x0000 to 0x007F are called DATA, which can be accessed using 8032 direct or indirect addressing schemes and are typically used to store variables and stack. Four register banks, each with 8 registers (R0 – R7), occupy addresses 0x0000 to 0x001F. Only one of these four banks may be enabled at a time. The next 16 locations at 0x0020 to 0x002F contain 128 directly addressable bit locations that can be used as software flags. SRAM locations 0x0030 and above may be used for variables and stack. 4.1.2 IDATA memory The next 128 bytes of internal SRAM are named IDATA and range from address 0x0080 to 0x00FF. IDATA can be accessed only through 8032 indirect addressing and is typically used to hold the MCU stack as well as data variables. The stack can reside in both DATA and IDATA memories and reach a size limited only by the available space in the combined 256 bytes of these two memories (since stack accesses are always done using indirect addressing, the boundary between DATA and IDATA does not exist with regard to the stack). 4.1.3 SFR memory Special Function Registers (Table 5 on page 32) occupy a separate physical memory, but they logically overlap the same 128 bytes as IDATA, ranging from address 0x0080 to 0x00FF. SFRs are accessed only using direct addressing. There 86 active registers used for many functions: changing the operating mode of the 8032 MCU core, controlling 8032 peripherals, controlling I/O, and managing interrupt functions. The remaining unused SFRs are reserved and should not be accessed. 16 of the SFRs are both byte- and bit-addressable. Bit-addressable SFRs are those whose address ends in “0” or “8” hex. 4.2 External memory (PSD module: program memory, data memory) The PSD Module has four memories: main Flash, secondary Flash, SRAM, and csiop. See the PSD MODULE section for more detailed information on these memories. Memory mapping in the PSD Module is implemented with the Decode PLD (DPLD) and optionally the Page Register. The user specifies decode equations for individual segments of each of the memories using the software tool PSDsoft Express. This is a very easy pointand-click process allowing total flexibility in mapping memories. Additionally, each of the memories may be placed in various combinations of 8032 program address space or 8032 data address space by using the software tool PSDsoft Express. 20/293 uPSD34xx Memory organization 4.2.1 Program memory External program memory is addressed by the 8032 using its 16-bit Program Counter (PC) and is accessed with the 8032 signal, PSEN. Program memory can be present at any address in program space between 0x0000 and 0xFFFF. After a power-up or reset, the 8032 begins program execution from location 0x0000 where the reset vector is stored, causing a jump to an initialization routine in firmware. At address 0x0003, just following the reset vector are the interrupt service locations. Each interrupt is assigned a fixed interrupt service location in program memory. An interrupt causes the 8032 to jump to that service location, where it commences execution of the service routine. External Interrupt 0 (EXINT0), for example, is assigned to service location 0x0003. If EXINT0 is going to be used, its service routine must begin at location 0x0003. Interrupt service locations are spaced at 8-byte intervals: 0x0003 for EXINT0, 0x000B for Timer 0, 0x0013 for EXINT1, and so forth. If an interrupt service routine is short enough, it can reside entirely within the 8-byte interval. Longer service routines can use a jump instruction to somewhere else in program memory. 4.2.2 Data memory External data is referred to as XDATA and is addressed by the 8032 using Indirect Addressing via its 16-bit Data Pointer Register (DPTR) and is accessed by the 8032 signals, RD and WR. XDATA can be present at any address in data space between 0x0000 and 0xFFFF. Note: The uPSD34xx has dual data pointers (source and destination) making XDATA transfers much more efficient. 4.2.3 Memory placement PSD Module architecture allows the placement of its external memories into different combinations of program memory and data memory spaces. This means the main Flash, the secondary Flash, and the SRAM can be viewed by the 8032 MCU in various combinations of program memory or data memory as defined by PSDsoft Express. As an example of this flexibility, for applications that require a great deal of Flash memory in data space (large lookup tables or extended data recording), the larger main Flash memory can be placed in data space and the smaller secondary Flash memory can be placed in program space. The opposite can be realized for a different application if more Flash memory is needed for code and less Flash memory for data. By default, the SRAM and csiop memories on the PSD Module must always reside in data memory space and they are treated by the 8032 as XDATA. The main Flash and secondary Flash memories may reside in program space, data space, or both. These memory placement choices specified by PSDsoft Express are programmed into non-volatile sections of the uPSD34xx, and are active at power-up and after reset. It is possible to override these initial settings during runtime for In-Application Programming (IAP). Standard 8032 MCU architecture cannot write to its own program memory space to prevent accidental corruption of firmware. However, this becomes an obstacle in typical 8032 systems when a remote update to firmware in Flash memory is required using IAP. The PSD module provides a solution for remote updates by allowing 8032 firmware to temporarily “reclassify” Flash memory to reside in data space during a remote update, then returning 21/293 Memory organization uPSD34xx Flash memory back to program space when finished. See the VM Register (Table 104 on page 197) in the PSD Module section of this document for more details. 22/293 uPSD34xx 8032 MCU core performance enhancements 5 8032 MCU core performance enhancements Before describing performance features of the uPSD34xx, let us first look at standard 8032 architecture. The clock source for the 8032 MCU creates a basic unit of timing called a machine-cycle, which is a period of 12 clocks for standard 8032 MCUs. The instruction set for traditional 8032 MCUs consists of 1, 2, and 3 byte instructions that execute in different combinations of 1, 2, or 4 machine-cycles. For example, there are one-byte instructions that execute in one machine-cycle (12 clocks), one-byte instructions that execute in four machine-cycles (48 clocks), two-byte, two-cycle instructions (24 clocks), and so on. In addition, standard 8032 architecture will fetch two bytes from program memory on almost every machine-cycle, regardless if it needs them or not (dummy fetch). This means for onebyte, one-cycle instructions, the second byte is ignored. These one-byte, one-cycle instructions account for half of the 8032's instructions (126 out of 255 opcodes). There are inefficiencies due to wasted bus cycles and idle bus times that can be eliminated. The uPSD34xx 8032 MCU core offers increased performance in a number of ways, while keeping the exact same instruction set as the standard 8032 (all opcodes, the number of bytes per instruction, and the native number a machine-cycles per instruction are identical to the original 8032). The first way performance is boosted is by reducing the machine-cycle period to just 4 MCU clocks as compared to 12 MCU clocks in a standard 8032. This shortened machine-cycle improves the instruction rate for one- or two-byte, one-cycle instructions by a factor of three (Figure 7 on page 23) compared to standard 8051 architectures, and significantly improves performance of multiple-cycle instruction types. The example in Figure 7 on page 23 shows a continuous execution stream of one- or twobyte, one-cycle instructions. The 5V uPSD34xx will yield 10 MIPS peak performance in this case while operating at 40MHz clock rate. In a typical application however, the effective performance will be lower since programs do not use only one-cycle instructions, but special techniques are implemented in the uPSD34xx to keep the effective MIPS rate as close as possible to the peak MIPS rate at all times. This is accomplished with an instruction PreFetch Queue (PFQ), a Branch Cache (BC), and a 16-bit program memory bus as shown in Figure 8 on page 24. Figure 7. Comparison of uPSD34xx with Standard 8032 Performance 1- or 2-byte, 1-cycle Instructions Instruction A Turbo uPSD34xx Execute Instruction and Pre-Fetch Next Instruction Instruction B Execute Instruction and Pre-Fetch Next Instruction Instruction C Execute Instruction and Pre-Fetch Next Instruction 4 clocks (one machine cycle) one machine cycle one machine cycle MCU Clock 12 clocks (one machine cycle) Instruction A Standard 8032 Fetch Byte for Instruction A Execute Instruction A and Fetch a Second Dummy Byte Dummy Byte is Ignored (wasted bus access) Turbo uPSD34xx executes instructions A, B, and C in the same amount of time that a standard 8032 executes only Instruction A. AI10411 23/293 8032 MCU core performance enhancements Figure 8. Instruction Pre-Fetch Queue and Branch Cache Branch 4 Code Branch Cache (BC) Branch 4 Code Compare uPSD34xx Branch 3 Branch 3 Code Code Branch 2 Branch 2 Code Code Branch 1 Code Branch 1 Code Load on Branch Address Match 16 16 Instruction Byte 16-bit Program Memory on PSD Module 8 Current Branch Address Instruction Byte 8 Instruction Byte 8 Address 4 Bytes of Instruction Wait 16 8032 MCU Address 16 Wait Instruction Pre-Fetch Queue (PFQ) AI10431 5.1 Pre-fetch queue (PFQ) and branch cache (BC) The PFQ is always working to minimize the idle bus time inherent to 8032 MCU architecture, to eliminate wasted memory fetches, and to maximize memory bandwidth to the MCU. The PFQ does this by running asynchronously in relation to the MCU, looking ahead to pre-fetch two bytes (word) of code from program memory during any idle bus periods. Only necessary word will be fetched (no dummy fetches like standard 8032). The PFQ will queue up to four code bytes in advance of execution, which significantly optimizes sequential program performance. However, when program execution becomes non-sequential (program branch), a typical pre-fetch queue will empty itself and reload new code, causing the MCU to stall. The Turbo uPSD34xx diminishes this problem by using a Branch Cache with the PFQ. The BC is a four-way, fully associative cache, meaning that when a program branch occurs, its branch destination address is compared simultaneously with four recent previous branch destinations stored in the BC. Each of the four cache entries contain up to four bytes of code related to a branch. If there is a hit (a match), then all four code bytes of the matching program branch are transferred immediately and simultaneously from the BC to the PFQ, and execution on that branch continues with minimal delay. This greatly reduces the chance that the MCU will stall from an empty PFQ, and improves performance in embedded control systems where it is quite common to branch and loop in relatively small code localities. By default, the PFQ and BC are enabled after power-up or reset. The 8032 can disable the PFQ and BC at runtime if desired by writing to a specific SFR (BUSCON). The memory in the PSD module operates with variable wait states depending on the value specified in the SFR named BUSCON. For example, a 5V uPSD34xx device operating at a 40MHz crystal frequency requires four memory wait states (equal to four MCU clocks). In this example, once the PFQ has one word of code, the wait states become transparent and a full 10 MIPS is achieved when the program stream consists of sequential one- or two-byte, one machine-cycle instructions as shown in Figure 7 on page 23 (transparent because a machine-cycle is four MCU clocks which equals the memory pre-fetch wait time that is also 24/293 uPSD34xx 8032 MCU core performance enhancements four MCU clocks). But it is also important to understand PFQ operation on multi-cycle instructions. 5.2 PFQ example, multi-cycle instructions Let us look at a string of two-byte, two-cycle instructions in Figure 9 on page 25. There are three instructions executed sequentially in this example, instructions A, B, and C. Each of the time divisions in the figure is one machine-cycle of four clocks, and there are six phases to reference in this discussion. Each instruction is pre-fetched into the PFQ in advance of execution by the MCU. Prior to Phase 1, the PFQ has pre-fetched the two instruction bytes (A1 and A2) of Instruction A. During Phase one, both bytes are loaded into the MCU execution unit. Also in Phase 1, the PFQ is pre-fetching Instruction B (bytes B1 and B2) from program memory. In Phase 2, the MCU is processing Instruction A internally while the PFQ is pre-fetching Instruction C. In Phase 3, both bytes of instruction B are loaded into the MCU execution unit and the PFQ begins to pre-fetch bytes for the next instruction. In Phase 4 Instruction B is processed. The uPSD34xx MCU instructions are an exact 1/3 scale of all standard 8032 instructions with regard to number of cycles per instruction. Figure 10 on page 26 shows the equivalent instruction sequence from the example above on a standard 8032 for comparison. 5.3 Aggregate performance The stream of two-byte, two-cycle instructions in Figure 9 on page 25, running on a 40MHz, 5V, uPSD34xx will yield 5 MIPs. And we saw the stream of one- or two-byte, one-cycle instructions in Figure 7 on page 23, on the same MCU yield 10 MIPs. Effective performance will depend on a number of things: the MCU clock frequency; the mixture of instructions types (bytes and cycles) in the application; the amount of time an empty PFQ stalls the MCU (mix of instruction types and misses on Branch Cache); and the operating voltage. A 5V uPSD34xx device operates with four memory wait states, but a 3.3V device operates with five memory wait states yielding 8 MIPS peak compared to 10 MIPs peak for 5V device. The same number of wait states will apply to both program fetches and to data READ/WRITEs unless otherwise specified in the SFR named BUSCON. In general, a 3X aggregate performance increase is expected over any standard 8032 application running at the same clock frequency. Figure 9. PFQ operation on multi-cycle instructions Three 2-byte, 2-cycle Instructions on uPSD34xx Pre-Fetch Inst A Pre-Fetch Inst B and C Pre-Fetch next Inst PFQ Inst A, Byte 1&2 Inst B, Byte 1&2 Inst C, Byte 1&2 Next Inst Continue to Pre-Fetch 4-clock Macine Cycle Phase 1 Phase 2 Process A Phase 3 B1 B2 Phase 4 Process B Phase 5 C1 C2 Phase 6 Process C Next Inst MCU Execution Previous Instruction A1 A2 Instruction A Instruction B Instruction C AI10432 25/293 8032 MCU core performance enhancements Figure 10. uPSD34xx multi-cycle instructions compared to standard 8032 Three 2-byte, 2-cycle Instructions, uPSD34xx vs. Standard 8032 24 Clocks Total (4 clocks per cycle) uPSD34xx A1 A2 Inst A B1 B2 Inst B C1 C2 Inst C uPSD34xx 1 Cycle 72 Clocks (12 clocks per cycle) Std 8032 Byte 1 Byte 2 Process Inst A 1 Cycle AI10412 Byte 1 Byte 2 Process Inst B Byte 1 Byte 2 Process Inst C 26/293 uPSD34xx MCU module description 6 MCU module description This following sections provide a detailed description of the MCU Module system functions and peripherals, including: ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● 8032 MCU Registers Special Function Registers 8032 Addressing Modes uPSD34xx Instruction Set Summary Dual Data Pointers Debug Unit Interrupt System MCU Clock Generation Power Saving Modes Oscillator and External Components I/O Ports MCU Bus Interface Supervisory Functions Standard 8032 Timer/Counters Serial UART Interfaces IrDA Interface I2C Interface SPI Interface Analog to Digital Converter Programmable Counter Array (PCA) USB Interface 27/293 8032 MCU registers uPSD34xx 7 8032 MCU registers The uPSD34xx has the following 8032 MCU core registers, also shown in Figure 11. Figure 11. 8032 MCU registers A B SP PCH PCL PSW R0-R7 DPTR(DPH) AI06636 Accumulator B Register Stack Pointer Program Counter Program Status Word General Purpose Register (Bank0-3) Data Pointer Register DPTR(DPL) 7.1 Stack pointer (SP) The SP is an 8-bit register which holds the current location of the top of the stack. It is incremented before a value is pushed onto the stack, and decremented after a value is popped off the stack. The SP is initialized to 07h after reset. This causes the stack to begin at location 08h (top of stack). To avoid overlapping conflicts, the user must initialize the top of the stack to 20h if all four banks of registers R0 - R7 are used, as well as the top of stack to 30h if all of the 8032 bit memory locations are used. 7.2 Data pointer (DPTR) DPTR is a 16-bit register consisting of two 8-bit registers, DPL and DPH. The DPTR Register is used as a base register to create an address for indirect jumps, table look-up operations, and for external data transfers (XDATA). When not used for addressing, the DPTR Register can be used as a general purpose 16-bit data register. Very frequently, the DPTR Register is used to access XDATA using the External Direct addressing mode. The uPSD34xx has a special set of SFR registers (DPTC, DPTM) to control a secondary DPTR Register to speed memory-to-memory XDATA transfers. Having dual DPTR Registers allows rapid switching between source and destination addresses (see details in Section 11: Dual data pointers on page 47). 7.3 Program counter (PC) The PC is a 16-bit register consisting of two 8-bit registers, PCL and PCH. This counter indicates the address of the next instruction in program memory to be fetched and executed. A reset forces the PC to location 0000h, which is where the reset jump vector is stored. 7.4 Accumulator (ACC) This is an 8-bit general purpose register which holds a source operand and receives the result of arithmetic operations. The ACC Register can also be the source or destination of logic and data movement operations. For MUL and DIV instructions, ACC is combined with 28/293 uPSD34xx 8032 MCU registers the B Register to hold 16-bit operands. The ACC is referred to as “A” in the MCU instruction set. 7.5 B register (B) The B Register is a general purpose 8-bit register for temporary data storage and also used as a 16-bit register when concatenated with the ACC Register for use with MUL and DIV instructions. 7.6 General purpose registers (R0 - R7) There are four banks of eight general purpose 8-bit registers (R0 - R7), but only one bank of eight registers is active at any given time depending on the setting in the PSW word (described next). R0 - R7 are generally used to assist in manipulating values and moving data from one memory location to another. These register banks physically reside in the first 32 locations of 8032 internal DATA SRAM, starting at address 00h. At reset, only the first bank of eight registers is active (addresses 00h to 07h), and the stack begins at address 08h. 7.7 Program status word (PSW) The PSW is an 8-bit register which stores several important bits, or flags, that are set and cleared by many 8032 instructions, reflecting the current state of the MCU core. Figure 12 on page 30 shows the individual flags. 7.7.1 Carry flag (CY) This flag is set when the last arithmetic operation that was executed results in a carry (addition) or borrow (subtraction). It is cleared by all other arithmetic operations. The CY flag is also affected by Shift and Rotate Instructions. 7.7.2 Auxiliary carry flag (AC) This flag is set when the last arithmetic operation that was executed results in a carry into (addition) or borrow from (subtraction) the high-order nibble. It is cleared by all other arithmetic operations. 7.7.3 General purpose flag (F0) This is a bit-addressable, general-purpose flag for use under software control. 7.7.4 Register bank select flags (RS1, RS0) These bits select which bank of eight registers is used during R0 - R7 register accesses (see Table 4) 7.7.5 Overflow flag (OV) The OV flag is set when: an ADD, ADDC, or SUBB instruction causes a sign change; a MUL instruction results in an overflow (result greater than 255); a DIV instruction causes a divide- 29/293 8032 MCU registers uPSD34xx by-zero condition. The OV flag is cleared by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. The CLRV instruction will clear the OV flag at any time. 7.7.6 Parity flag (P) The P flag is set if the sum of the eight bits in the Accumulator is odd, and P is cleared if the sum is even. Table 4. RS1 0 0 1 1 .Register bank select addresses RS0 0 1 0 1 Register Bank 0 1 2 3 8032 Internal DATA Address 00h - 07h 08h - 0Fh 10h - 17h 18h - 1Fh Figure 12. Program status word (PSW) register MSB PSW Carry Flag Auxillary Carry Flag General Purpose Flag Register Bank Select Flags (to select Bank0-3) AI06639 LSB P Reset Value 00h Parity Flag Bit not assigned Overflow Flag CY AC FO RS1 RS0 OV 30/293 uPSD34xx Special function registers (SFR) 8 Special function registers (SFR) A group of registers designated as Special Function Register (SFR) is shown in Table 5 on page 32. SFRs control the operating modes of the MCU core and also control the peripheral interfaces and I/O pins on the MCU Module. The SFRs can be accessed only by using the Direct Addressing method within the address range from 80h to FFh of internal 8032 SRAM. Sixteen addresses in SFR address space are both byte- and bit-addressable. The bitaddressable SFRs are noted in Table 5. 106 of a possible 128 SFR addresses are occupied. The remaining unoccupied SFR addresses (designated as “RESERVED” in Table 5) should not be written. Reading unoccupied locations will return an undefined value. Note: There is a separate set of control registers for the PSD Module, designated as csiop, and they are described in the Section 28: PSD module on page 185. The I/O pins, PLD, and other functions on the PSD Module are NOT controlled by SFRs. SFRs are categorized as follows: ● ● ● ● ● ● ● ● MCU core registers: IP, A, B, PSW, SP, DPTL, DPTH, DPTC, DPTM MCU Module I/O Port registers: P1, P3, P4, P1SFS0, P1SFS1, P3SFS, P4SFS0, P4SFS1 Standard 8032 Timer registers TCON, TMOD, T2CON, TH0, TH1, TH2, TL0, TL1, TL2, RCAP2L, RCAP2H Standard Serial Interfaces (UART) SCON0, SBUF0, SCON1, SBUF1 Power, clock, and bus timing registers PCON, CCON0, CCON1, BUSCON Hardware watchdog timer registers WDKEY, WDRST Interrupt system registers IP, IPA, IE, IEA Prog. Counter Array (PCA) control registers PCACL0, PCACH0, PCACON0, PCASTA, PCACL1, PCACH1, PCACON1, CCON2, CCON3 ● PCA capture/compare and PWM registers CAPCOML0, CAPCOMH0, TCMMODE0, CAPCOML1, CAPCOMH1, TCMMODE2, CAPCOML2, CAPCOMH2, TCMMODE2, CAPCOML3, CAPCOMH3, TCMMODE3, 31/293 Special function registers (SFR) uPSD34xx CAPCOML4, CAPCOMH4, TCMMODE4, CAPCOML5, CAPCOMH5, TCMMODE5, PWMF0, PMWF1 ● ● ● ● ● SPI interface registers SPICLKD, SPISTAT, SPITDR, SPIRDR, SPICON0, SPICON1 I2C interface registers S1SETUP, S1CON, S1STA, S1DAT, S1ADR Analog to Digital Converter registers ACON, ADCPS, ADAT0, ADAT1 IrDA interface register IRDACON USB interface registers Table 5. SFR Addr UADDR, UPAIR, WE0-3, UIF0-3, UCTL, USTA, USEL, UCON, USIZE, UBASEH, UBASEL, USCI, USCV SFR memory map with direct address and reset value Bit Name and Reset Value (hex) 07 00 00 00 00 00 00 00 00 00 00 00 00 00 P1.2 P1.1 P1.0 FF 00 00 00 Table 31 Table 32 Table 27 Table 30 Table 34 Table 35 Section 20.1 7 6 5 4 3 2 1 0 80 81 82 83 84 85 86 87 88(1) 89 8A 8B 8C 8D 8E 8F 90(1) 91 92 93 DPTC DPTM PCON TCON TMOD TL0 TL1 TH0 TH1 P1SFS0 P1SFS1 P1 P3SFS P4SFS0 P4SFS1 P1.7 P1.6 P1.5 – – SMOD0 TF1 GATE AT – SMOD1 TR1 C/T – – – TF0 M1 – – SP DPL DPH RESERVED SP[7:0] DPL[7:0] DPH[7:0] RESERVED – MD1[1:0] RCLK1 IE1 GATE TCLK1 IT1 C/T DPSEL[2:0] MD0[1:0] PD IE0 M1 IDLE IT0 M0 Table 13 Table 14 Table 26 Table 41 Table 42 Section 7.1 Section 7.2 POR TR0 M0 TL0[7:0] TL1[7:0] TH0[7:0] TH1[7:0] P1SFS0[7:0] P1SFS1[7:0] P1.4 P1.3 P3SFS[7:0] P4SFS0[7:0] P4SFS1[7:0] 32/293 Reg. Descr. with Link SFR Name uPSD34xx Table 5. SFR Addr Special function registers (SFR) SFR memory map with direct address and reset value Bit Name and Reset Value (hex) 00 00 – ADS[2:0] REN TB8 RB8 – ADATA[9:8] ADST TI ADSF RI 00 00 00 00 EB 00 00 – INTF2 CLK_SEL[1:0] INTF1 INTF0 00 00 00 – ET1 MATCH MATCH MATCH – EX1 TOGGLE TOGGLE TOGGLE EI2C ET0 – EX0 00 00 00 00 00 00 Table 93 00 55 Table 39 Table 99 7 6 5 4 3 2 1 0 94 95 96 97 98(1) 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8(1) A9 AA AB AC AD AE ADCPS ADAT0 ADAT1 ACON SCON0 SBUF0 – – – – ADCCE ADCPS[2:0] Table 90 Table 91 Table 92 Table 89 Table 47 Section 21 ADATA[7:0] – AINTF SM0 – AINTEN SM1 – ADEN SM2 – SBUF0[7:0] RESERVED RESERVED RESERVED BUSCO N EPFQ EBC WRW1 WRW0 RDW1 RDW0 CW1 CW0 Table 37 RESERVED RESERVED RESERVED RESERVED PCACL0 PCACH0 PCACO N0 PCASTA WDRST IEA IE TCMMO DE0 TCMMO DE1 TCMMO DE2 CAPCO ML0 CAPCO MH0 WDKEY EADC EA EINTF EINTF EINTF ESPI – E_COMP E_COMP E_COMP EPCA ET2 CAP_PE CAP_PE CAP_PE EN_ALL OVF1 EN_PCA INTF5 EOVF1 INTF4 PCACL0[7:0] PCACH0[7:0] PCA_IDL INTF3 – OVF0 Table 93 Table 93 Table 96 Table 98 Table 40 Table 18 Table 17 WDRST[7:0] ES1 ES0 CAP_NE CAP_NE CAP_NE PWM[1:0] PWM[1:0] PWM[1:0] CAPCOML0[7:0] CAPCOMH0[7:0] WDKEY[7:0] Reg. Descr. with Link 33/293 SFR Name Special function registers (SFR) Table 5. SFR Addr uPSD34xx SFR memory map with direct address and reset value Bit Name and Reset Value (hex) 00 P3.2 P3.1 P3.0 FF 00 00 Table 93 CAPCOMH2[7:0] PWMF0[7:0] RESERVED RESERVED IPA IP PADC – PSPI – PPCA PT2 PS1 PS0 – PT1 – PX1 PI2C PT0 – PX0 00 00 Table 20 Table 19 00 00 00 Table 93 00 – TOGGLE TOGGLE TOGGLE P4.2 CLK_SEL[1:0] PWM[1:0] PWM[1:0] PWM[1:0] P4.1 P4.0 00 00 00 00 FF Table 29 Table 99 Table 97 7 6 5 4 3 2 1 0 AF B0(1) B1 B2 B3 B4 B5 B6 B7 B8(1) B9 BA BB BC BD BE BF C0(1) CAPCO ML1 P3 CAPCO MH1 CAPCO ML2 CAPCO MH2 PWMF0 P3.7 P3.6 P3.5 CAPCOML1[7:0] P3.4 P3.3 Table 93 Table 28 CAPCOMH1[7:0] CAPCOML2[7:0] RESERVED PCACL1 PCACH1 PCACO N1 TCMMO DE3 TCMMO DE4 TCMMO DE5 P4 – EINTF EINTF EINTF P4.7 EN_PCA E_COMP E_COMP E_COMP P4.6 EOVF1 CAP_PE CAP_PE CAP_PE P4.5 PCACL1[7:0] PCACH1[7:0] PCA_IDL CAP_NE CAP_NE CAP_NE P4.4 – MATCH MATCH MATCH P4.3 34/293 Reg. Descr. with Link SFR Name uPSD34xx Table 5. SFR Addr Special function registers (SFR) SFR memory map with direct address and reset value Bit Name and Reset Value (hex) 00 00 00 00 00 00 00 TR2 C/T2 CP/RL2 00 Table 43 Table 93 00 00 00 00 CDIV2 OV CDIV1 – CDIV0 P 0F 00 Table 50 Section 7.7 Section 20.1 04 02 00 Table 64 00 FLSB RORIE RB8 SPO TIE TI – RIE RI 00 00 00 00 Table 63 Table 64 Table 48 Section 21 7 6 5 4 3 2 1 0 C1 C2 C3 C4 C5 C6 C7 C8(1) C9 CA CB CC CD CE D0(1) D1 D2 D3 D4 D5 D6 D7 D8(1) D9 CAPCO ML3 CAPCO MH3 CAPCO ML4 CAPCO MH4 CAPCO ML5 CAPCO MH5 PWMF1 T2CON TF2 EXF2 RCLK CAPCOML3[7:0] CAPCOMH3[7:0] CAPCOML4[7:0] CAPCOMH4[7:0] CAPCOML5[7:0] CAPCOMH5[7:0] PWMF1[7:0] TCLK EXEN2 RESERVED RCAP2L RCAP2H TL2 TH2 IRDACO N PSW – CY IRDA_EN AC BIT_PULS F0 RCAP2L[7:0] RCAP2H[7:0] TL2[7:0] TH2[7:0] CDIV4 CDIV3 RS[1:0] RESERVED SPICLK D SPISTAT SPITDR SPIRDR SPICON 0 SPICON 1 SCON1 SBUF1 – – SM0 VSTBY Only on VSTBY CSI > VDD – 0.3V (Notes 1,2) VSS < VIN < VDD 0.45 < VOUT < VDD PLD_TURBO = Off, f = 0MHz (Note 4) –1 –10 –0.1 2 4.49 3.9 VOH VOH1 VSTBY ISTBY IIDLE VDF ISB ILI ILO VDD 0.5 1 0.1 VDD – 0.2 120 ±0.1 ±5 0 400 15 0 0 700 30 0 0 Note 3 1.5 1.5 2.5 3.0 250 1 10 V uA uA V uA uA uA uA/P T uA/P T mA mA mA PLD Only ICC (DC) (Note 4) Operating Supply Current PLD_TURBO = On, f = 0MHz Flash memory SRAM PLD AC Adder ICC (AC) (Note 4) Flash memory AC Adder SRAM AC Adder During Flash memory WRITE/Erase Only Read only, f = 0MHz f = 0MHz mA/M Hz mA/M Hz Note: 1 2 3 4 Internal Power-down mode is active. PLD is in non-Turbo mode, and none of the inputs are switching. Please see Figure 96 on page 259 for the PLD current calculation. IOUT = 0mA 267/293 DC and AC parameters Table 158. PSD module DC characteristics (with 3.3V VDD) Symb. VIH VIL VLKO VOL Parameter High Level Input Voltage Low Level Input Voltage VDD (min) for Flash Erase and Program Output Low Voltage Output High Voltage Except VSTBY On Output High Voltage VSTBY On SRAM Stand-by Voltage SRAM Stand-by Current Idle Current (VSTBY input) SRAM Data Retention Voltage Stand-by Supply Current for Power-down Mode Input Leakage Current Output Leakage Current VDD = 0V VDD > VSTBY Only on VSTBY CSI > VDD – 0.3V (Notes 1,2) VSS < VIN < VDD 0.45 < VIN < VDD PLD_TURBO = Off, f = 0MHz (Note 2) PLD Only ICC (DC) (Note 4) Operating Supply Current PLD_TURBO = On, f = 0MHz Flash memory SRAM PLD AC Adder ICC (AC) (Note 4) Flash memory AC Adder SRAM AC Adder During Flash memory WRITE/Erase Only Read only, f = 0MHz f = 0MHz 200 10 0 0 Note 3 1.0 0.8 –1 –10 –0.1 2 50 ±0.1 ±5 0 IOL = 20uA, VDD = 3.0V IOL = 4mA, VDD = 3.0V IOH = –20uA, VDD = 3.0V IOH = –1mA, VDD = 3.0V IOH1 = 1uA 2.9 2.7 VSTBY – 0.8 2.0 0.5 Test Condition (in addition to those in Table 156 on page 265) 3.0V < VDD < 3.6V 3.0V < VDD < 3.6V Min. 0.7VDD –0.5 1.5 0.01 0.15 2.99 2.8 Typ. uPSD34xx Max. VDD +0.5 0.8 2.2 0.1 0.45 Unit V V V V V V V V VOH VOH1 VSTBY ISTBY IIDLE VDF ISB ILI ILO VDD 1 0.1 VDD – 0.2 100 1 10 V uA uA V uA uA uA uA/P T 400 25 0 0 uA/P T mA mA mA 1.5 1.5 mA/ MHz mA/ MHz Note: 1 2 3 4 Internal PD is active. PLD is in non-Turbo mode, and none of the inputs are switching. Please see Figure 97 on page 260 for the PLD current calculation. IOUT = 0mA 268/293 uPSD34xx Figure 99. External READ cycle (80-pin device only) tLHLL ALE tAVLL RD tLLAX tAZRL tAVDV MCU AD0 - AD7 A0-A7 tAVQV LATCHED MCU A8 - A15 A8-A15 DATA IN tRXDX tRXDZ tRLRH tLLRL DC and AC parameters A0-A7 A8-A15 AI10471 Table 159. External READ cycle AC characteristics (3V or 5V device) 40MHz Oscillator(1) Symbol Parameter Min tLHLL tAVLL tLLAX tLLRL tRLRH tRXIX tRHIZ tAVDX tAZRL tAVQV ALE pulse width Address setup to ALE Address hold after ALE ALE to RD RD pulse width(2) Input data hold after RD Input data float after RD Address to valid data in(2) Address float to RD Address valid to latched address out on Ports A and B –2 35.5 (3V) 28 (5V) 17 13 7.5 7.5 40 2 10.5 70 –2 1.5tCLCL – 2 tCLCL – 9.5 Max Variable Oscillator 1/tCLCL = 3 to 40MHz Min tCLCL – 8 tCLCL – 12 0.5tCLCL – 5 0.5tCLCL – 5 ntCLCL – 10 2 0.5tCLCL – 2 mtCLCL – 5 Max ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1 2 BUSCON Register is configured for 4 PFQCLK. Refer to Table 160 for “n” and “m” values. Table 160. n, m, and x, y values # of PFQCLK in BUSCON Reg. 4 5 READ Cycle n 2 3 m 3 4 x 2 3 WRITE Cycle y 1 2 269/293 DC and AC parameters uPSD34xx # of PFQCLK in BUSCON Reg. 6 7 READ Cycle n 4 5 m 5 6 x 4 5 WRITE Cycle y 3 4 Figure 100. External WRITE cycle (80-pin device only) ALE tLHLL RD tLLWL WR tAVLL tLLAX MCU AD0 - AD7 tAVQV LATCHED MCU A8 - A15 A8-A15 A8-A15 AI10472 tWHLH tWLWH tWHQX tQVWH DATA OUT A0-A7 DATA IN A0-A7 tAVWL Table 161. External WRITE cycle AC characteristics (3V or 5V device) 40MHz Oscillator(1) Symbol Parameter Min tLHLL tAVLL tLLAX tWLWH tLLWL tAVWL tWHLH tQVWH tWHQX ALE pulse width Address Setup to ALE Address hold after ALE WR pulse width(2) ALE to WR Address (A0-A7) valid to WR(3) WR High to ALE High Data setup before WR(y) Data hold after WR 17 13 7.5 40 7.5 32.5 9.5 20 9.5 14.5 35.5 (3V) 28 (5V) 9.5 Max Variable Oscillator 1/tCLCL = 3 to 40MHz Min tCLCL – 8 tCLCL – 12 0.5tCLCL – 5 xtCLCL – 10 0.5tCLCL – 5 1.5tCLCL – 5 0.5tCLCL – 3 ytCLCL – 5 0.5tCLCL – 3 0.5tCLCL + 2 1.5tCLCL – 2 tCLCL – 9.5 0.5tCLCL + 2 Max ns ns ns ns ns ns ns ns ns ns ns Unit tAVQV Address valid to Latched Address out on Ports A and B 270/293 uPSD34xx Note: 1 2 3 BUSCON Register is configured for 4 PFQCLK. Refer to Table 162 on page 271, for “n” and “m” values. Latched address out on Ports A and B to WR is 2ns, minimum. Table 162. External clock drive Parameter(1) 40MHz Oscillator Min tCLCL tCHCX tCLCX tCLCH tCHCL Oscillator period High time Low time Rise time Fall time Max DC and AC parameters Variable Oscillator 1/tCLCL = 3 to 40MHz Min 25 10 10 Max 333 tCLCL – tCLCX tCLCL – tCLCX 10 10 ns ns ns ns ns Unit Symbol Table 163. A/D Analog Specification Symbol Normal IDD AVIN AVREF(2)( 3) Parameter Test Conditions(1) Input = AVREF Min. Typ. 4.0 Max. Unit mA Power-down Analog Input Voltage Analog Reference Voltage GND 40 AVREF 3.6 10 Input = 0 to AVREF (V) fOSC ≤ 32MHz Input = 0 to AVREF (V) fOSC ≤ 32MHz fSAMPLE = 500ksps 50 48 2 8MHz Calibration Time 1 54 52 8 4 16 60 50 54 16 8 ±2 ±2 uA V V bits LSB LSB dB dB MHz µs ms kHz dB Accuracy Resolution INL DNL SNR SNDR ACLK tC tCAL fIN THD Integral Nonlinearity Differential Nonlinearity Signal to Noise Ratio Signal to Noise Distortion Ratio ADC Clock Conversion Time Power-up Time Analog Input Frequency Total Harmonic Distortion Note: 1 2 3 fIN 2kHz, ACLK = 8MHz, AVREF = AVCC = 3.3V AVREF = AVCC in 52-pin package. If the A/D converter is not used, connect AVCC/AVREF to VCC. 271/293 DC and AC parameters Table 164. USB transceiver specification Symbol UVOH UVOL UVIH UVIL RDH RDL IL IOZ VCR tRISE tFALL Parameter High Output Voltage Low Output Voltage High Input Voltage Low Input Voltage Output Impedance (high state) Output Impedance (low state) Input Leakage Current 3-state Output OFF State Current Crossover Point Rise Time Fall Time Test Conditions(1) VDD = 3.3V; IOUT = 2.2mA VDD = 3.3V; IOUT = 2.2mA VDD = 3.6V VDD = 3.6V Note 2 Note 2 VDD = 3.6V VI = VIH or VIL 1.3 4 4 28 28 ±0.1 Min. 3 – 2 Typ. uPSD34xx Max. – 0.25 – 0.8 43 43 ±5 ±10 2 20 20 Unit V V V V Ω Ω µA µA V ns ns Note: 1 2 Temperature range = –45°C to 85°C. This value includes an external resistor of 24Ω ±1%. Figure 101. Input to output disable / enable INPUT tER INPUT TO OUTPUT ENABLE/DISABLE tEA AI02863 Table 165. CPLD combinatorial timing (5V PSD module) Symbol Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay Conditions Min Max PT Aloc +2 Turbo Off + 10 Slew rate(1) –2 Unit tPD(2) 20 ns tEA tER tARP 21 21 21 + 10 + 10 + 10 –2 –2 –2 ns ns ns 272/293 uPSD34xx DC and AC parameters Symbol Parameter CPLD Register Clear or Preset Pulse Width CPLD Array Delay Conditions Min Max PT Aloc Turbo Off + 10 Slew rate(1) Unit tARPW tARD 10 Any macrocell 11 +2 ns ns Note: 1 2 Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) Table 166. CPLD combinatorial timing (3V PSD module) Symbol Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Any macrocell 18 20 +4 Conditions Min Max PT Aloc Turbo Off + 15 Slew rate(1) –6 Unit tPD(2) 35 +4 ns tEA tER tARP tARPW tARD 38 38 35 + 15 + 15 + 15 + 15 –6 –6 –6 ns ns ns ns ns Note: 1 2 Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) Figure 102. Synchronous Clock Mode Timing – PLD tCH tCL CLKIN tS INPUT tH tCO REGISTERED OUTPUT AI02860 273/293 DC and AC parameters uPSD34xx Table 167. CPLD macrocell synchronous clock mode timing (5V PSD module) Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tS tH tCH tCL tCO tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period(2) Clock Input Clock Input Clock Input Any macrocell tCH+tCL 12 Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit 1/(tS+tCO) 1/(tS+tCO– 10) 1/(tCH+tCL) 12 0 6 6 40.0 66.6 83.3 +2 + 10 MHz MHz MHz ns ns ns ns 13 11 +2 –2 ns ns ns Note: 1 2 Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. CLKIN (PD1) tCLCL = tCH + tCL. Table 168. CPLD Macrocell Synchronous Clock Mode Timing (3V PSD Module) Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tS tH tCH tCL tCO tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period(2) Clock Input Clock Input Clock Input Any macrocell tCH+tCL 25 Conditions 1/(tS+tCO) 1/(tS+tCO–10) 1/(tCH+tCL) 20 0 15 10 23 20 +4 –6 Min Max 23.2 30.3 40.0 +4 + 15 PT Turbo Slew Aloc Off rate(1) Unit MHz MHz MHz ns ns ns ns ns ns ns Note: 1 2 Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. CLKIN (PD1) tCLCL = tCH + tCL. 274/293 uPSD34xx Figure 103. Asynchronous RESET / Preset tARPW DC and AC parameters RESET/PRESET INPUT tARP REGISTER OUTPUT AI02864 Figure 104. Asynchronous Clock Mode Timing (Product Term Clock) tCHA tCLA CLOCK tSA tHA INPUT tCOA REGISTERED OUTPUT AI02859 Table 169. CPLD macrocell asynchronous clock mode timing (5V PSD module) Symbo l Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tSA tHA tCHA tCLA tCOA tARDA tMINA Input Setup Time Input Hold Time Clock Input High Time Clock Input Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any macrocell 1/fCNTA 16 Conditions Min Max PT Aloc Turbo Slew Off Rate Unit 1/(tSA+tCOA) 1/(tSA+tCOA– 10) 1/(tCHA+tCLA) 7 8 9 9 38.4 62.5 71.4 +2 + 10 MHz MHz MHz ns ns + 10 + 10 ns ns –2 ns ns ns 21 11 +2 + 10 275/293 DC and AC parameters uPSD34xx Table 170. CPLD macrocell asynchronous clock mode timing (3V PSD module) Symbol Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tSA tHA tCHA tCLA tCOA tARD tMINA Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any macrocell 1/fCNTA 36 Conditions Min Max PT Aloc Turbo Off Slew Rate Unit 1/(tSA+tCOA) 1/(tSA+tCOA– 10) 1/(tCHA+tCLA) 10 12 17 13 21.7 MHz 27.8 MHz 33.3 +4 + 15 MHz ns ns + 15 + 15 ns ns –6 ns ns ns 31 20 +4 + 15 Figure 105. Input macrocell timing (product term clock) t INH PT CLOCK t INL t IS INPUT t IH OUTPUT t INO AI03101 Table 171. Input macrocell timing (5V PSD module) Symbol tIS tIH tINH tINL tINO Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Condition s (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 0 15 9 9 34 +2 + 10 + 10 Max PT Aloc Turbo Off Unit ns ns ns ns ns Note: 1 Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX. 276/293 uPSD34xx Table 172. Input macrocell timing (3V PSD module) Symbol tIS tIH tINH tINL tINO Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 0 25 12 12 43 Max DC and AC parameters PT Aloc Turbo Off Unit ns + 15 ns ns ns +4 + 15 ns Note: 1 Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. Table 173. Program, WRITE and erase times (5V, 3V PSD modules) Symbol Flash Program Flash Bulk Erase(1) (pre-programmed) Parameter Min. Typ. 8.5 3(2) 5 1 2.2 14 100,000 1,000 100 30 150 10 10 Max. Unit s s s s s µs cycles cycles µs ns Flash Bulk Erase (not pre-programmed) tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program / Erase Cycles (per Sector) PLD Program / Erase Cycles tWHWLO tQ7VQV Sector Erase Time-Out DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)(3) Note: 1 2 3 Programmed to all zero before erase. Typical after 100K Write/Erase cycles is 5 seconds. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. 277/293 DC and AC parameters Figure 106. Peripheral I/O READ timing ALE uPSD34xx A /D BUS ADDRESS DATA VALID tAVQV (PA) tSLQV (PA) CSI tRLQV (PA) RD tRHQZ (PA) tDVQV (PA) DATA ON PORT A AI06610 Table 174. Port A peripheral data mode READ timing (5V PSD module) Symbol Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid Data In to Data Out Valid RD to Data High-Z (Note 2) Conditions Min Max Turbo Off + 10 + 10 Unit tAVQV–PA tSLQV–PA tRLQV–PA tDVQV–PA tRHQZ–PA (Note 1) 37 27 32 22 23 ns ns ns ns ns Note: 1 2 Any input used to select Port A Data Peripheral Mode. Data is already stable on Port A. Table 175. Port A peripheral data mode READ timing (3V PSD module) Symbol tAVQV–PA tSLQV–PA tRLQV–PA tDVQV–PA tRHQZ–PA Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid Data In to Data Out Valid RD to Data High-Z (Note 2) Conditions (Note 1) Min Max 50 37 45 38 36 Turbo Off + 15 + 15 Unit ns ns ns ns ns Note: 1 2 Any input used to select Port A Data Peripheral Mode. Data is already stable on Port A. 278/293 uPSD34xx Figure 107. Peripheral I/O WRITE timing ALE DC and AC parameters A / D BUS ADDRESS DATA OUT tWLQV WR (PA) tWHQZ (PA) tDVQV (PA) PORT A DATA OUT AI06611 Table 176. Port A peripheral data mode WRITE timing (5V PSD module) Symbol tWLQV–PA tDVQV–PA tWHQZ–PA Parameter WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state (Note 1) Conditions Min Max 25 22 20 Unit ns ns ns Note: 1 Data stable on Port 0 pins to data on Port A. Table 177. Port A peripheral data mode WRITE timing (3V PSD module) Symbol tWLQV–PA tDVQV–PA tWHQZ–PA Parameter WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state (Note 1) Conditions Min Max 42 38 33 Unit ns ns ns Note: 1 Data stable on Port 0 pins to data on Port A. Table 178. Supervisor reset and LVD Symbol tRST_LO_IN tRST_ACTV tRST_FIL VRST_HYS VRST_THRE SH Parameter Reset Input Duration Generated Reset Duration Reset Input Spike Filter Reset Input Hysteresis LVD Trip Threshold Conditions Min 1(1) Typ Max Unit µs ms fOSC = 40MHz 10(2) 1 µs V 2.8 V VCC = 3.3V VCC = 3.3V 2.4 0.1 2.6 Note: 1 2 25µs minimum to abort a Flash memory program or erase cycle in progress. As fOSC decreases, tRST_ACTV increases. Example: tRST_ACTV = 50ms when fOSC = 8MHz. 279/293 DC and AC parameters Table 179. VSTBYON definitions timing (5V, 3V PSD modules) Symbol tBVBH tBXBL Parameter VSTBY Detection to VSTBYON Output High VSTBY Off Detection to VSTBYON Output Low Conditions (Note 1) (Note 1) Min Typ 20 20 uPSD34xx Max Unit µs µs Note: 1 VSTBYON timing is measured at VCC ramp rate of 2ms. Figure 108. ISC timing t ISCCH TCK t ISCCL t ISCPSU t ISCPH TDI/TMS t ISCPZV t ISCPCO ISC OUTPUTS/TDO t ISCPVZ ISC OUTPUTS/TDO AI02865 Table 180. ISC timing (5V PSD module) Symbol tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH Parameter Clock (TCK, PC1) Frequency (except for PLD) Clock (TCK, PC1) High Time (except for PLD) Clock (TCK, PC1) Low Time (except for PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time ISC Port Hold Up Time Conditions (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 90 90 7 5 23 23 4 Min Max 20 Unit MHz ns ns MHz ns ns ns ns 280/293 uPSD34xx DC and AC parameters Symbol Parameter Conditions Min Max 21 21 21 Unit ns ns ns tISCPCO ISC Port Clock to Output tISCPZV tISCPVZ ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Note: 1 2 For non-PLD Programming, Erase or in ISC By-pass Mode. For Program or Erase PLD only. Table 181. ISC timing (3V PSD module) Symbol tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ Parameter Clock (TCK, PC1) Frequency (except for PLD) Clock (TCK, PC1) High Time (except for PLD) Clock (TCK, PC1) Low Time (except for PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Conditions (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 90 90 12 5 30 30 30 40 40 4 Min Max 16 Unit MHz ns ns MHz ns ns ns ns ns ns ns Note: 1 2 For non-PLD Programming, Erase or in ISC By-pass Mode. For Program or Erase PLD only. Figure 109. MCU module AC measurement I/O waveform VCC – 0.5V 0.2 VCC + 0.9V Test Points 0.2 VCC – 0.1V AI06650 0.45V Note: Note: AC inputs during testing are driven at VCC–0.5V for a logic '1,' and 0.45V for a logic '0.' Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0' 281/293 DC and AC parameters Figure 110. PSD Module AC float I/O waveform VLOAD + 0.1V Test Reference Points VLOAD – 0.1V 0.2 VCC – 0.1V VOL + 0.1V AI06651 uPSD34xx VOH – 0.1V Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH or VOL level occurs IOL and IOH ≥ 20mA Figure 111. External clock cycle Note: Figure 112. PSD module AC measurement I/O waveform 3.0V Test Point 0V AI03103b 1.5V Figure 113. PSD module AC measurement load circuit 2.01 V 195 Ω Device Under Test CL = 30 pF (Including Scope and Jig Capacitance) AI03104b 282/293 uPSD34xx Table 182. I/O pin capacitance Symbol CIN COUT Parameter(1) Input Capacitance (for input pins) Output Capacitance (for input/output pins)(3) Test Condition VIN = 0V VOUT = 0V Typ.(2) 4 8 DC and AC parameters Max. 6 12 Unit pF pF Note: 1 2 3 Sampled only, not 100% tested. Typical values are for TA = 25°C and nominal supply voltages. Maximum for MCU Address and Data lines is 20pF each. 283/293 Package mechanical information uPSD34xx 32 Package mechanical information Figure 114. TQFP52 – 52-lead plastic thin, quad, flat package outline D D1 D2 A2 e Ne E2 E1 E b N 1 Nd L1 A CP c QFP-A A1 α L Note: Drawing is not to scale Table 183. TQFP52 – 52-lead plastic thin, quad, flat package mechanical data Symb A A1 A2 b c D D1 D2 E E1 E2 e L L1 α n Nd Ne CP – Typ (mm) 1.50 0.10 1.40 – – 12.00 10.00 7.80 12.00 10.00 7.80 0.65 – 1.00 – Min (mm) – 0.05 1.30 0.20 0.07 11.80 9.80 7.67 11.80 9.80 7.67 – 0.45 – 0° 52 13 13 – Max (mm) 1.70 0.20 1.50 0.40 0.20 12.20 10.20 7.93 12.20 10.20 7.93 – 0.75 – 7° Typ (inch) 0.059 0.004 0.055 – – 0.472 0.394 0.307 0.472 0.394 0.307 0.026 – 0.039 – Min (inch) – 0.002 0.039 0.008 0.003 0.465 0.386 0.302 0.465 0.386 0.302 – 0.018 – 0° 52 13 13 Max (inch) 0.067 0.008 0.059 0.016 0.008 0.480 0.402 0.312 0.480 0.402 0.312 – 0.030 – 7° 0.10 – – 0.004 284/293 uPSD34xx Package mechanical information Figure 115. TQFP80 – 80-lead plastic thin, quad, flat package outline D D1 D2 A2 e Ne E2 E1 E b N 1 Nd L1 A CP c QFP-A A1 α L Note: Drawing is not to scale Table 184. TQFP80 – 80-lead plastic thin, quad, flat package mechanical data Symb A A1 A2 b c D D1 D2 E E1 E2 e L L1 a n Nd Ne CP 1.00 0° 80 20 20 0.08 7° 14.00 12.00 9.50 14.00 12.00 9.50 0.50 0.45 0.75 0.039 0° 80 20 20 0.003 7° 1.40 0.05 1.35 0.17 0.09 Typ (mm) Min (mm) Max (mm) 1.60 0.15 1.45 0.27 0.20 Typ (inch) Min (inch) Max (inch) 0.063 0.002 0.055 0.053 0.007 0.004 0.551 0.472 0.374 0.551 0.472 0.374 0.020 0.018 0.006 0.057 0.011 0.008 0.030 285/293 Part numbering uPSD34xx 33 Part numbering Table 185. Ordering information scheme Example: UPSD 34 3 4 E V – 40 U 6 T Device Type uPSD = Microcontroller PSD Family 34 = Turbo Plus core SRAM Size 2 = 4Kbytes 3 = 8Kbytes 5 = 32Kbytes Main Flash Memory Size 2 = 64Kbytes 3 = 128Kbytes 4 = 256Kbytes IP Mix E = IP Mix: USB, I2C, SPI, UART (2), IrDA, ADC, Supervisor, PCA Operating Voltage blank: VCC = 3.0 to 3.6V, VDD = 4.5 to 5.5V V: VCC = VDD = 3.0 to 3.6V Revision “-” = Revision A B = Revision B Speed –40 = 40MHz Package T = 52-pin TQFP U = 80-pin TQFP Temperature Range 6 = –40 to 85°C Shipping Option Tape & Reel Packing = T For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. 286/293 uPSD34xx Important notes 34 Important notes The following sections describe the limitations that apply to the uPSD34xx devices and the differences between revision A and B silicon. 34.1 USB interrupts with idle mode Description An interrupt generated by a USB related event does not bring the MCU out of idle mode for processing. Impact On Application Idle mode cannot be used with USB. Workaround Revision A - None identified at this time. Revision B - Corrected in silicon so that a USB interrupt that occurs will bring the MCU out of idle mode. 34.2 USB Reset Interrupt Description When the MCU clock prescaler is set to a value other than fMCU = fOSC (no division), a reset signal on the USB does not cause a USB interrupt to be generated. Impact On Application An MCU clock other than that equal to the frequency of the oscillator cannot be used. Workaround Revision A - The CPUPS field in the CCON0 register must be set to 000b (default after reset). The 3400 USB firmware examples set CCON0 register to 000b. Revision B - Corrected in silicon so that when an MCU clock prescaler is used, a reset signal on the USB does generate an interrupt. 34.3 USB Reset Description A USB reset does not reset the USB SIE's registers. Impact On Application A USB reset does not reset the USB SIE's registers as does a power-on or hardware reset. 287/293 Important notes uPSD34xx Workaround Revision A and B - When a USB reset is detected, the USB SIE's registers must be initialized appropriately by the firmware. The 3400 USB firmware examples clear USB SIE's registers if USB reset is detected. 34.4 Data Toggle Description The data toggle bit is read only. Impact On Application The IN FIFO data toggle bit is controlled exclusively by the USB SIE; therefore, it is not possible to change the state of the data toggle bit by firmware. Workaround Revision A - For cases where the data toggle bit must be reset, such as after a Clear Feature/Stall request, sending the subsequent data on that endpoint twice results in getting the data toggle bit back to the state that it should be. Revision B - A change in silicon was made so that the data toggle bit is reset by disabling and then enabling the respective endpoint's FIFO. 34.5 USB FIFO Accessibility Description The USB FIFO is only accessible by firmware and not by a JTAG debugger. Impact On Application Using a JTAG debugger, it is not possible to view the USB FIFO's contents in a memory dump window. Workaround Revision A and B - None identified at this time. 34.6 Erroneous Resend of Data Packet Description When a data packet is sent the respective IN FIFO busy bit is not automatically cleared by the USB SIE. This can cause a data packet to be erroneously resent to the host in response to an IN PID immediately after the first correct transmission of this data packet. Impact On Application Since the Data Toggle in the retransmitted data packet is toggled from when the data was first sent, the host will treat this packet as valid. If the identified workaround is not 288/293 uPSD34xx Important notes implemented then this extra and unexpected data packet would result in a communication breakdown. Workaround Revision A and B - In the USB ISR, when an INx (x = the endpoint number of the IN FIFO) interrupt is detected, the IN FIFOs respective busy bit should be unconditionally cleared. The uPSD3400 USB firmware implements this workaround. 34.7 IN FIFO Pairing Operation Description When FIFO pairing is used on IN endpoints, an erroneous resend of a data packet may occur. See the "Erroneous Resend of Data Packet" note as it also applies when IN FIFO pairing is used. Impact On Application See the "Erroneous Resend of Data Packet" note as the impact is the same when IN FIFO pairing is used. Workaround Revision A and B - See the "Erroneous Resend of Data Packet" note as the workaround is the same when IN FIFO pairing is used. 34.8 OUT FIFO Pairing Operation Description When data packets are received from the host and FIFO pairing is used, the paired FIFOs may get out of order. Impact On Application The received data packets are read out of order compared to the way they were sent from the host. If the workaround is not implemented, the out of order packets would result in a communication breakdown. Workaround Revision A and B - In the USB ISR, when an OUTx (x = the endpoint number of the OUT FIFO) interrupt is detected, the OUT FIFOs respective busy bit should be unconditionally cleared. The uPSD3400 USB firmware implements this workaround. 34.9 Missing ACK to host retransmission of SETUP packet Description If a host does not properly receive the ACK (due to noise) from the uPSD3400 in response to a SETUP packet, it will resend the SETUP packet but the uPSD3400 will not respond with 289/293 Important notes uPSD34xx an ACK. The host will resend the SETUP packet a number of times and if an ACK is not received from the uPSD3400, the host will issue a USB reset and then enumerate it again. Upon detecting a USB reset, the uPSD3400 firmware will reset and initialize the USB SIE putting the hardware back into the reset/initialized state so that when the next SETUP packet is received, the uPSD3400 will respond with an ACK to the host. Impact On Application If this occurs during enumeration, the impact is minimal as the host will retry the enumeration. If it happens after enumeration, the communication will break down between the host application and the uPSD3400 and will need to be re-established after the uPSD3400 is reset and enumerated again. In extremely noisy environments, the uPSD3400 may not communicate well over USB with the host application. Workaround Revision A and B - None identified at this time. 34.10 MCU JTAG ID Description MCU JTAG ID changed to differentiate revision A from revision B silicon through the JTAG port. The PSD JTAG ID remains the same. Revision A MCU JTAG ID - 0x0451F041 Revision B MCU JTAG ID - 0x1451F041 Impact On Application There will be no impact on the application. The impact will be to JTAG production programming equipment that may need to distinguish between revision A and B MCU silicon if the firmware is different depending on the revision level. 34.11 PORT 1 Not 5-volt IO Tolerant Description The port P1 is shared with the ADC module and as a result Port P1 is not 5V tolerant. Impact On Application 5V devices should not be connected to port P1. Workaround Revision A and B - Peripherals or GPIO that require 5-Volt IO tolerance should be mapped to Port 3 or Port 4. 290/293 uPSD34xx Important notes 34.12 Incorrect Code Execution when Code Banks are Switched Description When a code bank is switched, the PFQ/BC contain values from the previously selected bank and are not automatically flushed and reloaded from the newly selected code bank. Impact On Application. Depending on the contents of the PFQ/BC when the code bank is switched, improper code execution may result. Workaround. The PFQ/BC must be flushed when the code bank is changed. Disabling and re-enabling the PFQ/BC will flush them. The following instructions are an example of how to flush the PFQ/BC: ANL ORL BUSCON,#03Fh BUSCON,#0C0h ;Disable PFQ/BC ;Enable PFQ/BC Bank switching is typically handled by tool vendors in a file called l51_bank.a51. The uPSD tools offered by Keil and Raisonance now include an updated version of l51_bank.a51 for the uPSD products that flushes the PFQ/BC. The most recent banking examples available from ST's website include the updated l51_bank.a51 files. 34.13 9th Received Data Bit Corrupted in UART Modes 2 and 3 Description. If the 9th transmit data bit is written by firmware into TB8 at the same time as a received 9th bit is being written by the hardware into RB8, RB8 is not correctly updated. This applies to both UART0 and UART1. Typically, the 9th data bit is used as a parity bit to check for data transmission errors on a byte by byte basis. Impact on Application. UART Modes 2 and 3 can't be used reliably in full-duplex mode. Workaround. Revision A and B - Some options include: 1. 2. 3. 4. Only use Mode 1 (8 data bits) for full-duplex communication. Use Mode 1 and a packet based communication protocol with a checksum or CRC to detect data transmission errors. Use UART0 in mode 2 or 3 for transmitting data and UART1 in mode 2 or 3 for receiving data. Use some form of handshaking to ensure that data is never transmitted and received simultaneously on a single UART configured in mode 2 or 3. 291/293 Revision history uPSD34xx 35 Revision history Table 186. Document revision history Date 04-Feb-2005 Version 1 First Edition Added one note in Section 1: Summary description on page 9 Added two notes in Section 25: USB interface on page 143 Changed values in Table 175 on page 278 (Turbo Off column) Added Section 34: Important notes on page 287 Changed Table on page 2 to add sales types with 32K SRAM Changed Figure 2 on page 10 Changed Figure 6 on page 19 Corrected Port Pin P1.5 from ADC6 to ADC5 in Table 2 on page 13 Removed duplicate entry for 80-pin no. 11 in Table 2 on page 13 Changed Figure 62 on page 185 Updated Table 101 on page 187 Updated Table 185 on page 286 Pin descriptions, Figure 3 on page 11 and Figure 4 updated with VREF changed to AVREF VREF changed to AVREF throughout document Figure 14 updated, correcting CCON[2:0] Clarification of VCC, VDD, AVCC supply voltages in section Section 30: Maximum rating on page 262 Section 34: Important notes updated with differences between silicon revisions A and B, and new Important Notes added. SPI Master Controller corrected to 10MHz in features on first page Latched address out modified, adding A8-A15 to PB0-PB7, Section Table 2.: Pin definitions UCON register reset value changed from 00h to 08h throughout Reference to USBCE bit corrected to UPLLCESection 14 on page 59 Incorrect references to UART#2 changed to UART#1Section 22.1 on page 112 UADDR register description enhanced, Table 70 on page 155 USB interrupts section text expanded, Section 25.4.3 on page 155 UIFO register table modified, Table 76 on page 159 UCTL register table enhanced, Table 80 on page 163 Note added below Table 81 on page 164 Many modifications made to UCON register description, Table 83 on page 166 An incorrect reference to CAPCOMHn changed to CAPCOMLn Section 27.7 on page 178 Part numbering guide updated with B revision information Section 33 on page 286 Figure 41 on page 115 updated Document reformatted Note added related to non-support of external indirect addressing, inSection 9.6 and in Table 8 on page 44 Revision Details 30-Mar-2005 2 25-Oct-2005 3 11-Jul-2006 4 292/293 uPSD34xx Please Read Carefully: Information in this document is provided solely in connection with ST products. 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