VIPer01
Datasheet
Energy saving off-line high voltage converter
Features
•
•
•
•
•
•
Figure 1. Basic application
schematic
Din
~ AC
Rin
•
Cin
R1
800 V avalanche-rugged power MOSFET allowing ultra wide VAC input range to
be covered
Embedded HV startup and sense-FET
Current mode PWM controller
Drain current limit protection (OCP)
Wide supply voltage range: 4.5 V to 30 V
Self-supply option allows the auxiliary winding or bias components to be
removed
Minimized system input power consumption:
–
Less than 10 mW @ 230 VAC in no-load condition
–
VCC
DRAIN
•
C2
Cs
FB
COMP
DIS
R2
D2
GND
C1
Lout
D1
Product status link
Vout
Cout
•
•
•
•
•
Less than 400 mW @ 230 VAC with 250 mW load
Jittered switching frequency reduces the EMI filter cost:
–
30 kHz ± 7% (type X)
–
60 kHz ± 7% (type L)
–
120 kHz ± 7% (type H)
Embedded E/A with 1.2 V reference
Protections with automatic restart: overload/short-circuit (OLP), line or output
OVP, max. duty cycle counter, VCC clamp
Pulse-skip protection to prevent flux-runaway
Embedded thermal shutdown
Built-in soft-start for improved system reliability
VIPER01
Product label
Applications
•
•
Low power SMPS for home appliances, building and home control, small
industrial, consumers, lighting, motion control
Low power adapters
Description
The device is a high voltage converter smartly integrating an 800 V avalancherugged power MOSFET with PWM current mode control. The power MOSFET with
800 V breakdown voltage allows the extended input voltage range to be applied, as
well as the size of the DRAIN snubber circuit to be reduced. This IC meets the most
stringent energy-saving standards as it has very low consumption and operates in
pulse frequency modulation under light load. The design of flyback, buck and buck
boost converters is supported. The integrated HV startup, sense-FET, error amplifier
and oscillator with jitter allow a complete application to be designed with the
minimum number of components.
DS11423 - Rev 2 - April 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
VIPer01
Pin setting
1
Pin setting
Figure 2. Connection diagram
GND
DRAIN
VCC
DRAIN
DIS
DRAIN
FB
DRAIN
COMP
DRAIN
GIPD091220151050MT
Table 1. Pin description
SSOP10 Name
GND
Ground and MOSFET source. Connection of source of the internal MOSFET and the return of the bias
current of the device. All groundings of bias components must be tied to a trace going to this pin and kept
separate from the pulsed current return.
VCC
Controller supply. An external storage capacitor has to be connected across this pin and GND. The pin,
internally connected to the high voltage current source, provides the VCC capacitor charging current at
startup and during steady-state operation, if the self-supply mode is selected. A small bypass capacitor
(0.1 μF typ.) in parallel, placed as close as possible to the IC, is also recommended, for noise filtering
purpose.
DIS
Disable. If its voltage exceeds the internal threshold VDIS_th (1.2 V typ.) for more than tDEB time (1 ms,
typ.), the PWM is disabled in auto-restart mode. An input overvoltage protection can be built by connecting
a voltage divider between DIS pin and the rectified mains. In case of non-isolated topologies, with the
same principle an output overvoltage protection can be implemented. If the disable function is not required,
DIS pin must be soldered to GND, which excludes the function.
4
FB
Direct feedback. It is the inverting input of the internal transconductance E/A, which is internally
referenced to 1.2 V with respect to GND. In case of non-isolated converter, the output voltage information
is directly fed into the pin through a voltage divider. In case of primary regulation, the FB voltage divider is
connected to the VCC. The E/A is disabled soldering FB to GND.
5
Compensation. It is the output of the internal E/A. A compensation network is placed between this pin and
GND to achieve stability and good dynamic performance of the control loop. In case of secondary
COMP
feedback, the internal E/A must be disabled and the COMP directly driven by the optocoupler to control the
DRAIN peak current setpoint.
6 to 10
MOSFET drain. The internal high voltage current source sinks current from this pin to charge the VCC
capacitor at startup and during steady-state operation. These pins are mechanically connected to the
DRAIN internal metal PAD of the MOSFET in order to facilitate heat dissipation. On the PCB, copper area must be
placed under these pins in order to decrease the total junction-to-ambient thermal resistance thus
facilitating the power dissipation.
1
2
3
DS11423 - Rev 2
Function
page 2/36
VIPer01
Electrical and thermal ratings
2
Electrical and thermal ratings
Table 2. Absolute maximum ratings
Symbol
Parameter (1) (2)
Pin
Min.
Max.
Unit
VDS
6 to 10
Drain-to-source (ground) voltage
800
V
IDRAIN
6 to 10
Pulsed drain current (pulse-width limited by SOA)
2
A
VCC
2
VCC voltage
-0.3
Internally limited
V
ICC
2
VCC internal Zener current (pulsed)
VDIS
3
DIS voltage
-0.3
4.25 (4)
V
VFB
4
FB voltage
-0.3
4.25 (4)
V
-0.3
(4)
V
VCOMP
5
COMP voltage
PTOT
Power dissipation @ Tamb < 50 °C
TJ
Junction temperature operating range
TSTG
Storage temperature
45
(3)
5.25
mA
1 (5)
W
-40
150
°C
-55
150
°C
1. Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.
2. Exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability.
3. Pulse-width limited by maximum power dissipation, PTOT.
4. The AMR value is intended when VCC ≥ 5 V, otherwise the value VCC + 0.3 V has to be considered.
5. When mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 μm thick).
Table 3. Thermal data
Symbol
RTH-JC
RTH-JA
RTH-JC
RTH-JA
Parameter
Thermal resistance junction to case
Max. value
Unit
(1)
(Dissipated power = 1 W)
Thermal resistance junction ambient (1)
(Dissipated power = 1 W)
Thermal resistance junction to case (2)
(Dissipated power = 1 W)
Thermal resistance junction ambient (2)
(Dissipated power = 1 W)
10
°C/W
155
°C/W
5
°C/W
95
°C/W
1. When mounted on a standard, single side FR4 board with minimum copper area.
2. When mounted on a standard, single side FR4 board with 100 mm2 of Cu (35 µm thick).
DS11423 - Rev 2
page 3/36
VIPer01
Electrical and thermal ratings
Figure 3. RthJA/(RthJA@A=100 mm²)
RthJA /(RthJA @A=100 mm²)
GIPD080120161117IDL
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
25
50
75 100 125 150 175 A (mm²)
Table 4. Avalanche characteristics
Symbol
IAR
Parameter
Avalanche current
Test conditions
Pulse-width limited by TJmax
Repetitive and non-repetitive.
Min.
Typ.
Max.
Unit
0.8
A
1
mJ
L = 1 mH
EAS
Single pulse
avalanche energy
(1)
IAS = 0.8 A
VDS = 50 V
RG = 47 Ω
Starting TJ = 25 °C
1. Parameter derived by characterization.
DS11423 - Rev 2
page 4/36
VIPer01
Electrical characteristics
2.1
Electrical characteristics
Tj = -40 to 125 °C, VCC = 9 V (unless otherwise specified).
Table 5. Power section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IDRAIN = 1 mA
VBVDSS
Breakdown
voltage
VCOMP = GND
800
V
TJ = 25 °C
VDS = 400 V
IDSS
Drain-source
leakage current
VCOMP = GND
1
TJ = 25 °C
µA
VDRAIN = max. rating
IOFF
OFF-state drain
current
VCOMP = GND
45
TJ = 25 °C
IDRAIN = 360 mA
RDS(on)
Static drainsource ONresistance
30
TJ = 25 °C
Ω
IDRAIN = 360 mA
60
TJ = 125 °C
Table 6. Supply section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
High voltage start-up current source
VBVDSS_SU
Breakdown
voltage of startup MOSFET
VHV_START
Drain-source
start-up voltage
TJ = 25 °C
800
V
18
V
MΩ
VDRAIN = 400 V
RG
Start-up resistor VDRAIN = 600 V
22
30
38
1.4
1.9
2.4
3.5
4.5
5.5
7.6
8.8
10
VFB > VFB_REF
ICH1
VCC charging
current at
startup
ICH2
VCC charging
current at
startup
ICH3 (1)
DS11423 - Rev 2
Max. VCC
charging
current in selfsupply
VDRAIN = 100 V
VCC = 0 V
VFB > VFB_REF
VDRAIN = 100 V
VCC = 6 V
mA
VFB > VFB_REF
VDRAIN =100 V
VCC = 6 V
page 5/36
VIPer01
Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IC supply and consumptions
VCC
Operating
voltage range
VGND = 0 V
4.5
VCCclamp
Clamp voltage
ICC = Iclamp_max
30
Iclamp max
Clamp
shutdown
current
(2)
tclamp max
Clamp time
before
shutdown
VCCon
VCC start-up
threshold
VCSon
HV current
source turn-on
threshold
VCCoff
UVLO
Iq
Quiescent
current
32.5
30
V
35
V
30
VFB = 1.2 V
VDRAIN = 400 V
VCC falling
VFB = 1.2 V
VDRAIN = 400 V
mA
325
500
675
µs
7.5
8
8.5
V
4
4.25
4.5
V
3.75
4
4.25
V
0.3
0.45
mA
0.75
1.1
0.85
1.25
1
1.5
Not switching VFB > VFB_REF
VDS = 150 V
VCOMP = 1.2 V
FOSC = 30 kHz
Operating
supply current,
switching
ICC
VDS = 150 V
VCOMP = 1.2 V
mA
FOSC = 60 kHz
VDS = 150 V
VCOMP = 1.2 V
FOSC = 120 kHz
1. Current supplied during the main MOSFET OFF time only.
2. Parameter assured by design and characterization.
Table 7. Controller section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
E/A
DS11423 - Rev 2
VFB_REF
Reference voltage
1.175
1.2
1.225
V
VFB_DIS
E/A disable voltage
150
180
210
mV
IFB PULL UP
Pull-up current
0.9
1
1.1
µA
GM
Transconductance
350
500
650
µA/V
ICOMP1
Max. source current
65
100
135
µA
ICOMP2
Max. sink current
70
105
140
µA
VCOMP = 1.5 V
VFB > VFB_REF
VCOMP = 1.5 V
VFB = 0.5 V
VFB = 2 V
page 6/36
VIPer01
Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VCOMP = 1.5 V
RCOMP(DYN)
HCOMP
Dynamic resistance
ΔVCOMP/ΔIDRAIN
VCOMP = 2.7 V
50
58
66
VIPer011*
17
23
29
VIPer012*
9
12
15
VIPer013*
6.4
8.5
10.6
VFB = GND
kΩ
V/A
VCOMPH
Current limitation
threshold
3
V
VCOMPL
PFM threshold
0.8
V
OLP and timing
TJ = 25 °C
VIPer011*
IDLIM
Drain current
limitation
TJ = 25 °C
VIPer012*
TJ = 25 °C
VIPer013*
I2f
Power coefficient
IDLIM_TYP 2x
FOSC_TYP
114
120
126
228
240
252
342
360
378
0.9 ·I2f
I2f
1.1 ·I2f
23
35
47
45
65
85
60
80
100
1.15
1.2
1.25
V
mA
A2·kHz
TJ = 25 °C
VCOMP = VCOMPL
VIPer011*(1)
IDLIM_PFM
TJ = 25 °C
Drain current
VCOMP = VCOMPL
limitation at light load
VIPer012*(1)
mA
TJ = 25 °C
VCOMP = VCOMPL
VIPer013*(1)
VCC = 9 V
VDISth
Disable threshold
voltage
VCOMP = 1 V
VFB = VFB_REF
tDIS
Debounce time
before DIS protection
tripping
0.65
1
1.35
ms
tDIS_RESTART
Restart time after
DIS protection
tripping
325
500
675
ms
tOVL
Overload delay time
45
50
55
ms
90
100
110
180
200
220
360
400
440
VIPer01*X
FOSC = FOSC MIN
tOVL_MAX
Max. overload delay
time
VIPer01*L
FOSC = FOSC MIN
VIPer01*H
DS11423 - Rev 2
ms
page 7/36
VIPer01
Electrical characteristics
Symbol
Parameter
tOVL_MAX
Max. overload delay
time
tSS
Soft-start time
tON_MIN
Minimum turn-on
time
Test conditions
Min.
Typ.
Max.
FOSC = FOSC MIN
Unit
ms
5
8
11
ms
360
ns
s
VCC = 9 V
VCOMP = 1 V
250
VFB = VFB_REF
tRESTART
Restart time after
fault
0.65
1
1.35
27
30
33
54
60
66
108
120
132
13.5
15
16.5
Oscillator
TJ = 25 °C
VIPer01*X
FOSC
Switching frequency
TJ = 25 °C
VIPer01*L
TJ = 25 °C
VIPer01*H
kHz
FOSC_MIN
Minimum switching
frequency
TJ = 25 °C (2)
FD
Modulation depth
(3)
±7 FOSC
%
FM
Modulation
frequency
(3)
260
Hz
DMAX
Max. duty cycle
(3)
70
(3)
150
80
kHz
%
Thermal shutdown
TSD
Thermal shutdown
temperature
160
°C
1. See Section 4.10 Pulse frequency modulation.
2. See Section 4.7 Pulse-skipping.
3. Parameter assured by design and characterization.
DS11423 - Rev 2
page 8/36
VIPer01
Typical electrical characteristics
3
Typical electrical characteristics
Figure 4. IDLIM vs TJ
IDLIM
(norm)
GIPD101220151341IDL
Figure 5. FOSC vs TJ
FOSC
(norm)
GIPD101220151343FOS
IDLIM /(IDLIM @25°C)
FOSC /(FOSC @25°C)
1.05
1.05
1
1
0.95
0.95
0.9
-50 -25
0
25
50
75 100 125 Tj (°C)
0.9
-50 -25
Figure 6. VHV_START vs TJ
VHV_START
(norm)
GIPD101220151344VHV
1
1
0.95
0.975
50
75 100 125 Tj (°C)
Figure 8. Quiescent current Iq vs TJ
Iq
(norm)
GIPD101220151345QIQ
GIPD101220151344VRE
0.95
-50 -25
0
1
1
0.95
0.95
DS11423 - Rev 2
50
75 100 125 Tj (°C)
75 100 125 Tj (°C)
GIPD101220151346ICC
ICC /(ICC @25°C)
1.05
25
50
ICC
(norm)
1.05
0
25
Figure 9. Operating current ICC vs TJ
Iq /(Iq @25°C)
0.9
-50 -25
75 100 125 Tj (°C)
VFB_REF /(VFB_REF @25°C)
1.025
25
50
VFB_REF
(norm)
1.05
0
25
Figure 7. VFB_REF vs TJ
VHV_START /(VHV_START @25°C)
0.9
-50 -25
0
0.9
-50 -25
0
25
50
75 100 125 Tj (°C)
page 9/36
VIPer01
Typical electrical characteristics
Figure 10. ICH1 vs TJ
ICH1
(norm)
1.4
GIPD101220151346I1T
ICH1 /(ICH1 @25°C)
1.3
1.2
Figure 11. ICH1 vs VDRAIN
ICH1
(norm)
1.1
GIPD090320161204I1V
ICH1 /(ICH1 @VDRAIN =100V)
1
1.1
1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.5
-50 -25
0
25
50
75 100 125 Tj (°C)
0.6
0
Figure 12. ICH2 vs TJ
ICH2
(norm)
GIPD101220151347I2T
1.15
ICH2 /(ICH2 @25°C)
100 200 300 400 500 600 700 VDRAIN (V)
Figure 13. ICH2 vs VDRAIN
ICH2
(norm)
1.1
GIPD090320161213I2V
ICH2 /(ICH2 @VDRAIN =100V)
1.1
1
1.05
1
0.9
0.95
0.8
0.9
0.7
0.85
0.8
-50 -25
0
25
50
75 100 125 Tj (°C)
0.6
0
Figure 14. ICH3 vs TJ
ICH3
(norm)
GIPD101220151348I3T
1.15
ICH3 /(ICH3 @25°C)
100 200 300 400 500 600 700 VDRAIN (V)
Figure 15. ICH3 vs VDRAIN
ICH3
(norm)
1.1
GIPD090320161214I3V
ICH3 /(ICH3 @VDRAIN = 100V)
1.1
1
1.05
1
0.9
0.95
0.8
0.9
0.7
0.85
0.8
-50 -25
DS11423 - Rev 2
0
25
50
75 100 125 Tj (°C)
0.6
0
100 200 300 400 500 600 700 VDRAIN (V)
page 10/36
VIPer01
Typical electrical characteristics
Figure 16. GM vs TJ
GM
(norm)
GIPD101220151350GMT
1.15
Figure 17. ICOMP vs TJ
ICOMP
(norm)
GIPD101220151351ICO
ICOMP /(ICOMP @25°C)
GM /(GM @25°C)
1.05
1.1
1.05
1
1
0.95
0.9
0.95
0.85
0.8
-50 -25
0
25
50
75 100 125 Tj (°C)
Figure 18. RDS(on) vs TJ
RDS(on)
(norm)
2.25
GIPD101220151352RDS
RDS(on) /(RDS(on) @25°C)
0.9
-50 -25
0
25
50
75 100 125 Tj (°C)
Figure 19. Static drain-source on-resistance
RDS(on)
(norm)
GIPD101220151353SDS
RDS(on) /(RDS(on) @IDRAIN =360mA)
1.25
2
1.75
1
1.5
Tj=25 °C
0.75
1.25
1
0.5
0.75
0.5
0.25
0.25
0
-50 -25
0
25
50
75 100 125 Tj (°C)
0
0
50 100 150 200 250 300 350 IDRAIN (mA)
Figure 20. Power MOSFET capacitance variation vs VDS @ VGS=0, f=1MHz
DS11423 - Rev 2
page 11/36
VIPer01
Typical electrical characteristics
Figure 21. VBVDSS vs TJ
VBVDSS
(norm)
Figure 22. Output characteristic
IDRAIN
(mA)
1000
GIPD101220151354VBV
VBVDSS /(VBVDSS @25°C)
GIPD101220151355OUT
Tj = -40°C
900
1.1
800
700
1.05
Tj = 25°C
600
500
1
Tj = 125°C
400
300
0.95
200
0.9
-50 -30 -10 10 30 50 70 90 110 130 Tj (°C)
Figure 23. SOA SSOP10 package
IDRAIN
(A)
(o
n)
is
=Ron
=10µs
=100µs
=1ms
DS
10 -2
10 -3
4
6
8
10 12 14 16 18 VDS (V)
EAS
(mJ)
1
GIPD101220151356EAS
0.9
0.8
0.7
0.6
0.5
0.4
10 -4
10 -5
2
Figure 24. Maximum avalnche energy vs TJ
GIPD080120161340SOA
O
lim per
ite atio
d n
by in
m thi
ax s
. R are
a
10 -1
100
0
0
Tj=150°C
TC =25°C
Single pulse
10 -6
10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3
0.3
0.2
VDS (V)
0.1
0
0
20
40
60
80 100 120 140 Tj (°C)
* When mounted on a standard single side FR4 board
with 50 mm2 (0.077 sq in) of Cu (35 μm thick).
DS11423 - Rev 2
page 12/36
VIPer01
General description
4
General description
4.1
Block diagram
Figure 25. Block diagram
VCC
IHV
ICH*
REGULATOR
4V
HV
S ta rt up
HV DIS ABLE
LOGIC
Internal supply bus
COMP
DRAIN
Vz
RG
LIGHT LOAD P FM
+
FB
-
+
+
-
TURN ON
LOGIC
IDLIM re f
E/A
VFB_REF
S
Q
R
LEB
OCP
tOVL filte r
OCP
+
THERMAL
DIODE
(OTP )
J ITTERED
OS CILLATOR
S OFT S TART
MAX DUTY
UVLO VCC
VCC CLAMP
PWM
P ROTECTION
LOGIC
tRES TART
DIS LOGIC
tRES T_DIS
tDIS filte r
OTP
TS D LOGIC
tRES TART
R S ENS E
GND
DIS
GIPD091220151100MT
4.2
Typical power capability
Table 8. Typical power
Vin: 230 VAC
Adapter
(1)
7W
Open frame
8W
Vin: 85-265 VAC
(2)
Adapter
4W
(1)
Open frame (2)
4.5 W
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat-sinking.
4.3
Primary MOSFET
The primary switch is implemented with an avalanche-rugged N-channel MOSFET with minimum breakdown
voltage 800 V, VBVDSS, and maximum on-resistance of 20 Ω, RDS(on). The sense-FET is embedded and it allows
a virtually lossless current sensing. The MOSFET is embedded and it allows the HV voltage start-up operation.
The MOSFET gate driver controls the gate current during both turn-on and turn-off in order to minimize EMI.
Under UVLO conditions the embedded pull-down circuit holds the gate low in order to ensure that the MOSFET
cannot be turned on accidentally.
4.4
High voltage startup
The embedded high voltage startup includes both the 800 V start-up FET, whose gate is biased through the
resistor RG, and the switchable HV current source, delivering the current IHV. The major portion of IHV, (ICH),
charges the capacitor connected to VCC. A minor portion is sunk by the controller block.
DS11423 - Rev 2
page 13/36
VIPer01
High voltage startup
At startup, as the voltage across the DRAIN pin exceeds the VHV_START threshold, the HV current source is
turned on, charging linearly the CS capacitor. At the very beginning of the startup, when Cs is fully discharged, the
charging current is low, ICH1, in order to avoid IC damaging in case VCC is accidentally shorted to GND. As VCC
exceeds 1 V, ICH is increased to ICH2 in order to speed up the charging of CS.
As VCC reaches the start-up threshold VCCon (8 V typ.) the chip starts operating, the primary MOSFET is enabled
to switch, the HV current source is disabled and the device is powered by the energy stored in the CS capacitor.
In steady-state the IC supports two different kind of supplies: self-supply and external supply, as shown in
Figure 27. IC supply modes: self-supply and external supply.
Figure 26. IC supply modes: self-supply and external supply
External supply
Self -supply
VAux
VOUT
VCC
ICH
VCC
ICH
VCC
ICH
CS
CS
from the output
CS
from auxiliary winding
GIPD160720151024MT
In self-supply only one capacitor CS is connected to the VCC and the device is supplied by the energy stored in
CS. After the IC startup, due to its internal consumption, the VCC decays to VCCson (4.25 V, typ.) and the HV
current source is turned on delivering the current ICH3 until VCC is recharged to VCCon. The HV current source is
reactivated when VCC decays to VCCson again. The ICH3 is supplied during the switching OFF time only. In
external supply the HV current source is always kept off by maintaining the VCC above VCSon. This can be
obtained through a transformer auxiliary winding or a connection from the output, the latter in case of non-isolated
topology only. In this case the residual consumption is given by the power dissipated on RG, calculated as follows:
Pd =
V 2 INDC
RG
At the nominal input voltage, 230 VAC, the typical consumption (RG = 30 MΩ) is 3.5 mW and the worst-case
consumption (RG = 22 MΩ) is 4.8 mW.
When the IC is disconnected from the mains, or there is a mains interruption, for some time the converter keeps
on working, powered by the energy stored in the input bulk capacitor. When it is discharged below a critical value,
the converter is no longer able to keep the output voltage regulated. During the power down, when the DRAIN
voltage becomes too low, the HV current source (IHV) remains off and the IC is stopped as soon as the VCC drops
below the UVLO threshold, VCCoff.
DS11423 - Rev 2
page 14/36
VIPer01
Soft-start
Figure 27. Power-ON and power-OFF
VOUT
Regulated output
Output regulation is lost
VCC
Converter startup
HV current source disabled
* dashed line: self supply option
HV current source is
switched off because of a
too low VDRAIN
VCCon
VCSon
UVLO
VCCoff
ICH2
1V
ICH1
HV current source ( ICH3 ) enabled if VCC decays to VCSon
VDRAIN
Power-off
VIN decreases
VIN_DC
Output regulation is lost
VHV_START
Power-on
HV current source enabled
Time
GIPD210420151352MT
4.5
Soft-start
The internal soft-start function of the device progressively increases the cycle-by-cycle current limitation set point
from zero up to IDLIM in 8 steps. The soft-start time, tSS, is internally set at 8 ms. This function is activated at any
attempt of converter startup and at any restart after a fault event. The feature protects the system at the startup
when the output load occurs like a short-circuit and the converter works at its maximum drain current limitation.
Figure 28. Soft startup
Soft start zone with
growing IDLIM value
I DRAIN
t SS
Steady state
IDLIM
time
VCOMP
VCOMPH
time
VOUT
VOUT
time
GIPD280420151230MT
DS11423 - Rev 2
page 15/36
VIPer01
Oscillator
4.6
Oscillator
The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is modulated by
approximately ± 7% kHz FOSC at 260 Hz rate. The purpose of the jittering is to get a spread-spectrum action that
distributes the energy of each harmonic of the switching frequency over a number of frequency bands, having the
same energy on the whole but smaller amplitudes. This helps to reduce the conducted emissions, especially
when measured with the average detection method or, which is the same, to pass the EMI tests with an input filter
of smaller size than that needed in absence of jittering feature. Three options with different switching frequencies,
FOSC, are available: 30 (X type), 60 (L type) and 120 kHz (H type).
4.7
Pulse-skipping
The IC embeds a pulse-skip circuit that operates in the following ways:
•
each time the DRAIN peak current exceeds IDLIM level within tON_MIN, the switching cycle is skipped. The
cycles can be skipped until the minimum switching frequency is reached, FOSC_MIN (15 kHz).
•
each time the DRAIN peak current does not exceed IDLIM within tON_MIN, a switching cycle is restored. The
cycles can be restored until the nominal switching frequency is reached, FOSC (30 or 60 or 120 kHz).
If the converter is operated at FOSC_MIN, the IC is turned off after the time tOVL_MAX (100 ms or 200 ms or 400 ms
typ., depending on FOSC) and then automatically restarted with soft-start phase, after the time tRESTART (1 s, typ.).
The protection is intended to avoid the so called "flux-runaway" condition often present at converter startup and
due to the fact that the primary MOSFET, which is turned on by the internal oscillator, cannot be turned off before
than the minimum on-time.
During the on-time, the inductor is charged by the input voltage and if it cannot be discharged by the same
amount during the off-time, in every switching cycle there is an increase of the average inductor current, that can
reach dangerously high values until the output capacitor is not charged enough to ensure the inductor discharge
rate needed for the volt-second balance. This condition may happen at converter startup, because of the low
output voltage.
In the following Figure 31. Pulse-skipping during startup the effect of pulse-skipping feature on the DRAIN peak
current shape is shown (solid line), compared with the DRAIN peak current shape when pulse-skipping feature is
not implemented (dashed line). Providing more time for cycle-by-cycle inductor discharge when needed, this
feature is effective by keeping low the maximum DRAIN peak current avoiding the flux-runaway condition.
Figure 29. Pulse-skipping during startup
VOUT
VOUT_nom
time
IDRAIN
Without pulse skipping
With pulse skipping
IDLIM
time
Skipped cycles
GIPD280420151222MT
DS11423 - Rev 2
page 16/36
VIPer01
Direct feedback
4.8
Direct feedback
The IC embeds a transconductance type error amplifier (E/A) whose inverting input, ground reference and output
are FB and COMP, respectively. The internal reference voltage of the E/A is VFB_REF (1.2 V typical value referred
to GND). In non-isolated topologies this tightly regulates positive output voltages through a simple voltage divider
applied to the output voltage terminal, FB and GND.
The E/A output is scaled down and fed into the PWM comparator, where it is compared to the voltage across the
sense resistor in series to the sense-FET, thus setting the cycle-by-cycle drain current limitation.
An R-C network connected on the output of the E/A (COMP) is usually used to stabilize the overall control loop.
The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is accidentally left
floating.
The E/A is disabled if the FB voltage is lower than VFB_DIS (200 mV, typ.).
4.9
Secondary feedback
When a secondary feedback is required, the internal E/A has to be disabled shorting FB to GND (VFB < VFB_DIS).
With this setting, COMP is internally connected to a pre-regulated voltage through the pull-up resistor RCOMP(DYN)
and the voltage across COMP is set by the current sunk.
This allows the output voltage value to be set through an external error amplifier (TL431 or similar) placed on the
secondary side, whose error signal is used to set the DRAIN peak current setpoint corresponding to the output
power demand. If isolation is required, the error signal must be transferred through an optocoupler, with the
phototransistor collector connected across COMP and GND.
4.10
Pulse frequency modulation
If the output load is decreased, the feedback loop reacts lowering the VCOMP voltage, which reduces the DRAIN
peak current setpoint, down to the minimum value of IDLIM_PFM when the VCOMPL threshold is reached.
If the load is furtherly decreased, the DRAIN peak current value is maintained at IDLIM_PFM and some PWM
cycles are skipped. This kind of operation is referred to as “pulse frequency modulation” (PFM), the number of the
skipped cycles depends on the balance between the output power demand and the power transferred from the
input. The result is an equivalent switching frequency which can go down to some hundreds Hz, thus reducing all
the frequency-related losses.
This kind of operation, together with the extremely low IC quiescent current, allows very low input power
consumption in no-load and light load, while the low DRAIN peak current value, IDLIM_PFM, prevents any audible
noise which could arise from low switching frequency values. When the load is increased, VCOMP increases and
PFM is exited. VCOMP reaches its maximum at VCOMPH and corresponding to that value, the DRAIN current
limitation (IDLIM) is reached.
4.11
Overload protection
To manage the overload condition, the IC embeds the following main blocks: the OCP comparator to turn off the
power MOSFET when the drain current reaches its limit (IDLIM) , the up and down OCP counter to define the turnoff delay time in case of continuous overload (tOVL = 50 ms typ.) and the timer to define the restart time after
protection tripping (tRESTART = 1 s typ.).
In case of short-circuit or overload, the control level on the inverting input of the PWM comparator is greater than
the reference level fed into the inverting input of the OCP comparator. As a result, the cycle-by-cycle turn-off of
the power switch is triggered by the OCP comparator instead of PWM comparator. Every cycle where this
condition is met, the OCP counter is incremented and if the fault condition lasts longer than tOVL (corresponding
to the counter end-of-count), the protection is tripped, the PWM is disabled for tRESTART, then it resumes
switching with soft-start and, if the fault is still present, it is disabled again after tOVL. The OLP management
prevents IC from operating indefinitely at IDLIM and the low repetition rate of the restart attempts of the converter
avoids IC overheating in case of repeated fault events.
After the fault removal, the IC resumes working normally. If the fault is removed earlier than the protection tripping
(before tOVL), the tOVL-counter is decremented on a cycle-by-cycle basis down to zero and the protection is not
tripped. If the fault is removed during tRESTART, the IC waits for the tRESTART period has elapsed before resuming
switching.
DS11423 - Rev 2
page 17/36
VIPer01
Max. duty cycle counter protection
In fault condition the VCC ranges between VCSon and VCCon levels, due to the periodical activation of the HV
current source recharging the VCC capacitor.
Figure 30. Short-circuit condition
VCC
Overload removed
Overload occurs
VCCon
VCSon
IDRAIN
time
IDLIM
tOVL
tOVL
time
tRESTART
tRESTART
tSS
tSS
GIPD270420151208MT
4.12
Max. duty cycle counter protection
The IC embeds a max. duty cycle counter, which disables the PWM if the MOSFET is turned off by max. duty
cycle (70% min., 80% max.) for ten consecutive switching cycles. After protection tripping, the PWM is stopped for
tRESTART and then activated again with soft-start phase until the fault condition is removed.
In some cases (i.e. breaking of the loop) even if VCOMP is saturated high, the OLP cannot be triggered because at
every switching cycle the PWM is turned off by maximum duty cycle before than DRAIN peak current reaches the
IDLIM setpoint. As a result, the output voltage VOUT can increase without control by keeping a value much higher
than the nominal one with the risk for the output capacitor, the output diode and the IC itself. The max. duty cycle
counter protection avoids this kind of failures.
4.13
VCC clamp protection
This protection can occur when the IC is supplied by auxiliary winding or diode from the output voltage, when an
output overvoltage produces an increase of VCC.
If VCC reaches the clamp level VCCclamp (30 V, min. referred to GND) the current injected into the pin is monitored
and if it exceeds the internal threshold Iclamp_max (30 mA, typ.) for more than tclamp_max (500 µs, typ.), the PWM is
disabled for tRESTART (1 s, typ.) and then activated again in soft-start phase. The protection is disabled during the
soft-start time.
4.14
Disable function
When the voltage across the pin is externally pulled above VDIS_th (1.2 V typ.) for more than tDEB (for instance by
a voltage divider connected to some higher voltages), the PWM is disabled. If the voltage divider on the DIS pin is
connected to the rectified mains, as shown in Figure 33. Connection for input overvoltage protection (isolated or
non-isolated topologies), an input overvoltage protection can be built.
DS11423 - Rev 2
page 18/36
VIPer01
Disable function
Figure 31. Connection for input overvoltage protection (isolated or non-isolated topologies)
~ AC
Din
T
VCC
DRAIN
RH
C BULK
Cs
FB
C ONTR OL
COMP
RL
DIS
GND
C1
GND
GIPD091120151408MT
In case of non-isolated topologies, by following the same principle an output overvoltage protection can be built,
as shown in Figure 34. Connection for output overvoltage protection (non-isolated topologies).
Figure 32. Connection for output overvoltage protection (non-isolated topologies)
Dout
Vout
T
C out
GND
VCC
FB
Cs
DRAIN
R f b1
RH
R f b2
RL
C ONTR OL
COMP
C1
DIS
GND
GIPD110120161010MT
DS11423 - Rev 2
page 19/36
VIPer01
Thermal shutdown
If VOVP is the desired input/output overvoltage threshold, the resistors RH and RL of the voltage divider are to be
selected according to the following formula:
RH = ( VOVP /VDIS_th - 1) × RL
The power dissipation associated to the DIS network is:
(VIN − VDIS)2 VDIS 2
PDIS(VIN) = PRH + PRL =
+
RH
RL
in case of connection for the input overvoltage detection and
(VOUT − VDIS)2 VDIS 2
PDIS(VOUT) = PRH + PRL =
+
RH
RL
in case of connection for the output overvoltage detection.
4.15
Thermal shutdown
If the junction temperature becomes higher than the internal threshold TSD (160 °C, typ.), the PWM is disabled.
After tRESTART time, a single switching cycle is performed, during which the temperature sensor embedded in the
power MOSFET section is checked. If a junction temperature above TSD is still measured, the PWM is maintained
disabled for tRESTART time, otherwise it resumes switching with soft-start phase.
During tRESTART VCC is maintained between VCSon and VCCon levels by the HV current source periodical
activation. Such a behavior is summarized in below figure:
Figure 33. Thermal shutdown timing diagram
VCC
TJ > TS D
TJ < TS D
VCCon
VCS on
IDRAIN
time
IDLIM
IP EAK
tRES TART
time
tRES TART
tS S
GIPD270420151404MT
DS11423 - Rev 2
page 20/36
VIPer01
Application information
5
Application information
5.1
Typical schematics
Figure 34. Flyback converter (non-isolated)
Optional if Vout >= 5 V
Daux
~ AC
Din
Rin
Dout
Vout
T
Ccl
Cout
Cin
Rcl
GND
DRAIN
VCC
Cs
CONTROL
FB
COMP
R1
DIS
GND
C1
R2
GIPD091120151428MT
Figure 35. Flyback converter with line OVP (non-isolated)
Optional if Vout > = 5 V
Da ux
~ AC
Din
Dout
Rin
Vout
T1
Ccl
Cout
Cin
Rcl
R3
GND
DRAIN
VCC
Cs
FB
CONTROL
COMP
R1
DIS
GND
R4
C1
R2
GIPD091220151436MT
DS11423 - Rev 2
page 21/36
VIPer01
Typical schematics
Figure 36. Flyback converter (isolated)
~ AC
Din
Rin
T
Cin
Dout
Vout
Ccl
Cout
Rcl
GND
Da ux
R3
R1
OP TO
optiona l
VCC
DRAIN
R4
Cs
FB
C2
CONTROL
COMP
GND
DIS
OP TO
R2
C1
GIPD091220151444MT
Figure 37. Primary side regulation isolated flyback converter
~ AC
Din
T
Rin
Cin
Dout
Vout
Cout
Ccl
Rcl
GND
Da ux
VCC
R1
Cs
FB
DRAIN
CONTROL
COMP
DIS
GND
R2
C1
GIPD091220151429MT
DS11423 - Rev 2
page 22/36
VIPer01
Typical schematics
Figure 38. Buck converter (positive output)
Din
~ AC
Rin
Cin
Optional if Vout > = 5 V
Da ux
VCC
DRAIN
R1
FB
D
CONTROL
COMP
Cs
DIS
C2
GND
R2
C1
Lout
Vout
Dout
Cout
GIPD091220151457MT
Figure 39. Buck-boost converter (negative output)
~ AC
Din
Rin
Cin
Optional if IVout > = 5 V
Da ux
VCC
DRAIN
R1
Cs
FB
CONTROL
COMP
C2
DIS
GND
R2
D
C1
Dout
Lout
Vout (< 0 V)
Cout
GIPD091220151501MT
DS11423 - Rev 2
page 23/36
VIPer01
Energy saving performance
5.2
Energy saving performance
The device allows designing applications to be compliant with the most stringent energy saving regulations. In
order to show the typical performance is achievable, the active mode average efficiency and the efficiency at 10%
of the rated output power of a single output flyback converter have been measured and are reported in
Table 9. Power supply efficiency, VOUT = 5 V. In addition, no-load and light load consumptions are shown in
Figure 45. PIN versus VIN in no-load, VOUT = 5 V and Figure 46. PIN versus VIN in light load, VOUT = 5 V.
Table 9. Power supply efficiency, VOUT = 5 V
VIN
10 % output load efficiency
[%]
Active mode average
efficiency [%]
Pin @ no-load [mW]
115 VAC
72.2
74.6
4.5
230 VAC
65.1
75.1
8.6
Figure 40. PIN versus VIN in no-load, VOUT = 5 V
PIN
(mW)
GIPD101220151535PVNL
12
10
8
6
4
2
0
85 110 135 160 185 210 235 260
VIN (VAC )
Figure 41. PIN versus VIN in light load, VOUT = 5 V
PIN
(mW)
400
GIPD101220151402PVL
POUT = 250mW
350
300
250
200
150
100
POUT = 50mW
50
POUT = 25mW
0
85 110 135 160 185 210 235 260
DS11423 - Rev 2
VIN (VAC )
page 24/36
VIPer01
Layout guidelines and design recommendations
5.3
Layout guidelines and design recommendations
A proper printed circuit board layout ensures the correct operation of any switch-mode converter and this is true
for the VIPer as well. The main reasons to have a proper PCB layout are:
•
Providing clean signals to the IC, ensuring good immunity against external and switching noises.
•
Reducing the electromagnetic interferences, both radiated and conducted, to pass the EMC tests more
easily.
If the VIPer is used to design a SMPS, the following basic rules should be considered:
•
Separating signal from power tracks. Generally, traces carrying signal currents should run far from others
carrying pulsed currents or with fast swinging voltages. Signal ground traces should be connected to the IC
signal ground, GND, using a single "star point", placed close to the IC. Power ground traces should be
connected to the IC power ground, GND. The compensation network should be connected to the COMP,
maintaining the trace to GND as short as possible. In case of two-layer PCB, it is a good practice to route
signal traces on one PCB side and power traces on the other side.
•
Filtering sensitive pins. Some crucial points of the circuit need or may need filtering. A small highfrequency bypass capacitor to GND might be useful to get a clean bias voltage for the signal part of the IC
and protect the IC itself during EFT/ESD tests. A low ESL ceramic capacitor (a few hundreds pF up to 0.1
μF) should be connected across VCC and GND, placed as close as possible to the IC. With flyback
topologies, when the auxiliary winding is used, it is suggested to connect the VCC capacitor on the auxiliary
return and then to the main GND using a single track.
•
Keeping power loops as confined as possible. The area circumscribed by current loops where high
pulsed current flow should be minimized to reduce its parasitic self-inductance and the radiated
electromagnetic field. As a consequence, the electromagnetic interferences produced by the power supply
during the switching are highly reduced. In a flyback converter the most critical loops are: the one including
the input bulk capacitor, the power switch, the power transformer, the one including the snubber, the one
including the secondary winding, the output rectifier and the output capacitor. In a buck converter the most
critical loop is the one including the input bulk capacitor, the power switch, the power inductor, the output
capacitor and the free-wheeling diode.
•
Reducing line lengths. Any wire acts as an antenna. With the very short rise times exhibited by EFT
pulses, any antenna can receive high voltage spikes. By reducing line lengths, the level of received radiated
energy is reduced, and the resulting spikes from electrostatic discharges are lower. This also keeps both
resistive and inductive effects to a minimum. In particular, all traces carrying high currents, especially if
pulsed (tracks of the power loops) should be as short and wide as possible.
•
Optimizing track routing. As levels of pickup from static discharges are likely greater near the edges of the
board, it is wise to keep any sensitive lines away from these areas. Input and output lines often need to
reach the PCB edge at some stage, but they can be routed away from the edge as soon as possible where
applicable. Since vias are to be considered inductive elements, it is recommended to minimize their number
in the signal path and avoid them in the power path.
•
Improving thermal dissipation. An adequate copper area has to be provided under the DRAIN pins as
heatsink, while it is not recommended to place large copper areas on the GND.
DS11423 - Rev 2
page 25/36
VIPer01
Layout guidelines and design recommendations
Figure 42. Recommended routing for flyback converter
~ AC
T
Din
Dout
Rin
Cin
Vout
Ccl
Cout
Rcl
Da ux
GND
Cs
OP TO
VCC
FB
R1
DRAIN
CONTROL
COMP
DIS
GND
C1
OP TO
R2
GIPD091220151526MT
Figure 43. Recommended routing for buck converter
~ AC
Din
Rin
Cin
Da ux
VCC
DRAIN
R1
Cs
FB
CONTROL
C2
D
COMP
DIS
R2
GND
C1
Lout
Dout
Vout
Cout
GIPD091220151532MT
DS11423 - Rev 2
page 26/36
VIPer01
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
DS11423 - Rev 2
page 27/36
VIPer01
SSOP10 package information
6.1
SSOP10 package information
Figure 44. SSOP10 package outline
8140761_2
DS11423 - Rev 2
page 28/36
VIPer01
SSOP10 package information
Table 10. SSOP10 mechanical data
mm
Dim.
Min.
Typ.
A
Max.
1.75
A1
0.10
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
4.80
4.90
5
E
5.80
6
6.20
E1
3.80
3.90
4
e
0.25
1
h
0.25
0.50
L
0.40
0.90
K
0°
8°
Figure 45. SSOP10 recommended footprint
8140761_rev2_footprint
DS11423 - Rev 2
page 29/36
VIPer01
Order code
7
Order code
Table 11. Order code
Order code
DS11423 - Rev 2
IDLIM (OCP)
VIPer011XS(TR)
120 mA
VIPer012XS(TR)
240 mA
VIPer013XS(TR)
360 mA
VIPer011LS(TR)
120 mA
VIPer012LS(TR)
240 mA
VIPer013LS(TR)
360 mA
VIPer012HS(TR)
240 mA
VIPer013HS(TR)
360 mA
FOSC ± jitter
Package
30 kHz ± 7%
60 kHz ± 7%
SSOP10 tube (tape and reel)
120 kHz ± 7%
page 30/36
VIPer01
Revision history
Table 12. Document revision history
Date
DS11423 - Rev 2
Revision
Changes
09-Mar-2016 1
Initial release
16-Apr-2020 2
Updated cover image, updated Table 2, Table 3, Table 5, Table 7, add fig 20 Power MOSFET
capacitance variation vs VDS @ VGS=0, f=1MHz.
page 31/36
VIPer01
Contents
Contents
1
Pin setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical and thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5
6
4.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Typical power capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Primary MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
High voltage startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5
Soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7
Pulse-skipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.8
Direct feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9
Secondary feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10
Pulse frequency modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.11
Overload protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.12
Max. duty cycle counter protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13
VCC clamp protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14
Disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.15
Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.1
Typical schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2
Energy saving performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3
Layout guidelines and design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.1
7
SSOP10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
DS11423 - Rev 2
page 32/36
VIPer01
Contents
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
DS11423 - Rev 2
page 33/36
VIPer01
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Pin description. . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . .
Thermal data. . . . . . . . . . . . . . . . .
Avalanche characteristics . . . . . . . .
Power section . . . . . . . . . . . . . . . .
Supply section . . . . . . . . . . . . . . . .
Controller section. . . . . . . . . . . . . .
Typical power . . . . . . . . . . . . . . . .
Power supply efficiency, VOUT = 5 V .
SSOP10 mechanical data . . . . . . . .
Order code . . . . . . . . . . . . . . . . . .
Document revision history . . . . . . . .
DS11423 - Rev 2
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. 2
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. 3
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. 5
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13
24
29
30
31
page 34/36
VIPer01
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
DS11423 - Rev 2
Basic application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RthJA/(RthJA@A=100 mm²) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDLIM vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FOSC vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VHV_START vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VFB_REF vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quiescent current Iq vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating current ICC vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICH1 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICH1 vs VDRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICH2 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICH2 vs VDRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICH3 vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICH3 vs VDRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GM vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICOMP vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RDS(on) vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static drain-source on-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power MOSFET capacitance variation vs VDS @ VGS=0, f=1MHz . . . . . . . . . .
VBVDSS vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOA SSOP10 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum avalnche energy vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IC supply modes: self-supply and external supply . . . . . . . . . . . . . . . . . . . . . .
Power-ON and power-OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse-skipping during startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short-circuit condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection for input overvoltage protection (isolated or non-isolated topologies).
Connection for output overvoltage protection (non-isolated topologies) . . . . . . .
Thermal shutdown timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flyback converter (non-isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flyback converter with line OVP (non-isolated) . . . . . . . . . . . . . . . . . . . . . . . .
Flyback converter (isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary side regulation isolated flyback converter . . . . . . . . . . . . . . . . . . . . . .
Buck converter (positive output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck-boost converter (negative output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN versus VIN in no-load, VOUT = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN versus VIN in light load, VOUT = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended routing for flyback converter . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended routing for buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSOP10 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSOP10 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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