VIPER100A

VIPer100/SP VIPer100A/ASP SMPS PRIMARY I.C. Table 1. Figure 2. General Features Type VDSS In RDS(on) VIPer100/SP 620V 3A 2.5 Ω VIPer100A/ASP 700V 3A 2.8 Ω ■ ADJUSTABLE SWITCHING FREQUENCY UP TO 200 kHz ■ CURRENT MODE CONTROL ■ SOFT START AND SHUTDOWN CONTROL ■ AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET “BLUE ANGEL” NORM (1.2KΩ and C t ≥ 15nF if FSW ≤ 40KHz VDD Rt OSC 550 F = ---2.3 -------- ⋅ ⎛ 1 – ------------------- ⎞ SW R C ⎝ R – 150 ⎠ CLK t t ~360Ω t Ct FC00050 Ct c u d Forbidden area 880 Ct(nF) = 22nF Fsw(kHz) e t le 15nF ) s ( ct o r P e 1,000 40kHz Fsw Oscillator frequency vs Rt and Ct FC00030 Ct = 1.5 nF 500 Frequency (kHz) s b O t e l o o r P o s b O - Forbidden area du ) s t( Ct = 2.7 nF 300 Ct = 4.7 nF 200 Ct = 10 nF 100 50 30 1 2 3 5 10 20 30 50 Rt (kΩ) 9/24 VIPer100/SP - VIPer100A/ASP Figure 13. Error Amplifier frequency Response FC00200 60 RCOMP = +∞ Voltage Gain (dB) RCOMP = 270k 40 RCOMP = 82k RCOMP = 27k 20 RCOMP = 12k 0 (20) 0.001 0.01 0.1 1 10 Frequency (kHz) Figure 14. Error Amplifier Phase Response 200 t e l o s b O 10/24 Phase (°) o r P e du e t le o s b O - ct 150 100 (s) 100 1,000 c u d o r P FC00210 RCOMP = +∞ RCOMP = 270k RCOMP = 82k RCOMP = 27k RCOMP = 12k 50 0 (50) 0.001 0.01 0.1 1 10 Frequency (kHz) 100 1,000 ) s t( VIPer100/SP - VIPer100A/ASP Figure 15. Avalanche Test Circuit L1 1mH 2 VDD 1 3 DRAIN OSC 13V BT1 0 to 20V + COMP BT2 12V C1 47uF 16V Q1 2 x STHV102FI in parallel R1 47 SOURCE 5 4 GENERATOR INPUT 500us PULSE U1 VIPer100 R2 1k R3 100 c u d ) s t( FC00195 e t le ) s ( ct o r P o s b O - u d o r P e t e l o s b O 11/24 VIPer100/SP - VIPer100A/ASP Figure 16. Offline Power Supply With Auxiliary Supply Feedback F1 BR1 TR2 C1 TR1 D2 AC IN L2 +Vcc D1 R9 C2 C7 C9 R1 C3 GND D3 C10 R7 C4 R2 VDD DRAIN - U1 OSC VIPer100 + 13V COMP SOURCE C5 c u d C6 C11 R3 o r P FC00081 e t le o s b O - Figure 17. Offline Power Supply With Optocoupler Feedback F1 BR1 TR2 C1 TR1 (s) AC IN R9 ct u d o r P e t e l o s b O D2 L2 +Vcc D1 C2 C7 C9 R1 C3 GND D3 C10 R7 C4 R2 VDD DRAIN - U1 OSC 13V VIPer100 + COMP SOURCE C5 C11 C6 R3 R6 ISO1 R4 C8 U2 R5 FC00091 12/24 ) s t( VIPer100/SP - VIPer100A/ASP Operation Description: Current Mode Topology: The current mode control method, like the one integrated in the VIPer100/100A, uses two control loops an inner current control loop and an outer loop for voltage control. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage VS proportional to this current. When VS reaches VCOMP (the amplified output voltage error) the power switch is switched off. Thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. This results in improved line regulation, instantaneous correction to line changes, and better stability for the voltage regulation loop. Current mode topology also ensures good limitation in case there is a short circuit. During the first phase the output current increases slowly following the dynamic of the regulation loop. Then it reaches the maximum limitation current internally set and finally stops because the power supply on VDD is no longer correct. For specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the COMP pin. An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in case there are current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. c u d Stand-by Mode e t le ) s t( o r P Stand-by operation in nearly open load conditions automatically leads to a burst mode operation allowing voltage regulation on the secondary side. The transition from normal operation to burst mode operation happens for a power PSTBY given by : so Where: b O - 1 2 F P STBY = --- L P I STBY SW 2 LP is the primary inductance of the transformer. FSW is the normal switching frequency. ) s ( ct ISTBY is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. This current can be computed as : ( t b + t d )V IN u d o I STBY = ----------------------------Lp tb + td is the sum of the blanking time and of the propagation time of the internal current sense and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. r P e t e l o As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the 13V regulation level, forcing the output voltage of the transconductance amplifier to low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power switch is maintained in the Off state, resulting in missing cycles and zero duty cycle. As soon as VDD gets back to the regulation level and the VCOMPth threshold is reached, the device operates again. The above cycle repeats indefinitely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. The equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input main supply lines. This mode of operation allows the VIPer100/100A to meet the new German "Blue Angel" Norm with less than 1W total power consumption for the system when working in stand-by mode. The output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because of the output capacitors and low output current drawn in such conditions.The normal operation resumes automatically when the power gets back to higher levels than PSTBY. s b O 13/24 VIPer100/SP - VIPer100A/ASP High Voltage Start-up Current Suorce An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and also provided to the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device becomes active mode and starts switching. The start-up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on (see Figure 18). In case there are abnormal conditions where the auxiliary winding is unable to provide the low voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the external capacitor discharges to the low threshold voltage VDDoff of the UVLO logic, and the device goes back to the inactive state where the internal circuits are in standby mode and the start-up current source is activated. The converter enters a endless start-up cycle, with a start-up duty cycle defined by the ratio of charging current towards discharging when the VIPer100/100A tries to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle while the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage. ) s t( This low value start-up duty cycle prevents the application of stress to the output rectifiers as well as the transformer when a short circuit occurs. c u d The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start up, when the device starts switching. This time tSS depends on many parameters, among which transformer design, output capacitors, soft start feature, and compensation network implemented on the COMP pin. The following formula can be used for defining the minimum capacitor needed: I e t le where: o r P t DD SS C VDD > -------------------V DDhyst IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and I DD2 values. o s b O - tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value). ) s ( ct The soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics of (see Figure 19) can be used. It mixes a high performance compensation network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. u d o r P e If the device is intentionally shut down by tying the COMP pin to ground, the device is also performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff. t e l o This voltage can be used for supplying external functions, provided that their consumption does not exceed 0.5mA. (see Figure 20) page 17 shows a typical application of this function, with a latched shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state until the input voltage is removed. s b O 14/24 VIPer100/SP - VIPer100A/ASP Figure 18. Behaviour of the high voltage current source at start-up VDD 2 mA VDDon VDDoff 15 mA DRAIN 3 mA VDD 1 mA 15 mA CVDD Ref. t Auxiliary primary winding UNDERVOLTAGE LOCK OUT LOGIC VIPer100 SOURCE Start up duty cycle ~ 12% FC00100 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 15/24 VIPer100/SP - VIPer100A/ASP Transconductance Error Amplifier The VIPer100/100A includes a transconductance error amplifier. Transconductance Gm is the change in output current (ICOMP) versus change in input voltage (VDD). Thus: G m ∂I OM P = ------C -----------------∂ V DD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: Z CO MP ∂VCOMP 1 ∂ VCOMP = -------------------------- = --------- × -------------------------G ∂ I CO MP ∂VDD m This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: AVOL = Gm x ZCOMP where Gm value for VIPer100/100A is 1.5 mA/V typically. Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z can be connected between the COMP pin and ground in order to define the transfer function F of the error amplifier more accurately, according to the following equation (very similar to the one above): c u d F(S) = Gm x Z(S) ) s t( o r P The error amplifier frequency response is reported in figure 10 page 8 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 330KΩ. More complex impedance can be connected on the COMP pin to achieve different compensation level. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. This configuration is illustrated in (see Figure 21) page 17. e t le o s b O - As shown in (see Figure 21) an additional noise filtering capacitor of 2.2nF is generally needed to avoid any high frequency interference. Is also possible to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. (see Figure 22) shows such a configuration. Note: R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. ) s ( ct u d o External Clock Synchronization: r P e The OSC pin provides a synchronisation capability when connected to an external frequency source. (see Figure 23) page17 shows one possible schematic to be adapted, depending the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor. t e l o s b O Primary Peak Current Limitation The primary IDPEAK current and, consequently, the output power can be limited using the simple circuit shown in (see Figure 24) page 18. The circuit based on Q1, R1 and R2 clamps the voltage on the COMP pin in order to limit the primary peak current of the device to a value: V – 0.5 where: R 1 + R2 V COM P = 0.6 × -------------------R 2 The suggested value for R1+R2 is in the range of 220KΩ. 16/24 I D PEAK = ------C----OM -----------P--------------H ID VIPer100/SP - VIPer100A/ASP Over-Temperature Protection Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at which over-temperature cut-out occurs is 140ºC, while the typical value is 170ºC. The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 11) page 8.. Figure 19. Mixed Soft Start and Compensation Figure 20. Latched Shut Down D2 U1 VIPER100 VDD D3 DRAIN VDD - - OSC R3 + SOURCE COMP SOURCE D1 C4 R3 AUXILIARY WINDING R2 R1 R4 R2 Shutdown D1 Q1 + C2 C1 Figure 21. Typical Compensation Network c u d DRAIN e t le R2 13V C2 R1 so + COMP SOURCE R1 C1 c u d (t s) o r P Figure 22. Slope Compensation U1 VIPER100 VDD b O - U1 V IP E R 1 0 0 VD D D R A IN - O SC 13 V + CO M P Q1 C1 C3 R3 FC 00 1 4 1 Figure 23. External Clock Sinchronisation t e l o Figure 24. Current Limitation Circuit Example U1 V IP E R 1 0 0 V DD s b O SO UR CE C2 FC00121 o r P e ) s t( FC00110 FC00131 OSC + 13V COMP + C3 DRAIN Q2 OSC 13V U1 VIPER100 R1 U1 VIPER100 VDD D R A IN - O SC 13V + COMP DRAIN SO U RC E - OSC 13V + COMP SOURCE R1 10 kΩ Q1 R2 FC00220 FC 00240 17/24 VIPer100/SP - VIPer100A/ASP Figure 25. Input Voltage Surges Protection D1 R1 (Optional) R2 39R Auxilliary winding VDD C1 Bulk capacitor C2 DRAIN OSC 22nF 13V VIPerXX0 + COMP SOURCE c u d Electrical Over Stress Ruggedness ) s t( The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages most of the time. However in some cases, the voltage surges coupled through the transformer auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events may trigger the VDD internal protection circuitry which could be damaged by the strong discharge current of the VDD bulk capacitor. The simple RC filter shown in (see Figure 25) page 17 can be implemented to improve the application immunity to such surges. e t le ) s ( ct u d o r P e t e l o s b O 18/24 o s b O - o r P VIPer100/SP - VIPer100A/ASP Figure 26. Recommended Layout T1 D1 C7 D2 To secondary filtering and load R1 VDD DRAIN - C1 OSC C5 + 13V From input diodes bridge COMP SOURCE U1 VIPerXX0 R2 C6 C2 C3 ISO1 C4 FC00500 c u d Layout Considerations e t le ) s t( o r P Some simple rules insure a correct running of switching power supplies. They may be classified into two categories: o s b O - - Minimizing power loops: The switched power current must be carefully analysed and the corresponding paths must be as small an inner loop area as possible. This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. ) s ( ct - Using different tracks for low level and power signals: Interference due to mixing of signal and power may result in instabilities and/or anomalous behaviour of the device in case of violent power surge (Input overvoltages, output short circuits...). u d o In case of VIPer, these rules apply as shown on (see Figure 26). r P e • Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized. • C6 must be as close as possible to T1. t e l o • Signal components C2, ISO1, C3, and C4 are using a dedicated track connected directly to the power source of the device. s b O 19/24 VIPer100/SP - VIPer100A/ASP Pentawatt HV Mechanical Data mm. inch Dim Min. Typ. Maw. Min. Typ. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.11 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 H2 10.40 10.05 10.40 L 15.60 17.30 6.14 L1 14.60 15.22 0.575 L2 21.20 21.85 L3 22.20 22.82 L5 2.60 3 L6 15.10 15.80 P e let L7 6 M 2.50 M1 4.50 R 0.50 o r P e Diam 3.65 (s) 0.396 ro c u d 0.835 0.409 0.681 0.599 0.860 0.874 0.898 0.102 0.118 0.594 0.622 6.60 0.236 0.260 3.10 0.098 0.122 5.60 0.177 0.220 o s b O - ct du ) s t( 0.409 H3 V4 0.02 90° 3.85 0.144 0.152 t e l o s b O P023H3 20/24 Max. VIPer100/SP - VIPer100A/ASP Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data mm. inch Dim Min. Typ. Maw. Min. Typ. Max. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.110 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 H2 10.40 H3 10.05 10.40 0.396 L 16.42 17.42 0.646 L1 14.60 15.22 0.575 L3 20.52 21.52 L5 2.60 3.00 L6 15.10 15.80 L7 6.00 6.60 P e let M 2.50 M1 5.00 R 0.50 V4 90° Diam 3.65 o r P e ct du c u d ro 0.409 0.686 0.599 0.847 0.102 0.118 0.594 0.622 0.236 0.260 3.10 0.098 0.122 5.70 0.197 0.224 0.02 0.020 90° 3.85 0.144 0.154 L t e l o 0.808 o s b O - (s) ) s t( 0.409 L1 E A M M1 C R D s b O Resin between leads L6 L7 V4 H2 H3 H1 G1 G2 F DIA L5 L3 21/24 VIPer100/SP - VIPer100A/ASP Figure 27. Pentawatt HV Tube Shipment ( no suffix ) Base Q.ty 50 Bulk Q.ty 1000 Tube length ( ± 0.5 ) 532 A 18 B 33.1 C ( ± 0.1) 1 All dimensions are in mm. c u d e t le ) s ( ct u d o r P e t e l o s b O 22/24 o s b O - o r P ) s t( VIPer100/SP - VIPer100A/ASP Table 13. Revision history Date Revision Changes 02-May-2005 1 Initial release. 08-JUn-2005 2 Update without PowerSO-10 TM c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 23/24 VIPer100/SP - VIPer100A/ASP c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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