VIPER100BSP

® VIPer100B VIPer100BSP SMPS PRIMARY I.C. PRELIMINARY DATA T YPE VIPer100B/BSP V DSS 400V In 6A R DS(on) 1.1 Ω 10 PENTAWATT HV FEATURE s ADJUSTABLE SWITCHING FREQUENCY UP TO 200KHZ s CURRENT MODE CONTROL s SOFT START AND SHUT DOWN CONTROL s AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET ”BLUE ANGEL” NORM ( 1.2 KΩ: 2.3 FSW = D RT CT MAX CLK Ct ~360Ω DMAX = 1 − 550 RT − 150 Recommended DMAX values: 100KHz: > 80% 200KHz: > 70% FC00050 Maximum duty cycle vs Rt 1 FC00040 0.9 0.8 Dmax 0.7 0.6 0.5 1 2 3 5 10 20 30 50 Rt (kΩ) Oscillator frequency vs Rt and Ct 1,000 Ct = 1.5 nF FC00030 500 Ct = 2.7 nF Frequency (kHz) 300 200 Ct = 4.7 nF Ct = 10 nF 100 50 30 1 2 3 5 10 20 30 50 Rt (kΩ) 8/20 VIPER100B/BSP Figure 10: Error Amplifier Frequency Response FC00200 60 RCOMP = +∞ RCOMP = 270k Voltage Gain (dB) 40 RCOMP = 82k RCOMP = 27k 20 RCOMP = 12k 0 (20) 0.001 0.01 0.1 1 10 Frequency (kHz) 100 1,000 Figure 11: Error Amplifier Phase Response FC00210 200 RCOMP = +∞ 150 Phase (°) 100 50 0 (50) 0.001 RCOMP = 270k RCOMP = 82k RCOMP = 27k RCOMP = 12k 0.01 0.1 1 10 Frequency (kHz) 100 1,000 9/20 VIPER100B/BSP Figure 12: Avalanche Test Circuit L1 1mH 2 VDD 1 3 DRAIN Q1 2 x STHV102FI in parallel R1 BT1 0 to 20V COMP SOURCE 5 4 47 GENERATOR INPUT 500us PULSE OSC 13V + BT2 12V C1 47uF 16V U1 VIPer100B R2 1k R3 100 FC00195B 10/20 VIPER100B/BSP Figure 13: Off Line Power Supply With Auxiliary Supply Feedback F1 C1 AC IN TR2 BR1 TR1 D1 C2 R1 C3 D3 C10 R7 C4 GND D2 L2 +Vcc R9 C7 C9 R2 VDD DRAIN OSC 13V C5 + COMP SOURCE C6 C11 VIPer100B R3 FC00081B Figure 14: Off Line Power Supply With Optocoupler Feedback F1 TR2 BR1 TR1 D1 C2 R1 C3 D3 C10 R7 C4 GND C7 C9 D2 L2 +Vcc C1 AC IN R9 R2 VDD DRAIN OSC 13V C5 + COMP SOURCE VIPer100B C11 C6 R3 ISO1 R6 R4 C8 U2 R5 FC00091B 11/20 VIPER100B/BSP OPERATION DESCRIPTION : CURRENT MODE TOPOLOGY: The current mode control method, like the one integrated in the VIPer100B/BSPuses two control loops - an inner current control loop and an outer loop for voltage control. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage VS proportional to this current. When VS reaches VCOMP (the amplified output voltage error) the power switch is switched off. Thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. This results in an improved line regulation, instantaneous correction to line changes and better stability for the voltage regulation loop. Current mode topology also ensures good limitation in the case of short circuit. During a first phase the output current increases slowly following the dynamic of the regulation loop. Then it reaches the maximum limitation current internally set and finally stops because the power supply on VDD is no longer correct. For specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the COMP pin. An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. STAND-BY MODE Stand-by operation in nearly open load condition automatically leads to a burst mode operation allowing voltage regulation on the secondary side. The transition from normal operation to burst mode operation happens for a power PSTBY given by : 1 2 PSTBY = LP ISTBY FSW 2 12/20 Where: LP is the primary inductance of the transformer. FSW is the normal switching frequency. ISTBY is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. This current can be computed as : (tb + td) VIN ISTBY = LP tb + td is the sum of the blanking time and of the propagation time of the internal current sense and comparator, and represents roughly the minimum on time of the device. Note that PSTBY may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the 13V regulation level forcing the output voltage of the transconductance amplifier to low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power switch is maintained in the off state, resulting in missing cycles and zero duty cycle. As soon as VDD gets back to the regulation level and the VCOMPth threshold is reached, the device operates again. The above cycle repeats indefinitely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. The equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input mains lines. This mode of operation allows the VIPer100B/BSP to meet the new German ”Blue Angel” Norm with less than 1W total power consumption for the system when working in stand-by. The output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because of the output capacitors and of the low output current drawn in such conditions.The normal operation resumes automatically when the power get back to higher levels than PSTBY. HIGH VOLTAGE START-UP CURRENT SOURCE An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits which are VIPER100B/BSP placed into a standby mode with reduced consumption and also provided to the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device turns into active mode and starts switching. The start up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on figure 15. In case of abnormal condition where the auxiliary winding is unable to provide the low voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the external capacitor discharges itself down to the low threshold voltage VDDoff of the UVLO logic, and the device get back to the inactive state where the internal circuits are in standby mode and the start up current source is activated. The converter enters a endless start up cycle, with a start-up duty cycle defined by the ratio of charging current towards discharging when the VIPer100B/BSP tries to start. This ratio is fixed by design to 2 to 15, which gives a 12% start up duty cycle while the power dissipation at start up is approximately 0.6 W, for a 230 Vrms input voltage. This low value of start-up duty cycle prevents the stress of the output rectifiers and of the transformer when in short circuit. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start up, when the device starts switching. This time tSS depends on many parameters, among which transformer design, output capacitors, soft start feature and compensation network implemented on the COMP pin. The following formula can be used for defining the minimum capacitor needed: IDD tSS CVDD > VDDhyst where: IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2 values. tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. VDDhyst is the voltage hysteresis of the UVLO logic. Refer to the minimum specified value. Soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics of figure 16 can be Figure 15: Behaviour of the high voltage current source at start-up VDD VDDon VDDoff 2 mA 15 mA C VDD VDD 1 mA 15 mA 3 mA DRAIN Ref. t Auxiliary primary winding UNDERVOLTAGE LOCK OUT LOGIC VIP er100B SOURCE Sta rt up duty cycle ~ 10% FC00100B 13/20 VIPER100B/BSP used. It mixes a high performance compensation network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. If the device is intentionally shut down by putting the COMP pin to ground, the device is also performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff. This voltage can be used for supplying external functions, provided that their consumption doesn’t exceed 0.5mA. Figure 17 shows a typical application of this function, with a latched shut down. Once the ”Shutdown” signal has been activated, the device remains in the off state until the input voltage is removed. TRANSCONDUCTANCE ERROR AMPLIFIER The VIPer100B/BSP includes a transconductance error amplifier. Transconductance Gm is the change in output current (ICOMP) versus change in input voltage (VDD). Thus: ∂ ICOMP Gm = ∂ VDD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: ∂ VCOMP ∂ VCOMP 1 ZCOMP = = x ∂ ICOMP Gm ∂ VDD This last equation shows that the open loop gain AVOL can be related to Gm and Z COMP: AVOL = Gm x ZCOMP where Gm value for VIPer100B/BSP is 1.5 mA/V typically. Gm is well defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z can be connected between the COMP pin and ground in order to define more accurately the transfer function F of the error amplifier, according to the following equation, very similar to the one above: F(S) = Gm x Z(S) The error amplifier frequency response is reported in figure 10 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 330 KΩ. More complex impedance can be connected on the COMP pin to achieve different compensation laws. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. This configuration is illustrated on figure 18. As shown in figure 18 an additional noise filtering capacitor of 2.2 nF is generally needed to avoid any high frequency interference. It can be also interesting to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. Figure 19 shows such a configuration. Note that R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. EXTERNAL CLOCK SYNCHRONIZATION: The OSC pin provides a synchronisation capability, when connected to an external Figure 17: Latched Shut Down Figure 16: Mixed Soft Start and Compensation D2 VIPer100B VDD DRAIN D3 R1 VDD VIPer100B DRAIN OSC 13V + COMP SOURCE R3 D1 Q2 OSC 13V + COMP SOURCE AUXILIARY WINDING R3 R2 C4 R1 R2 R4 Shutdo wn + C3 C1 + C2 Q1 D1 FC0 0131B FC00110B 14/20 VIPER100B/BSP f requency source. Figure 20 shows one possible schematic to be adapted depending the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor. PRIMARY PEAK CURRENT LIMITATION The primary IDPEAK current and, as resulting effect, the output power can be limited using the simple circuit shown in figure 21. The circuit based on Q1, R1 and R2 clamps the voltage on the COMP pin in order to limit the primary peak current of the device to a value: IDPEAK = where: VCOMP − 0.5 HID R1 + R2 VCOMP = 0.6 x R2 The suggested value for R1+R2 is in the range of 220KΩ. OVER-TEMPERATURE PROTECTION: Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at which over-temperature cut-out occurs is 140oC while the typical value is 170oC. The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40oC below Figure 19: Slope Compensation Figure 18: Typical Compensation Network VIPer100B VDD OSC 13V DRAIN + COMP SOURCE R2 R1 VIPer100B VDD OSC 13V DRAIN + COMP SOURCE C2 R1 C1 C2 Q1 C3 C1 R3 F C00121B FC0 0141B Figure 20:External Clock Synchronization Figure 21:Current Limitation Circuit Example VIPer10 0B VDD OSC 13V DRAIN + COMP SOURCE VIPer100B VDD OSC DRAIN 13V + COMP SOURCE R1 Q1 R2 10 kΩ FC00220B FC0 0240B 15/20 VIPER100B/BSP Figure 22: Recommended layout T1 D1 D2 C7 To secon a d ry filte ringa ndloa d R1 2 VDD DRAIN 3 C1 - 1 OSC 13V Frominp ut diod b g es rid e + COMP SOURCE C5 U1 VIPer100B R2 C2 C3 ISO1 C4 5 4 C6 FC00500B LAYOUT CONSIDERATIONS Some simple rules insure a correct running of switching power supplies. They may be classified into two categories: - To minimise power loops: the way the switched power current must be carefully analysed and the corresponding paths must present the smallest inner loop area as possible. This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. power ones. The interferences due to a mixing of signal and power may result in instabilities and/or anomalous behaviour of the device in case of violent power surge (Input overvoltages, output short circuits...). In case of VIPer, these rules apply as shown on figure 22. The loops C1-T1-U1, C5-D2-T1, C7-D1-T1 must be minimised. C6 must be as close as possible from T1. The signal components C2, ISO1, C3 and C4 are using a dedicated track to be connected directly to the source of the device. - To use different tracks for low level signals and 16/20 VIPER100B/BSP PENTAWATT HV (VERTICAL) MECHANICAL DATA DIM. A C D E F G1 G2 H1 H2 H3 L L1 L2 L3 L5 L6 L7 M M1 R V4 Diam. mm TYP. inch TYP. MIN. 4.30 1.17 2.40 0.35 0.60 4.90 7.42 9.30 10.05 16.60 14.60 21.20 22.20 2.60 15.10 6.00 2.50 7.56 MAX. 4.80 1.37 2.80 0.55 0.80 5.28 7.82 9.70 10.40 10.40 17.30 15.22 21.85 22.82 3.00 15.80 6.60 3.10 8.16 MIN. 0.169 0.046 0.094 0.014 0.024 0.193 0.292 0.366 0.396 0.653 0.575 0.835 0.874 0.102 0.594 0.236 0.098 0.298 MAX. 0.189 0.054 0.110 0.022 0.031 0.208 0.308 0.382 0.409 0.409 0.681 0.599 0.860 0.898 0.118 0.622 0.260 0.122 0.321 0.50 90o 3.70 3.90 0.146 0.020 90 0.154 L E L1 M1 M R Resin between leads A D C L6 L7 V4 G2 G1 F L2 L3 L5 H1 H3 Diam H2 P023H3 17/20 VIPER100B/BSP PENTAWATT HV 022Y(VERTICAL HIGH PITCH) MECHANICAL DATA DIM. A C D E F G1 G2 H1 H2 H3 L L1 L3 L5 L6 L7 M M1 R V4 Diam. mm TYP. inch TYP. MIN. 4.30 1.17 2.40 0.35 0.60 4.90 7.42 9.30 10.05 16.42 14.60 20.52 2.60 15.10 6.00 2.50 5.00 MAX. 4.80 1.37 2.80 0.55 0.80 5.28 7.82 9.70 10.40 10.40 17.42 15.22 21.52 3.00 15.80 6.60 3.10 5.70 MIN. 0.169 0.046 0.094 0.014 0.024 0.193 0.292 0.366 0.396 0.646 0.575 0.808 0.102 0.594 0.236 0.098 0.197 MAX. 0.189 0.054 0.110 0.022 0.031 0.208 0.308 0.382 0.409 0.409 0.686 0.599 0.847 0.118 0.622 0.260 0.122 0.224 0.50 o 90 3.70 3.90 0.146 0.020 90o 0.154 L L1 E M1 M R Resin between leads A D C L6 L7 V4 G2 G1 F L3 L5 H1 H3 Diam H2 P023H2 18/20 VIPER100B/BSP PowerSO-10 MECHANICAL DATA DIM. A A1 B C D D1 e E E1 E2 E3 E4 F h H L q α 0o 13.80 1.20 1.70 8o 9.30 7.20 7.20 6.10 5.90 1.25 0.50 14.40 1.80 0.543 0.047 0.067 mm MIN. 3.35 0.00 0.40 0.35 9.40 7.40 1.27 9.50 7.40 7.60 6.35 6.10 1.35 0.366 0.283 0.283 0.240 0.232 0.049 0.002 0.567 0.071 TYP. MAX. 3.65 0.10 0.60 0.55 9.60 7.60 MIN. 0.132 0.000 0.016 0.013 0.370 0.291 0.050 0.374 0.291 0.300 0.250 0.240 0.053 inch TYP. MAX. 0.144 0.004 0.024 0.022 0.378 0.300 B 0.10 A B 10 = H = A F A1 = 6 = = = E = 1 5 = E2 E3 E1 E4 = = A = SEATING PLANE DETAIL ”A” e 0.25 M B C Q h D = D1 = = = SEATING PLANE = A1 L DETAIL ”A” α 0068039-C 19/20 VIPER100B/BSP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 20/20