VIPER16
Fixed frequency VIPer™ plus family
Datasheet - production data
• Standby power < 30 mW at 230 VAC
• Limiting current with adjustable set point
• On-board soft-start
• Safe auto-restart after a fault condition
62QDUURZ
• Hysteretic thermal shutdown
',3
Application
Figure 1. Typical application
• Replacement of capacitive power supply
• Auxiliary power supply for appliances,
• Power metering
• LED drivers
Description
Features
• 800 V avalanche rugged power section
• PWM operation with frequency jittering for low
EMI
• Operating frequency:
– 60 kHz for L type
– 115 kHz for H type
The device is an off-line converter with an 800 V
avalanche ruggedness power section, a PWM
controller, user defined overcurrent limit,
protection against feedback network
disconnection, hysteretic thermal protection, soft
start up and safe auto restart after any fault
condition. It is able to power itself directly from the
rectified mains, eliminating the need for an
auxiliary bias winding. Advance frequency jittering
reduces EMI filter cost. Burst mode operation and
the devices very low consumption both help to
meet the standard set by energy saving
regulations.
• No need of auxiliary winding for low power
application
Table 1. Device summary
Order codes
Package
Packaging
DIP-7
Tube
VIPER16LN
VIPER16HN
VIPER16HD
Tube
VIPER16HDTR
Tape and reel
SO16 narrow
VIPER16LD
Tube
VIPER16LDTR
Tape and reel
June 2014
This is information on a product in full production.
DocID15232 Rev 7
1/30
www.st.com
Contents
VIPER16
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8
High voltage current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10
Soft start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11
Adjustable current limit set point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12
FB pin and COMP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
13
Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
14
Automatic auto restart after overload or short-circuit . . . . . . . . . . . . . 20
15
Open loop failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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VIPER16
Contents
16
Layout guidelines and design recommendations . . . . . . . . . . . . . . . . 23
17
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Block diagram
1
VIPER16
Block diagram
Figure 2. Block diagram
2
Typical power
Table 2. Typical power
85-265 VAC
230 VAC
Part number
VIPER16
Adapter(1)
Open frame(2)
Adapter(1)
Open frame(2)
9W
10 W
5W
6W
1. Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat
sinking.
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VIPER16
3
Pin settings
Pin settings
Figure 3. Connection diagram (top view)
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'5$,1
'5$,1
1&
'5$,1
1$
'5$,1
'5$,1
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Note:
The copper area for heat dissipation has to be designed under the DRAIN pins.
Table 3. Pin description
Pin N.
Name
Function
1-2
GND
Connected to the source of the internal power MOSFET and controller
ground reference.
-
4
N.A.
Not available for user. This pin is mechanically connected to the
controller die pad of the frame. In order to improve the noise immunity,
is highly recommended connect it to GND (pin 1-2).
2
5
VDD
Supply voltage of the control section. This pin provides the charging
current of the external capacitor.
LIM
This pin allows setting the drain current limitation to a lower value
respect to IDlim, which is the default one. The limit can be reduced by
connecting an external resistor between this pin and GND. In case of
high electrical noise, a capacitor could be connected between this pin
and GND, the capacitor value must be lower than 470 nF in order to
not impact the functionality of the pin. The pin can be left open if
default drain current limitation, IDlim, is used.
FB
Inverting input of the internal trans conductance error amplifier.
Connecting the converter output to this pin through a single resistor
results in an output voltage equal to the error amplifier reference
voltage (see VFB_REF on Table 8). An external resistors divider is
required for higher output voltages.
DIP-7
SO16
1
3
4
6
7
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Pin settings
VIPER16
Table 3. Pin description (continued)
Pin N.
DIP-7
6/30
Name
Function
COMP
Output of the internal trans conductance error amplifier. The
compensation network have to be placed between this pin and GND to
achieve stability and good dynamic performance of the voltage control
loop. The pin is used also to directly control the PWM with an
optocoupler. The linear voltage range extends from VCOMPL to
VCOMPH (Table 8).
SO16
5
8
7,8
13-16
High voltage drain pin. The built-in high voltage switched start-up bias
DRAIN current is drawn from this pin too.
Pins connected to the metal frame to facilitate heat dissipation.
DocID15232 Rev 7
VIPER16
Electrical data
4
Electrical data
4.1
Maximum ratings
Table 4. Absolute maximum ratings
Parameter
Unit
Min
VDRAIN
7, 8
Drain-to-source (ground) voltage
EAV
7, 8
IAR
Max
800
V
Repetitive avalanche energy (limited by TJ = 150 °C)
2
mJ
7, 8
Repetitive avalanche current (limited by TJ = 150 °C)
1
A
IDRAIN
7, 8
Pulse drain current (limited by TJ = 150 °C)
2.5
A
VCOMP
5
Input pin voltage
-0.3
3.5
V
VFB
4
Input pin voltage
-0.3
4.8
V
VLIM
3
Input pin voltage
-0.3
2.4
V
VDD
2
Supply voltage
-0.3
Self
limited
V
IDD
2
Input current
20
mA
Power dissipation at TA < 40 °C (DIP-7)
1
W
Power dissipation at TA < 60 °C (SO16N)
1
W
PTOT
TJ
TSTG
4.2
Value
Pin
(DIP-7)
Symbol
Operating junction temperature range
-40
150
°C
Storage temperature
-55
150
°C
4
kV
1.5
kV
ESD(HBM)
1 to 8
Human body model
ESD(CDM)
1 to 8
Charge device model
Thermal data
Table 5. Thermal data
Symbol
Parameter
Max value
Max value
SO16N
DIP-7
Unit
RthJP
Thermal resistance junction pin
(Dissipated power = 1 W)
35
40
°C/W
RthJA
Thermal resistance junction ambient
(Dissipated power = 1 W)
90
110
°C/W
RthJA
Thermal resistance junction ambient (1)
(Dissipated power = 1 W)
80
90
°C/W
1. When mounted on a standard single side FR4 board with 100 mm2 (0.155 sq in) of Cu (35 μm thick)
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Electrical data
4.3
VIPER16
Electrical characteristics
(TJ = -25 to 125 °C, VDD = 14 V (a); unless otherwise specified)
Table 6. Power section
Symbol
Parameter
Test condition
IDRAIN = 1 mA,
VCOMP = GND, TJ = 25 °C
VBVDSS
Break-down voltage
RDS(on)
Drain-source on state resistance
COSS
IOFF
Min Typ Max Unit
800
IDRAIN = 0.2 A, TJ = 25 °C
20
24
Ω
IDRAIN = 0.2 A, TJ = 125 °C
40
48
Ω
Effective (energy related) output capacitance VDRAIN = 0 to 640 V
OFF state drain current
V
10
pF
VDRAIN = 640 V
VFB = GND
60
μA
VDRAIN = 800 V
VFB = GND
75
μA
Table 7. Supply section
Symbol
Parameter
Test condition
Min Typ Max Unit
Voltage
VDRAIN_START
Drain-source start voltage
IDDch1
Start up charging current
VDRAIN = 100 V to 640 V,
VDD = 4 V
IDDch2
Charging current during operation
VDRAIN = 100 V to 640 V,
VDD = 9 V falling edge
VDD
VDDclamp
VDDon
VDDCSon
VDDoff
40
Operating voltage range
VDD clamp voltage
IDD = 15 mA
60
V
-0.6
-1.8
mA
-7
-14
mA
11.5
23.5
V
23.5
V
VDD start up threshold
12
VDD on internal high voltage current
generator threshold
9.5 10.5 11.5
VDD under voltage shutdown threshold
a. Adjust VDD above VDDon start-up threshold before setting to 14 V
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13
8
14
9
V
V
V
VIPER16
Electrical data
Table 7. Supply section (continued)
Symbol
Parameter
Test condition
Min Typ Max Unit
Current
IDD0
IDD1
Operating supply current, not switching
Operating supply current, switching
FOSC = 0 kHz, VCOMP = GND
0.6
mA
VDRAIN = 120 V,
FSW = 60 kHz
1.3
mA
1.5
mA
0.35
mA
VDRAIN = 120 V,
FSW = 115 kHz
IDDoff
Operating supply current with VDD < VDDoff
VDD < VDDoff
IDDol
Open loop failure current threshold
VDD = VDDclamp
VCOMP = 3.3 V,
4
mA
Table 8. Controller section
Symbol
Parameter
Test condition
Min Typ Max Unit
Error amplifier
VREF_FB
FB reference voltage
3.2
IFB_PULL UP Current pull up
GM
Trans conductance
3.3
3.4
V
-1
μA
2
mA/V
0.5
V
3
V
Current setting (LIM) pin
VLIM_LOW
Low level clamp voltage
ILIM = -100 μA
Compensation (COMP) pin
VCOMPH
Upper saturation limit
TJ = 25 °C
VCOMPL
Burst mode threshold
TJ = 25 °C
VCOMPL_HYS Burst mode hysteresis
HCOMP
TJ = 25 °C
ΔVCOMP / ΔIDRAIN
1.1
1.2
40
4
V
mV
9
V/A
VFB = GND
15
kΩ
Source / sink current
VFB > 100 mV
150
μA
Max source current
VCOMP = GND, VFB = GND
220
μA
ILIM = -10 μA, VCOMP = 3.3 V,
0.38
TJ = 25 °C
0.4 0.42
A
RCOMP(DYN) Dynamic resistance
ICOMP
1
Current limitation
IDlim
Drain current limitation
tSS
Soft-start time
TON_MIN
Minimum turn ON time
IDlim_bm
Burst mode current limitation
8.5
220
VCOMP = VCOMPL
ms
450
ns
85
mA
Overload time
50
ms
Restart time after fault
1
s
Overload
tOVL
tRESTART
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Electrical data
VIPER16
Table 8. Controller section (continued)
Symbol
Parameter
Test condition
Min Typ Max Unit
Oscillator section
FOSC
VIPer16L
54
60
66
kHz
VIPer16H
103
115
127
kHz
Switching frequency
FD
Modulation depth
FM
Modulation frequency
DMAX
Maximum duty cycle
FOSC = 60 kHz
±4
kHz
FOSC = 115 kHz
±8
kHz
230
Hz
70
80
%
Thermal shutdown
TSD
THYST
Thermal shutdown temperature(1)
Thermal shutdown hysteresis(1)
1. Specification assured by design, characterization and statistical correlation.
10/30
DocID15232 Rev 7
150
160
°C
30
°C
VIPER16
Typical electrical characteristics
5
Typical electrical characteristics
Figure 4. IDlim vs TJ
Figure 5. FOSC vs TJ
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Figure 6. VDRAIN_START vs TJ
7->&@
7->&@
Figure 7. HCOMP vs TJ
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Figure 8. GM vs TJ
7->&@
7->&@
Figure 9. VREF_FB vs TJ
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7->&@
7->&@
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DocID15232 Rev 7
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Typical electrical characteristics
VIPER16
Figure 10. ICOMP vs TJ
Figure 11. Operating supply current
(no switching) vs TJ
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7->&@
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Figure 12. Operating supply current (switching)
vs TJ
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Figure 13. IDlim vs RLIM
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7->&@
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Figure 14. Power MOSFET on-resistance vs TJ
12/30
$0Y
Figure 15. Power MOSFET break down voltage
vs TJ
DocID15232 Rev 7
VIPER16
Typical electrical characteristics
Figure 16. Thermal shutdown
VDD
VDDon
VDDCSon
VDDoff
time
IDRAIN
time
TJ
TSD
TSD - THYST
Normal operation
Shut down after over temperature
DocID15232 Rev 7
Normal operation
time
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Typical circuit
6
VIPER16
Typical circuit
Figure 17. Buck converter
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14/30
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VIPER16
Typical circuit
Figure 19. Flyback converter (primary regulation)
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Power section
7
VIPER16
Power section
The power section is implemented with an n-channel power MOSFET with a breakdown
voltage of 800 V min. and a typical RDS(on) of 20 Ω. It includes a SenseFET structure to
allow a virtually lossless current sensing and the thermal sensor.
The gate driver of the power MOSFET is designed to supply a controlled gate current during
both turn-ON and turn-OFF in order to minimize common mode EMI. During UVLO
conditions, an internal pull-down circuit holds the gate low in order to ensure that the power
MOSFET cannot be turned ON accidentally.
8
High voltage current generator
The high voltage current generator is supplied by the DRAIN pin. At the first start up of the
converter it is enabled when the voltage across the input bulk capacitor reaches the
VDRAIN_START threshold, sourcing a IDDch1 current (see Table 7 on page 8); as the VDD
voltage reaches the VDDon threshold, the power section starts switching and the high
voltage current generator is turned OFF. The VIPer16 is powered by the energy stored in
the VDD capacitor.
In steady state condition, if the self biasing function is used, the high voltage current
generator is activated between VDDCSon and VDDon (see Table 7 on page 8), delivering
IDDch2, see Table 7 on page 8 to the VDD capacitor during the MOSFET off time (see
Figure 21 on page 16).
The device can also be supplied through the auxiliary winding; in this case the high voltage
current source is disabled during steady-state operation, provided that VDD is above
VDDCSon.
At converter power-down, the VDD voltage drops and the converter activity stops as it falls
below VDDoff threshold (see Table 7 on page 8).
Figure 21. Power on and power off
VIN
VIN < VDRAIN_START
HV startup is no more activated
VDRAIN_START
VDD
With internal self-supply
Without internal self-supply
regulation is lost here
t
VDDon
VDDCSon
VDDoff
VDRAIN
t
IDD
t
IDDch2
IDDch1
Power-on
16/30
Normal operation
DocID15232 Rev 7
Power-off
t
VIPER16
9
Oscillator
Oscillator
The switching frequency is internally fixed at 60 kHz (part number VIPER16LN or LD) or 115
kHz (part number VIPER16HN or HD).
In both cases the switching frequency is modulated by approximately ±4 kHz (60 kHz
version) or ±8 kHz (115 kHz version) at 230 Hz (typical) rate, so that the resulting spreadspectrum action distributes the energy of each harmonic of the switching frequency over a
number of sideband harmonics having the same energy on the whole but smaller
amplitudes.
10
Soft start-up
During the converters' start-up phase, the soft-start function progressively increases the
cycle-by-cycle drain current limit, up to the default value IDlim. By this way the drain current
is further limited and the output voltage is progressively increased reducing the stress on the
secondary diode. The soft-start time is internally fixed to tSS, see typical value
on Table 8 on page 9, and the function is activated for any attempt of converter start-up and
after a fault event.
This function helps prevent transformers' saturation during start-up and short-circuit.
11
Adjustable current limit set point
The VIPer16 includes a current mode PWM controller: cycle by cycle the drain current is
sensed through the integrated resistor RSENSE and the voltage is applied to the non
inverting input of the PWM comparator, see Figure 2 on page 4. As soon as the sensed
voltage is equal to the voltage derived from the COMP pin, the power MOSFET is switched
OFF.
In parallel with the PWM operations, the comparator OCP, see Figure 2 on page 4, checks
the level of the drain current and switch OFF the power MOSFET in case the current is
higher than the threshold IDlim, see Table 8 on page 9.
The level of the drain current limit, IDlim, can be reduced depending from the sunk current
from the pin LIM. The resistor RLIM, between LIM and GND pins, fixes the current sunk and
than the level of the current limit, IDlim, see Figure 13 on page 12.
When the LIM pin is left open or if the RLIM has an high value (i.e. > 80 kΩ) the current limit
is fixed to its default value, IDlim, as reported on Table 8 on page 9.
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FB pin and COMP pin
12
VIPER16
FB pin and COMP pin
The device can be used both in non-isolated and in isolated topology. In case of nonisolated topology, the feedback signal from the output voltage is applied directly to the FB
pin as inverting input of the internal error amplifier having the reference voltage, VREF_FB,
see the Table 8 on page 9.
The output of the error amplifier sources and sinks the current, ICOMP, respectively to and
from the compensation network connected on the COMP pin. This signal is then compared,
in the PWM comparator, with the signal coming from the SenseFET; the power MOSFET is
switched off when the two values are the same on cycle by cycle basis. See the Figure 2 on
page 4 and the Figure 22 on page 18.
When the power supply output voltage is equal to the error amplifier reference voltage,
VREF_FB, a single resistor has to be connected from the output to the FB pin. For higher
output voltages the external resistor divider is needed. If the voltage on FB pin is
accidentally left floating, an internal pull-up protects the controller.
The output of the error amplifier is externally accessible through the COMP pin and it’s used
for the loop compensation: usually an RC network.
As reported on Figure 22 on page 18, in case of isolated power supply, the internal error
amplifier has to be disabled (FB pin shorted to GND). In this case an internal resistor is
connected between an internal reference voltage and the COMP pin, see the Figure 22 on
page 18. The current loop has to be closed on the COMP pin through the opto-transistor in
parallel with the compensation network. The VCOMP dynamics ranges is between VCOMPL
and VCOMPH as reported on Figure 23 on page 19.
When the voltage VCOMP drops below the voltage threshold VCOMPL, the converter enters
burst mode, see Section 13 on page 19.
When the voltage VCOMP rises above the VCOMPH threshold, the peak drain current will
reach its limit, as well as the deliverable output power.
Figure 22. Feedback circuit
Without Isolation:
switch open & E/A enabled
VREF
With Isolation:
switch closed & E/A disabled
VOUT
RCOMP
VCOMPL
+
PWM stop
-
SW
BUS
FB
from RSENSE
-
VREF_FB
+
RH
E/A
+
Isolation
RL
nR
No
Isolation
R
COMP
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to PWM
VIPER16
Burst mode
Figure 23. COMP pin voltage versus IDRAIN
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13
Burst mode
When the voltage VCOMP drops below the threshold, VCOMPL, the power MOSFET is kept in
OFF state and the consumption is reduced to IDD0 current, as reported on Table 7 on
page 8. As reaction at the energy delivery stop, the VCOMP voltage increases and as soon
as it exceeds the threshold VCOMPL + VCOMPL_HYS, the converter starts switching again with
consumption level equal to IDD1 current. This ON-OFF operation mode, referred to as “burst
mode” and reported on Figure 24 on page 19, reduces the average frequency, which can go
down even to a few hundreds hertz, thus minimizing all frequency-related losses and
making it easier to comply with energy saving regulations. During the burst mode, the drain
current limit is reduced to the value IDlim_bm (reported on Table 8 on page 9) in order to
avoid the audible noise issue.
Figure 24. Load-dependent operating modes: timing diagrams
V COMP
V COMPL +V COMPL_HYS
V COMPL
time
I DD
I DD1
I DD0
time
I DRAIN
I Dlim_bm
time
Burst Mode
AM13269v1
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Automatic auto restart after overload or short-circuit
14
VIPER16
Automatic auto restart after overload or short-circuit
The overload protection is implemented in automatic way using the integrated up-down
counter. Every cycle, it is incremented or decremented depending if the current logic detects
the limit condition or not. The limit condition is the peak drain current, IDlim , reported on
Table 8 on page 9 or the one set by the user through the RLIM resistor, as reported in
Figure 13 on page 12. After the reset of the counter, if the peak drain current is continuously
equal to the level IDlim, the counter will be incremented till the fixed time, tOVL, after that will
be disabled the power MOSFET switch ON. It will be activated again, through the soft start,
after the tRESTART time, see the Figure 25 and Figure 26 on page 20 and the mentioned
time values on Table 8 on page 9.
In case of overload or short-circuit event, the power MOSFET switching will be stopped after
a time that depends from the counter and that can be as maximum equal to tOVL. The
protection will occur in the same way until the overload condition is removed, see Figure 25
and Figure 26 on page 20. This protection ensures restart attempts of the converter with low
repetition rate, so that it works safely with extremely low power throughput and avoiding the
IC overheating in case of repeated overload events. If the overload is removed before the
protection tripping, the counter will be decremented cycle by cycle down to zero and the IC
will not be stopped.
Figure 25. Timing diagram: OLP sequence (IC externally biased)
VDD
SHORT CIRCUIT
REMOVED HERE
SHORT CIRCUIT
OCCURS HERE
VDDon
VDDCSon
IDRAIN
time
IDlim_bm
t1*
tOVL
tRESTART
tOVL
tRESTART
tSS
tSS
tSS
time
tRESTART
* The time t1 can be lower or equal to the time tOVL
AM13270v1
Figure 26. Timing diagram: OLP sequence (IC internally biased)
VDD
SHORT CIRCUIT
REMOVED HERE
SHORT CIRCUIT
OCCURS HERE
VDDon
VDDCSon
IDRAIN
time
IDlim_bm
t1*
tOVL
tRESTART
tOVL
tRESTART
tSS
tSS
time
tRESTART
tSS
* The time t1 can be lower than or equal to the time tOVL
AM13271v1
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DocID15232 Rev 7
VIPER16
Open loop failure protection
In case the power supply is built in fly-back topology and the VIPer16 is supplied by an
auxiliary winding, as shown in Figure 27 on page 21 and Figure 28 on page 22, the
converter is protected against feedback loop failure or accidental disconnections of the
winding.
The following description is applicable for the schematics of Figure 27 on page 21 and
Figure 28 on page 22, respectively the non-isolated fly-back and the isolated fly-back.
If RH is opened or RL is shorted, the VIPer16 works at its drain current limitation. The output
voltage, VOUT, will increase and so the auxiliary voltage, VAUX, which is coupled with the
output through the secondary-to-auxiliary turns ratio.
As the auxiliary voltage increases up to the internal VDD active clamp, VDDclamp (the value is
reported on Table 8 on page 9) and the clamp current injected on VDD pin exceeds the latch
threshold, IDDol (the value is reported on Table 8 on page 9), a fault signal is internally
generated.
In order to distinguish an actual malfunction from a bad auxiliary winding design, both the
above conditions (drain current equal to the drain current limitation and current higher than
IDDol through VDD clamp) have to be verified to reveal the fault.
If RL is opened or RH is shorted, the output voltage, VOUT, will be clamped to the reference
voltage VREF_FB (in case of non isolated fly-back) or to the external TL voltage reference (in
case of isolated fly-back).
Figure 27. FB pin connection for non-isolated fly-back
RAUX
DAUX
VAUX
CVDD
VDD
VOUT
VCOMPL
+
PWM stop
-
RH
BUS
FB
from RSENSE
-
RL
VREF_FB
+
15
Open loop failure protection
E/A
+
nR
to PWM
R
COMP
RS
CP
CS
AM13272v1
DocID15232 Rev 7
21/30
30
Open loop failure protection
VIPER16
Figure 28. FB pin connection for isolated fly-back
RAUX
DAUX
VAUX
CVDD
VREF
RCOMP
VCOMPL
SW
FB
Disabled
-
PWM stop
BUS
VOUT
from RSENSE
+
VREF_FB
+
E/A
+
nR
-
to PWM
R
ROPTO
RH
COMP
R3
U5
RC
CCOMP
CC
TL
RL
-
AM13273v1
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DocID15232 Rev 7
VIPER16
16
Layout guidelines and design recommendations
Layout guidelines and design recommendations
A proper printed circuit board layout is essential for correct operation of any switch-mode
converter and this is true for the VIPer16 as well. Also some trick can be used to make the
design rugged versus external influences.
Careful component placing, correct traces routing, appropriate traces widths and
compliance with isolation distances are the major issues.
The main reasons to have a proper PCB routing are:
–
Provide a noise free path for the signal ground and for the internal references,
ensuring good immunity against external noises and switching noises
–
Minimize the pulsed loops (both primary and secondary) to reduce the
electromagnetic interferences, both radiated and conducted and passing more
easily the EMC regulations.
The below list can be used as guideline when designing a SMPS using VIPer16.
–
Signal ground routing should be routed separately from power ground and, in
general, from any pulsed high current loop;
–
Connect all the signal ground traces to the power ground, using a single "star
point", placed close to the IC GND pin;
–
With flyback topologies, when the auxiliary winding is used, it is suggested to
connect the VDD capacitor on the auxiliary return and then to the main GND using
a single track;
–
The compensation network should be connected as close as possible to the
COMP pin, maintaining the trace for the GND as short as possible;
–
A small bypass capacitor (a few hundreds pF up to 0.1 µF) to GND might be useful
to get a clean bias voltage for the signal part of the IC and protect the IC itself
during EFT/ESD tests. A low ESL ceramic capacitor should be used, placed as
close as possible to the VDD pin;
–
When using SO16 package it is recommended to connect the pin 4 to GND pin,
using a signal track, in order to improve the noise immunity. This is highly
recommended in case of high nosily environment;
–
An optional capacitor can be connected on the LIM pin in order to improve the IC
noise immunity. It is strongly recommended to don't exceed 470nF.
–
The IC thermal dissipation takes place through the drain pins. An adequate heat
sink copper area has to be designed under the drain pins to improve the thermal
dissipation;
–
It is not recommended to place large copper areas on the GND pins.
–
Minimize the area of the pulsed loops (primary, RCD and secondary loops), in
order to reduce its parasitic self- inductance and the radiated electromagnetic
field: this will greatly reduce the electromagnetic interferences produced by the
power supply during the switching.
DocID15232 Rev 7
23/30
30
Layout guidelines and design recommendations
VIPER16
Figure 29. Suggested routing for converter: flyback case
9287
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*1'
9,3(5
9''
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Figure 30. Suggested routing for converter: buck case
$&
$&
9,3(5
9''
'5$,1
)%
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&203
/,0
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*1'
9287
237,21$/
*1'
24/30
DocID15232 Rev 7
VIPER16
17
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 31. DIP-7 package dimensions
DocID15232 Rev 7
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30
Package mechanical data
VIPER16
Table 9. DIP-7 mechanical data
mm
Dim.
Typ
Min
A
5,33
A1
0,38
A2
3,30
2,92
4,95
b
0,46
0,36
0,56
b2
1,52
1,14
1,78
c
0,25
0,20
0,36
D
9,27
9,02
10,16
E
7,87
7,62
8,26
E1
6,35
6,10
7,11
e
2,54
eA
7,62
eB
L
M
(6)(8)
N
10,92
3,30
2,92
3,81
0,40
0,60
2,508
0,50
N1
O
(7)(8)
0,60
0,548
1- The leads size is comprehensive of the thickness of the leads finishing material.
2- Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side).
3- Package outline exclusive of metal burrs dimensions.
4- Datum plane “H” coincident with the bottom of lead, where lead exits body.
5- Ref. POA MOTHER doc. 0037880
6- Creepage distance > 800 V
7- Creepage distance 250 V
8- Creepage distance as shown in the 664-1 CEI / IEC standard.
26/30
Max
DocID15232 Rev 7
VIPER16
Package mechanical data
Figure 32. SO16N package dimensions
DocID15232 Rev 7
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30
Package mechanical data
VIPER16
Table 10. SO16N mechanical data
mm
Dim.
Min
Typ
A
1.75
A1
0.1
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
9.8
9.9
10
E
5.8
6
6.2
E1
3.8
3.9
4
e
0.25
1.27
h
0.25
0.5
L
0.4
1.27
k
0
8
ccc
28/30
Max
0.1
DocID15232 Rev 7
VIPER16
18
Revision history
Revision history
s
Table 11. Document revision history
Date
Revision
Changes
21-Jan-2009
1
Initial release
07-Dec-2009
2
Updated Figure 7 on page 11
14-May-2010
3
Updated Figure 3 on page 5 and Table 3 on page 5
26-Aug-2010
4
Updated Table 3 on page 5, Figure 16 on page 13 and
Figure 21 on page 16
10-Oct-2011
5
Updated Figure 32 on page 27 and Table 7 on page 8
26-May-2014
6
Updated the features in cover page, Table 3: Pin description,
Table 4: Absolute maximum ratings, Table 6: Power section,
Table 7: Supply section.
Modified Figure 17, 18, 19 and 20.
Added Section 16: Layout guidelines and design
recommendations.
Minor text changes.
13-Jun-2014
7
Updated Table 3: Pin description and Table 6: Power section.
Minor text changes.
DocID15232 Rev 7
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VIPER16
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