VIPer20A-E
SMPS primary I.C.
General features
Type
VDSS
In
RDS(on)
VIPer20A-E
VIPer20ASP-E
VIPer20ADIP-E
700V
700V
700V
0.5A
0.5A
0.5A
18Ω
18Ω
DIP-8
PENTAWATT HV
18Ω
■
Adjustable switching frequency up to 200 kHz
■
Current mode control
■
Soft start and shutdown control
■
Automatic burst mode operation in stand-by
condition able to meet “blue angel” norm ( -------------------V DDhyst
IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2
values.
tSS is the start up time of the converter when the device begins to switch. Worst case is
generally at full load.
VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).
12/34
VIPer20A-E
Operation description
The soft start feature can be implemented on the COMP pin through a simple capacitor which
will be also used as the compensation network. In this case, the regulation loop bandwidth is
rather low, because of the large value of this capacitor. In case a large regulation loop
bandwidth is mandatory, the schematics of (see Figure 17) can be used. It mixes a high
performance compensation network together with a separate high value soft start capacitor.
Both soft start time and regulation loop bandwidth can be adjusted separately.
If the device is intentionally shut down by tying the COMP pin to ground, the device is also
performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff.
This voltage can be used for supplying external functions, provided that their consumption does
not exceed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched
shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state
until the input voltage is removed.
5.4
Transconductance error amplifier
The VIPer20A-E includes a transconductance error amplifier. Transconductance Gm is the
change in output current (ICOMP) versus change in input voltage (VDD). Thus:
∂l COMP
G m = -----------------∂V DD
The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as:
V
V
∂ COMP
1
∂ COMP
Z COMP = -------------------= -------- × -----------------------I
G
∂V DD
m
∂ COMP
This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP:
AVOL = Gm x ZCOMP
where Gm value for VIPer20A-E is 1.5 mA/V typically.
Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances.
An impedance Z can be connected between the COMP pin and ground in order to define the
transfer function F of the error amplifier more accurately, according to the following equation
(very similar to the one above):
F(S) = Gm x Z(S)
The error amplifier frequency response is reported in for different values of a simple resistance
connected on the COMP pin. The unloaded transconductance error amplifier shows an internal
ZCOMP of about 330KΩ. More complex impedance can be connected on the COMP pin to
achieve different compensation level. A capacitor will provide an integrator function, thus
eliminating the DC static error, and a resistance in series leads to a flat gain at higher
frequency, insuring a correct phase margin. This configuration is illustrated in Figure 20
As shown in Figure 19 an additional noise filtering capacitor of 2.2nF is generally needed to
avoid any high frequency interference.
Is also possible to implement a slope compensation when working in continuous mode with
duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the
classical compensation network, and Q1 is injecting the slope compensation with the correct
polarity from the oscillator sawtooth.
13/34
Operation description
5.5
VIPer20A-E
External clock synchronization:
The OSC pin provides a synchronisation capability when connected to an external frequency
source. Figure 21 shows one possible schematic to be adapted, depending the specific needs.
If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is
sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through
the optotransistor.
5.6
Primary peak current limitation
The primary IDPEAK current and, consequently, the output power can be limited using the
simple circuit shown in Figure 22 . The circuit based on Q1, R1 and R2 clamps the voltage on
the COMP pin in order to limit the primary peak current of the device to a value:
V COMP – 0.5
I DPEAK = ------------------------------H ID
where:
R1 + R2
V COMP = 0.6 × ------------------R2
The suggested value for R1+R2 is in the range of 220KΩ.
5.7
Over-temperature protection
Over-temperature protection is based on chip temperature sensing. The minimum junction
temperature at which over-temperature cut-out occurs is 140ºC, while the typical value is
170ºC. The device is automatically restarted when the junction temperature decreases to the
restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 13)
14/34
VIPer20A-E
5.8
Operation description
Operation pictures
Figure 5.
VDD Regulation point
ICOMP
Figure 6.
Undervoltage lockout
IDD
Slope =
Gmin mA/V
ICOMPHI
IDD0
VDD
VDS= 35 V
Fsw = 0
VDDhyst
0
VDDon VDD
VDDoff
ICOMPLO
IDDch
VDDreg
FC00170
FC00150
Figure 7.
Transition time
Figure 8.
Shutdown action
VOSC
ID
t
10% Ipeak
VDS
t
VCOMP
tDISsu
90% VD
VCOMPth
t
10% VD
t
tf
ID
tr
FC00160
t
ENABLE
ENABLE
DISABLE
FC00060
Figure 9.
Breakdown voltage vs temperature
Figure 10. Typical frequency variation
FC00180
1.15
(%)
BVDSS
FC00190
1
0
(Normalized)
1.1
-1
-2
1.05
-3
1
0.95
-4
-5
0
20
40 60 80 100 120
Temperature (°C)
0
20
40 60 80 100 120 140
Temperature (°C)
15/34
VIPer20A-E
Operation description
Figure 11. Behaviour of the high voltage current source at start-up
VDD
2 mA
VDDon
VDDoff
15 mA
3 mA
VDD
1 mA
DRAIN
15 mA
CVDD
Ref.
t
Auxiliary primary
winding
UNDERVOLTAGE
LOCK OUT LOGIC
VIPer20
Start up duty cycle ~ 12%
Figure 12. Start-up waveforms
16/34
SOURCE
FC00101A
VIPer20A-E
Operation description
Figure 13. Over-temperature protection
T
T ts c J
T t s d -T h y s t
t
Vdd
V dd on
V dd off
t
Id
t
V
co m p
t
SC 1 0 1 9 1
17/34
VIPer20A-E
Operation description
Figure 14. Oscillator
For Rt > 1.2kΩ and Ct ≤40KHz
VDD
Rt
OSC
Ct
~360Ω
CLK
FC00050
Ct
Forbidden area
Ct(nF) =
22nF
880
Fsw(kHz)
15nF
Forbidden area
Fsw
40kHz
Oscillator frequency vs Rt and Ct
FC00030
1,000
Ct = 1.5 nF
500
Frequency (kHz)
Ct = 2.7 nF
300
Ct = 4.7 nF
200
Ct = 10 nF
100
50
30
1
2
3
5
Rt (kΩ)
18/34
10
20
30
50
VIPer20A-E
Operation description
Figure 15. Error amplifier frequency response
FC00200
60
RCOMP = +∞
Voltage Gain (dB)
RCOMP = 270k
40
RCOMP = 82k
RCOMP = 27k
20
RCOMP = 12k
0
(20)
0.001
0.01
0.1
1
10
Frequency (kHz)
100
1,000
Figure 16. Error amplifier phase response
FC00210
200
RCOMP = +∞
150
RCOMP = 270k
Phase (°)
RCOMP = 82k
RCOMP = 27k
100
RCOMP = 12k
50
0
(50)
0.001
0.01
0.1
1
10
Frequency (kHz)
100
1,000
19/34
VIPer20A-E
Operation description
Figure 17. Mixed soft start and compensation
Figure 18. Latched shut down
D2
D3
VIPer20
VDD
VDD
-
OSC
13V
VIPer20
R1
DRAIN
Q2
R3
+
COMP
DRAIN
-
OSC
+
13V
SOURCE
D1
COMP SOURCE
AUXILIARY
WINDING
R3
R2
R1
C4
R2
+ C3
R4
Shutdown
+ C2
C1
D1
Q1
FC00440
FC00431
Figure 19. Typical compensation network
Figure 20. Slope compensation
VIPer20
VDD
DRAIN
-
OSC
13V
R2
R1
VIPer20
+
VDD
COMP SOURCE
DRAIN
-
OSC
+
13V
COMP SOURCE
C2
R1
C2
C1
Q1
C1
C3
R3
FC00451
FC00461
Figure 21. External clock sinchronisation
Figure 22. Current limitation circuit example
VIPer20
VDD
VIPer20
VDD
OSC
OSC
DRAIN
13V
DRAIN
13V
+
COMP
SOURCE
+
COMP SOURCE
10 kΩ
R1
Q1
FC00470
R2
FC00480
20/34
VIPer20A-E
Electrical over stress
6
Electrical over stress
6.1
Electrical over stress ruggedness
The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or
lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages
most of the time. However in some cases, the voltage surges coupled through the transformer
auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events
may trigger the VDD internal protection circuitry which could be damaged by the strong
discharge current of the VDD bulk capacitor. The simple RC filter shown in Figure 23 can be
implemented to improve the application immunity to such surges.
Figure 23. Input voltage surges protection
R1
D1
(Optional)
R2
39R
Auxilliary winding
C1
Bulk capacitor
VDD
C2
22nF
OSC
DRAIN
13V
VIPerXX0
+
COMP SOURCE
21/34
VIPer20A-E
Layout
7
Layout
7.1
Layout considerations
Some simple rules insure a correct running of switching power supplies. They may be
classified into two categories:
–
Minimizing power loops: The switched power current must be carefully analysed and
the corresponding paths must be as small an inner loop area as possible. This avoids
radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a
better efficiency by eliminating parasitic inductances, especially on secondary side.
–
Using different tracks for low level and power signals: Interference due to mixing of
signal and power may result in instabilities and/or anomalous behaviour of the device
in case of violent power surge (Input overvoltages, output short circuits...).
In case of VIPer, these rules apply as shown on (see Figure 24).
–
Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized.
–
C6 must be as close as possible to T1.
–
Signal components C2, ISO1, C3, and C4 are using a dedicated track connected
directly to the power source of the device.
Figure 24. Recommended layout
T1
D1
C7
D2
R1
VDD
DRAIN
-
C1
OSC
From input
diodes bridge
13V
C5
+
COMP
SOURCE
U1
VIPerXX0
R2
C6
C2
C3
ISO1
C4
FC00500
22/34
To secondary
filtering and load
VIPer20A-E
8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.
These packages have a Lead-free second level interconnect . The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
23/34
VIPer20A-E
Package mechanical data
Table 9.
Pentawatt HV Mechanical data
mm.
inch
Dim
Min
Typ
Max
Min
Typ
A
4.30
4.80
0.169
0.189
C
1.17
1.37
0.046
0.054
D
2.40
2.80
0.094
0.11
E
0.35
0.55
0.014
0.022
F
0.60
0.80
0.024
0.031
G1
4.91
5.21
0.193
0.205
G2
7.49
7.80
0.295
0.307
H1
9.30
9.70
0.366
0.382
H2
10.40
0.409
H3
10.05
10.40
L
15.60
17.30
6.14
0.681
L1
14.60
15.22
0.575
0.599
L2
21.20
21.85
0.835
0.860
L3
22.20
22.82
0.874
0.898
L5
2.60
3
0.102
0.118
L6
15.10
15.80
0.594
0.622
L7
6
6.60
0.236
0.260
0.396
0.409
M
2.50
3.10
0.098
0.122
M1
4.50
5.60
0.177
0.220
R
0.50
0.02
V4
Diam
90°
3.65
3.85
0.144
0.152
Figure 25. Package dimension
P023H3
24/34
Max
VIPer20A-E
Table 10.
Package mechanical data
Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical data
mm.
inch
Dim
Min
Typ
Max
Min
Typ
Max
A
4.30
4.80
0.169
0.189
C
1.17
1.37
0.046
0.054
D
2.40
2.80
0.094
0.110
E
0.35
0.55
0.014
0.022
F
0.60
0.80
0.024
0.031
G1
4.91
5.21
0.193
0.205
G2
7.49
7.80
0.295
0.307
H1
9.30
9.70
0.366
0.382
H2
10.40
0.409
H3
10.05
10.40
0.396
0.409
L
16.42
17.42
0.646
0.686
L1
14.60
15.22
0.575
0.599
L3
20.52
21.52
0.808
0.847
L5
2.60
3.00
0.102
0.118
L6
15.10
15.80
0.594
0.622
L7
6.00
6.60
0.236
0.260
M
2.50
3.10
0.098
0.122
M1
5.00
5.70
0.197
R
0.50
V4
90°
Diam
0.224
0.02
0.020
90°
3.65
3.85
0.144
0.154
Figure 26. Package dimension
L
L1
E
A
M
M1
C
D
R
Resin between
leads
L6
L7
V4
H2
H3
H1
G1
G2
F
DIA
L5
L3
25/34
VIPer20A-E
Package mechanical data
Table 11.
DIP-8 Mechanical data
mm
Inch
Dim.
Min
A
Typ
Min
3.32
Typ
Max
0.131
a1
0.51
B
1.15
1.65
0.045
0.020
0.065
b
0.356
0.55
0.014
0.022
b1
0.204
0.304
0.008
0.012
0.313
0.384
D
E
10.92
7.95
9.75
0.430
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
6.6
0.260
I
5.08
0.200
L
3.18
Z
Figure 27. Package dimensions
26/34
Max
3.81
1.52
0.125
0.150
0.060
VIPer20A-E
Table 12.
Package mechanical data
PowerSO-10 mechanical data
mm
Inch
Dim.
Min
Typ
Max
Min
Typ
Max
A
3.35
3.65
0.132
0.144
A1
0.00
0.10
0.000
0.004
B
0.40
0.60
0.016
0.024
C
0.35
0.55
0.013
0.022
D
9.40
9.60
0.370
0.378
D1
7.40
7.60
0.291
0.300
e
1.27
0.050
E
9.30
9.50
0.366
0.374
E1
7.20
7.40
0.283
0.291
E2
7.20
7.60
0.283
0.300
E3
6.10
6.35
0.240
0.250
E4
5.90
6.10
0.232
0.240
F
1.25
1.35
0.049
0.053
h
0.50
0.002
H
13.80
14.40
0.543
0.567
L
1.20
1.80
0.047
0.071
q
α
1.70
0o
0.067
8o
Figure 28. Package dimension
27/34
VIPer20A-E
Package mechanical data
Figure 29. Power Pad layout
Figure 30. Tube shipment
Table 13.
Tube shipment
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
Casablanca
50
1000
532
10.4
16.4
0.8
Muar
50
1000
532
4.9
17.2
0.8
28/34
VIPer20A-E
Package mechanical data
Figure 31. Reel shipment
Table 14.
Note:
Reel dimension
Base Q.ty
600
Bulk Q.ty
600
A (max)
330
B (min)
1.5
C (± 0.2)
13
F
20.2
G (± 0.2)
24.4
N (min)
60
T (max)
30.4
All dimensoin are in mm.
29/34
VIPer20A-E
Package mechanical data
Figure 32. Tape shipment
Table 15.
Note:
30/34
Tape dimension
Tape width
W
24
Tape Hole Spacing
P0 (± 0.1)
4
Component Spacing
P
24
Hole Diameter
D (± 0.1/-0)
1.5
Hole Diameter
D1 (min)
1.5
Hole Position
F (± 0.05)
11.5
Compartment Depth
K (max)
6.5
Hole Spacing
P1 (± 0.1)
2
All dimensions are in mm.
VIPer20A-E
Package mechanical data
Figure 33. Pentawatt HV tube shipment ( no suffix )
Table 16.
Tube dimension
Base Q.ty
50
Bulk Q.ty
1000
Tube length (± 0.5 )
532
A
18
B
33.1
C (± 0.1)
1
Note:
All dimensions are in mm.
Figure 34. Dip-8 Tube shipment (no suffix)
Table 17.
Tube dimension
Base Q.ty
20
Bulk Q.ty
1000
Tube length (± 0.5 )
532
A
8.4
B
11.2
C (± 0.1)
0.8
Note:
All dimensions are in mm.
31/34
VIPer20A-E
Order code
9
Order code
Table 18.
32/34
Order code
Part number
Package
VIPer20A-E
PENTAWATT HV
VIPer20A-22-E
PENTAWATT HV (022Y)
VIPer20ADIP-E
DIP-8
VIPer20ASP-E
PowerSO-10
VIPer20A-E
10
Revision history
Revision history
Table 19.
Revision history
Date
Revision
Changes
28-Sep-2005
1
Initial release.
21-Jun-2006
2
New template, few updates
33/34
VIPer20A-E
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