VIPer50-E
SMPS PRIMARY I.C.
General Features
Type VIPer50-E
■
VDSS 620V
In 1.5A
RDS(on) 5Ω
PENTAWATT HV PENTAWATT HV (022Y)
ADJUSTABLE SWITCHING FREQUENCY UP TO 200 kHz CURRENT MODE CONTROL SOFT START AND SHUTDOWN CONTROL AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET “BLUE ANGEL” NORM ( -------------------V DD hyst
where:
IDD is the consumption current on the VDD pin when switching. Refer to specified I DD1 and IDD2 values. tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load.
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VIPer50-E
5 Operation Description
VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value). The soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics of (see Figure 17) can be used. It mixes a high performance compensation network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. If the device is intentionally shut down by tying the COMP pin to ground, the device is also performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff. This voltage can be used for supplying external functions, provided that their consumption does not exceed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state until the input voltage is removed.
5.4
Transconductance Error Amplifier
The VIPer50-E includes a transconductance error amplifier. Transconductance Gm is the change in output current (ICOMP) versus change in input voltage (V DD). Thus:
∂ l COMP G m = -----------------∂ V DD
The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as:
∂ CO MP 1 ∂ COMP Z CO MP = -------------------- = ------- × -----------------------I Gm ∂ V DD ∂ COMP
V V
This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: AVOL = Gm x ZCOMP where Gm value for VIPer50-E is 1.5 mA/V typically. Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z can be connected between the COMP pin and ground in order to define the transfer function F of the error amplifier more accurately, according to the following equation (very similar to the one above): F(S) = Gm x Z(S) The error amplifier frequency response is reported in Figure 10. for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 330KΩ. More complex impedance can be connected on the COMP pin to achieve different compensation level. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. This configuration is illustrated in Figure 20 As shown in Figure 19 an additional noise filtering capacitor of 2.2nF is generally needed to avoid any high frequency interference. Is also possible to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth.
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5 Operation Description
VIPer50-E
5.5
External Clock Synchronization:
The OSC pin provides a synchronisation capability when connected to an external frequency source. Figure 21 shows one possible schematic to be adapted, depending the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor.
5.6
Primary Peak Current Limitation
The primary IDPEAK current and, consequently, the output power can be limited using the simple circuit shown in Figure 22 . The circuit based on Q1, R1 and R2 clamps the voltage on the COMP pin in order to limit the primary peak current of the device to a value:
V COMP – 0.5 I D PEAK = ------------------------------H ID
where:
R1 + R 2 V COMP = 0.6 × -----------------R2
The suggested value for R1+R2 is in the range of 220KΩ.
5.7
Over-Temperature Protection
Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at which over-temperature cut-out occurs is 140ºC, while the typical value is 170ºC. The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 13)
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VIPer50-E
5 Operation Description
5.8
Operation Pictures
VDD R egulation Point Figure 6. Undervoltage Lockout
Figure 5.
ICOMP
ICOMPHI
Slope = Gmin m A/V
IDD
IDD0
VDD
0 ICOMPLO VDDreg
FC00150
VDDhyst VDDoff IDDch
VD S= 35 V Fsw = 0
VDDon VD D
FC00170
Figure 7.
Transition Time
Figure 8.
Shutdown Action
VOSC
ID
VCOMP tDISsu
t
10% Ipeak t
VDS
90% VD
V COMPth
t
ID
10% VD t tf tr
FC00160
t
ENABLE
ENABLE DISABLE
FC00060
Figure 9.
Breakdown Voltage vs. Temperature Figure 10. Typical Frequency Variation
1.15
FC00180
FC00190
BVDSS
(Normalized)
(%)
1 0
1.1
-1
1.05
-2 -3
1
-4 -5
0 20 40 60 80 100 120 Temperature (°C)
0.95
0
20
40 60 80 100 120 140 Temperature (°C)
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5 Operation Description
VIPer50-E
Figure 11. Behaviour of the high voltage current source at start-up
VDD VDDon VDDoff
2 mA 15 mA
CVDD
VDD
1 mA 15 mA
3 mA
DRAIN
Ref. t Auxiliary primary winding UNDERVOLTAGE LOCK OUT LOGIC
VIPer50
SOURCE
Start up duty cycle ~ 12%
FC00320
Figure 12. Start-Up Waveforms
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Figure 13. Over-temperature Protection
VIPer50-E
T T ts c J
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SC 1 0 1 9 1
T t s d -T h y s t
V dd on V dd off
V
co m p
Vdd
Id
t
t
t
t
5 Operation Description
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5 Operation Description
VIPer50-E
Figure 14. Oscillator
For R t > 1.2kΩ and Ct ≤ 40KHz
550 2.3 F SW = ---------- ⋅ 1 – ------------------R t – 150 RtCt
CLK Ct ~360Ω
⎝ ⎛
Rt O SC
VDD
FC 00050
Ct
Forbidden area
880 Ct(nF) = 22nF 15nF Fsw(kHz)
Forbidden area
40kHz
Fsw
FC00030
Oscillator frequency vs Rt and Ct
1,000
Ct = 1.5 nF
500
Ct = 2.7 nF
Frequency (kHz)
300 200
Ct = 4.7 nF
Ct = 10 nF
100
50 30
1
2
3
5
10
20
30
50
Rt (kΩ)
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⎠ ⎞
VIPer50-E
Figure 15. Error Amplifier frequency Response
FC00200
5 Operation Description
60
RCOMP = +∞ RCOMP = 270k
Voltage Gain (dB)
40
RCOMP = 82k RCOMP = 27k
20
RCOMP = 12k
0
(20) 0.001
0.01
0.1 1 10 Frequency (kHz)
100
1,000
Figure 16. Error Amplifier Phase Response
FC00210
200
RCOMP = +∞
150 Phase (°) 100 50 0 (50) 0.001
RCOMP = 270k RCOMP = 82k RCOMP = 27k RCOMP = 12k
0.01
0.1 1 10 Frequency (kHz)
100
1,000
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5 Operation Description
VIPer50-E
Figure 17. Mixed Soft Start and Compensation Figure 18. Latched Shut Down
D2
VIPer50
VDD DRAIN
D3
R1
VDD
VIPer50
DRAIN
OSC 13V
+
COMP SOURCE
R3 D1
Q2
OSC
13V
+
COMP SOURCE
AUXILIARY WINDING R2
R3
R2
C4
R1
R4
Shutdown
+ C3
C1
+ C2
Q1
D1
FC00331
FC00340
Figure 19. Typical Compensation Network
VIPer50
VDD OSC 13V DRAIN
Figure 20. Slope Compensation
+
COMP SOURCE
R2
R1 VIPer5 0
VD D D RAIN
OS C 13V
+
C OM P SO UR CE
C2
R1 C1
C1 Q1
C2
C3
R3
FC00351
Figure 21. External Clock Sinchronisation
FC 00361
Figure 22. Current Limitation Circuit Example
VIPer50
VDD DRAIN
VIPer50
VDD DRAIN
OSC 13V
+
COMP SOURCE
OSC
13V
+
COMP SOURCE
10 kΩ
R1 Q1 R2
FC00370
FC00380
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VIPer50-E
6 Electrical Over Stress
6
6.1
Electrical Over Stress
Electrical Over Stress Ruggedness
The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages most of the time. However in some cases, the voltage surges coupled through the transformer auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events may trigger the VDD internal protection circuitry which could be damaged by the strong discharge current of the VDD bulk capacitor. The simple RC filter shown in Figure 23 can be implemented to improve the application immunity to such surges.
Figure 23. Input Voltage Surges Protection
R1 (Optional) R2 39R D1
Auxilliary winding
C2 22nF
OSC 13V VIPerXX0
VDD
+
DRAIN
C1 Bulk capacitor
COMP SOURCE
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7 Layout
VIPer50-E
7
7.1
Layout
Layout Considerations
Some simple rules insure a correct running of switching power supplies. They may be classified into two categories: – Minimizing power loops: The switched power current must be carefully analysed and the corresponding paths must be as small an inner loop area as possible. This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. Using different tracks for low level and power signals: Interference due to mixing of signal and power may result in instabilities and/or anomalous behaviour of the device in case of violent power surge (Input overvoltages, output short circuits...). Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized. C6 must be as close as possible to T1. Signal components C2, ISO1, C3, and C4 are using a dedicated track connected directly to the power source of the device.
–
In case of VIPer, these rules apply as shown on (see Figure 24). – – –
Figure 24. Recommended Layout
T1
D1
D2
C7
To secondary filtering and load
R1
VDD DRAIN
C1
OSC
13V + COMP SOURCE
C5
From input diodes bridge
U1 VIPerXX0 R2 C2 C3 ISO1 C4 C6
FC00500
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VIPer50-E
8 Package Mechanical Data
8
Package Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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8 Package Mechanical Data
VIPer50-E
Pentawatt HV Mechanical Data
mm. Dim Min. Typ. Maw. Min. Typ. Max. inch
A C D E F G1 G2 H1 H2 H3 L L1 L2 L3 L5 L6 L7 M M1 R V4 Diam
4.30 1.17 2.40 0.35 0.60 4.91 7.49 9.30
4.80 1.37 2.80 0.55 0.80 5.21 7.80 9.70 10.40
0.169 0.046 0.094 0.014 0.024 0.193 0.295 0.366
0.189 0.054 0.11 0.022 0.031 0.205 0.307 0.382 0.409 0.396 0.409 0.681 0.599 0.860 0.898 0.118 0.622 0.260 0.122 0.220
10.05 15.60 14.60 21.20 22.20 2.60 15.10 6 2.50 4.50 0.50
10.40 17.30 15.22 21.85 22.82 3 15.80 6.60 3.10 5.60 6.14 0.575 0.835 0.874 0.102 0.594 0.236 0.098 0.177 0.02 90°
3.65
3.85
0.144
0.152
P023H3
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VIPer50-E
8 Package Mechanical Data
Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data
mm. Dim Min. Typ. Maw. Min. Typ. Max. inch
A C D E F G1 G2 H1 H2 H3 L L1 L3 L5 L6 L7 M M1 R V4 Diam
4.30 1.17 2.40 0.35 0.60 4.91 7.49 9.30
4.80 1.37 2.80 0.55 0.80 5.21 7.80 9.70 10.40
0.169 0.046 0.094 0.014 0.024 0.193 0.295 0.366
0.189 0.054 0.110 0.022 0.031 0.205 0.307 0.382 0.409
10.05 16.42 14.60 20.52 2.60 15.10 6.00 2.50 5.00 0.50 90° 3.65
10.40 17.42 15.22 21.52 3.00 15.80 6.60 3.10 5.70
0.396 0.646 0.575 0.808 0.102 0.594 0.236 0.098 0.197 0.02 0.020 90°
0.409 0.686 0.599 0.847 0.118 0.622 0.260 0.122 0.224
3.85
0.144
0.154
L L1
E
M1 G2 G1
A
M D C R
Resin between leads
L6 L7
V4 H1 H3 H2 F DIA L3 L5
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8 Package Mechanical Data
VIPer50-E
Figure 25. Pentawatt HV Tube Shipment ( no suffix )
Base Q.ty Bulk Q.ty Tube length ( ± 0.5 ) A B C ( ± 0.1)
50 1000 532 18 33.1 1
All dimensions are in mm.
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VIPer50-E
9 Order Codes
9
Order Codes
PENTAWATT HV PENTAWATT HV (022Y)
VIPer50-E
VIPer50-22-E
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10 Revision history
VIPer50-E
10
Revision history
Date Revision Changes
26-Sep-2005
1
Initial release.
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VIPer50-E
10 Revision history
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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