VN7003AH
High-side driver with CurrentSense analog feedback for
automotive applications
Datasheet - production data
Applications
Features
Max transient supply voltage
VCC
40 V
Operating voltage range
VCC
4 to
28 V
Typ. on-state resistance (per
Ch)
RON
3.5 mΩ
Current limitation (typ)
ILIMH
135 A
Stand-by current (max)
ISTBY
0.5 µA
VUSD_Cranking
3V
Minimum cranking supply
voltage (VCC decreasing)
AEC-Q100 qualified
Extreme low voltage operation for deep cold
cranking applications (compliant with LV124,
revision 2013)
General
Single channel smart high-side driver
with CurrentSense analog feedback
Very low standby current
Compatible with 3 V and 5 V CMOS
outputs
Diagnostic functions
Overload and short to ground (power
limitation) indication
Thermal shutdown indication
OFF-state open-load detection
Output short to VCC detection
Sense enable/ disable
November 2016
Protections
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Loss of ground and loss of VCC
Reverse battery
Electrostatic discharge protection
Specially intended for Automotive smart power
distribution, glow plugs, heating systems, DC
motors, relay replacement and high power
resistive and inductive actuators.
Description
The device is a single channel high-side driver
manufactured using ST proprietary VIPower®
technology and housed in the Octapak package.
The device is designed to drive 12 V automotive
grounded loads through a 3 V and 5 V CMOScompatible interface, providing protection and
diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
Table 1: Device summary
Package
Octapak
DocID029238 Rev 4
This is information on a product in full production.
Order codes
Tape and reel
VN7003AHTR
1/37
www.st.com
Contents
VN7003AH
Contents
1
Block diagram and pin description ................................................ 5
2
Electrical specification .................................................................... 7
3
4
2.1
Absolute maximum ratings ................................................................ 7
2.2
Thermal data ..................................................................................... 8
2.3
Electrical characteristics .................................................................... 8
2.4
Electrical characteristics curves ...................................................... 16
Protections..................................................................................... 20
3.1
Power limitation ............................................................................... 20
3.2
Thermal shutdown ........................................................................... 20
3.3
Current limitation ............................................................................. 20
3.4
Negative voltage clamp ................................................................... 20
Application information ................................................................ 21
4.1
Protection against reverse battery................................................... 21
4.2
Immunity against transient electrical disturbances .......................... 22
4.3
MCU I/Os protection ........................................................................ 22
4.4
CS - analog current sense .............................................................. 23
4.4.1
Principle of CurrentSense signal generation .................................... 24
4.4.2
Short to VCC and OFF-state open-load detection ........................... 26
5
Maximum demagnetization energy (VCC = 16 V) ........................ 28
6
Package and PCB thermal data .................................................... 29
6.1
7
8
2/37
Octapak thermal data ...................................................................... 29
Package information ..................................................................... 32
7.1
Octapak package information.......................................................... 32
7.2
Octapak packing information ........................................................... 33
7.3
Octapak marking information .......................................................... 35
Revision history ............................................................................ 36
DocID029238 Rev 4
VN7003AH
List of tables
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pin functions ................................................................................................................................. 5
Table 3: Suggested connections for unused and not connected pins ........................................................ 6
Table 4: Absolute maximum ratings ........................................................................................................... 7
Table 5: Thermal data ................................................................................................................................. 8
Table 6: Electrical characteristics during cranking ..................................................................................... 8
Table 7: Power section ............................................................................................................................... 9
Table 8: Switching..................................................................................................................................... 10
Table 9: Logic inputs ................................................................................................................................. 10
Table 10: Protection .................................................................................................................................. 11
Table 11: CurrentSense ............................................................................................................................ 11
Table 12: Truth table ................................................................................................................................. 15
Table 13: ISO 7637-2 - electrical transient conduction along supply line ................................................. 22
Table 14: CurrentSense pin levels in off-state .......................................................................................... 26
Table 15: PCB properties ......................................................................................................................... 29
Table 16: Thermal parameters ................................................................................................................. 31
Table 17: Octapak mechanical data ......................................................................................................... 32
Table 18: Reel dimensions ....................................................................................................................... 34
Table 19: Document revision history ........................................................................................................ 36
DocID029238 Rev 4
3/37
List of figures
VN7003AH
List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Configuration diagram (top view)................................................................................................. 6
Figure 3: Current and voltage conventions ................................................................................................. 7
Figure 4: IOUT/ISENSE versus IOUT ....................................................................................................... 13
Figure 5: Current sense precision vs. IOUT ............................................................................................. 14
Figure 6: Switching times and Pulse skew ............................................................................................... 14
Figure 7: tDSTKON ................................................................................................................................... 15
Figure 8: OFF-state output current ........................................................................................................... 16
Figure 9: Standby current ......................................................................................................................... 16
Figure 10: IGND(ON) vs. Iout ................................................................................................................... 16
Figure 11: Logic input high level voltage .................................................................................................. 16
Figure 12: Logic input low level voltage .................................................................................................... 16
Figure 13: High level logic input current ................................................................................................... 16
Figure 14: Low level logic input current .................................................................................................... 17
Figure 15: Logic input hysteresis voltage ................................................................................................. 17
Figure 16: Undervoltage shutdown ........................................................................................................... 17
Figure 17: On-state resistance vs. Tcase ................................................................................................. 17
Figure 18: On-state resistance vs. VCC ................................................................................................... 17
Figure 19: Turn-on voltage slope .............................................................................................................. 17
Figure 20: Turn-off voltage slope .............................................................................................................. 18
Figure 21: Won vs. Tcase ......................................................................................................................... 18
Figure 22: Woff vs. Tcase ......................................................................................................................... 18
Figure 23: ILIMH vs. Tcase ....................................................................................................................... 18
Figure 24: Turn-off output voltage clamp .................................................................................................. 18
Figure 25: OFF-state open-load voltage detection threshold ................................................................... 18
Figure 26: Vs clamp vs. Tcase ................................................................................................................. 19
Figure 27: Vsenseh vs. Tcase .................................................................................................................. 19
Figure 28: Application diagram ................................................................................................................. 21
Figure 29: Simplified internal structure ..................................................................................................... 21
Figure 30: CurrentSense and diagnostic – block diagram........................................................................ 23
Figure 31: CurrentSense block diagram ................................................................................................... 24
Figure 32: Analogue HSD – open-load detection in off-state ................................................................... 25
Figure 33: Open-load / short to VCC condition ......................................................................................... 26
Figure 34: Maximum turn off current versus inductance .......................................................................... 28
Figure 35: Octapak on two-layers PCB (2s0p to JEDEC JESD 51-5) ...................................................... 29
Figure 36: Octapak on four-layers PCB (2s2p to JEDEC JESD 51-7) ..................................................... 29
Figure 37: Rthj-amb vs PCB copper area in open box free air conditions ............................................... 30
Figure 38: Octapak thermal impedance junction ambient single pulse .................................................... 30
Figure 39: Thermal fitting model for Octapak ........................................................................................... 31
Figure 40: Octapak package dimensions ................................................................................................. 32
Figure 41: Octapack reel 13" .................................................................................................................... 33
Figure 42: Octapak carrier tape ................................................................................................................ 34
Figure 43: Octapak schematic drawing of leader and trailer tape ............................................................ 35
Figure 44: Octapak marking information................................................................................................... 35
4/37
DocID029238 Rev 4
VN7003AH
1
Block diagram and pin description
Block diagram and pin description
Figure 1: Block diagram
V CC
Reverse
Battery
Protection
Signal Clamp
Undervoltage
IN
Control & Diagnostic
Power
Clamp
DRIVER
Over
temperature
Current
Limitation
OFF State
Open load
SEn
V SENSEH
CS
Current
Sense
LOGIC
OUT
OVERLOAD PROTECTION
( ACTIVE POWER LIMI TATION )
GND
Table 2: Pin functions
Name
VCC
OUTPUT
GND
INPUT
Function
Battery connection.
Power outputs. all the pins must be connected together.
Ground connection.
Voltage controlled input pin with hysteresis. Compatible with 3 V and 5 V CMOS outputs.
It controls output switch state.
CS
Analog current sense output pin delivers a current proportional to the load current.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the CurrentSense
diagnostic pin.
DocID029238 Rev 4
5/37
Block diagram and pin description
VN7003AH
Figure 2: Configuration diagram (top view)
Table 3: Suggested connections for unused and not connected pins
Connection /
pin
CurrentSense
N.C.
Output
Input
SEn
Floating
Not allowed
X (1)
X
X
X
To ground
Through 1 kΩ
resistor
X
Not
allowed
Through 15 kΩ
resistor
Through 15 kΩ
resistor
Notes:
(1)X:
6/37
do not care.
DocID029238 Rev 4
VN7003AH
2
Electrical specification
Electrical specification
Figure 3: Current and voltage conventions
VF = VOUT - VCC when VOUT > VCC and INPUT = LOW
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 4: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 4: Absolute maximum ratings
Symbol
VCC
Parameter
Value
DC supply voltage
38
VCCPK
Maximum transient supply voltage (ISO7637-2:2004 Pulse 5b level
IV clamped to 40 V; RL = 4Ω)
40
Unit
V
-VCC
Reverse DC supply voltage
16
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT DC output current
Internally
limited
A
-IOUT
Reverse DC output current
38
IIN
INPUT DC input current
ISEn
SEn DC input current
ISENSE
EMAX
-1 to 10
CS pin DC output current (VGND = VCC and VSENSE < 0 V)
10
CS pin DC output current in reverse (VCC < 0 V)
-20
Maximum switching energy (single pulse)
TDEMAG = 0.4 ms; Tjstart = 150°C
TBD
DocID029238 Rev 4
mA
mA
mJ
7/37
Electrical specification
VN7003AH
Symbol
Parameter
Value
Unit
VESD
Electrostatic discharge (JEDEC 22A-114F)
INPUT
CurrentSense
SEn
OUTPUT
VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Tstg
2.2
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
°C
Thermal data
Table 5: Thermal data
Symbol
Parameter
Typ. value
Rthj-board
Thermal resistance junction-board (1)
2.1
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5) (2)
57.9
Rthj-amb
(1)
15.4
Thermal resistance junction-ambient (JEDEC JESD 51-7)
Unit
°C/W
Notes:
2.3
(1)Device
mounted on four-layers 2s2p PCB
(2)Device
mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
Electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified.
Table 6: Electrical characteristics during cranking
Symbol
VUSD_Cranking
RON
TTSD(1)
Parameter
Test conditions
Min.
Minimum cranking supply
voltage (VCC decreasing)
On-state resistance
IOUT = 4 A; VCC = 3 V;
VCC decreasing
Shutdown temperature (VCC
decreasing)
VCC = 3 V
140
Notes:
(1)Parameter
8/37
guaranteed by design and characterization; not subject to production test.
DocID029238 Rev 4
Typ.
Max.
Unit
—
3
V
—
15
mΩ
—
°C
VN7003AH
Electrical specification
Table 7: Power section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
4
13
28
V
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
3
V
VUSDReset
Undervoltage shutdown
reset
5
V
VUSDhyst
Undervoltage shutdown
hysteresis
0.3
IOUT = 15 A; Tj = 25°C
RON
RON_Rev
Vclamp
ISTBY
tD_STBY
IS(ON)
IGND(ON)
IL(off)
VF
On-state resistance
RDSON in reverse battery
condition
Clamp voltage
Supply current in standby
at VCC = 13 V (1)
7
IOUT = 15 A; VCC = 4 V;
Tj = 25°C
5.25
VCC = -13 V; IOUT = -15 A;
Tj = 25°C
38
IS = 20 mA; 25°C < Tj < 150°C
41
46
mΩ
mΩ
3.5
IS = 20 mA; Tj = -40°C
52
V
VCC = 13 V;
VIN = VOUT = VSEn = 0 V;
Tj = 25°C
0.5
µA
VCC = 13 V;
VIN = VOUT = VSEn = 0 V;
Tj = 85°C (2)
1.4
µA
VCC = 13 V;
VIN = VOUT = VSEn = 0 V;
Tj = 125°C
11
µA
300
550
µs
4
6.5
mA
9
mA
VCC = 13 V; VIN = 5 V;
VSEn = 0 V; IOUT = 0 A
Supply current
VCC = 13 V; VSEn = 0 V;
VIN = 5 V; IOUT = 0 A
Control stage current
consumption in ON-state.
All channels active.
VCC = 13 V; VSEn = 5 V;
VIN = 5 V; IOUT = 15 A
Output - VCC diode voltage
3.5
IOUT = 15 A; Tj = 150°C
Standby mode blanking
time
Off-state output current at
VCC = 13 V
V
60
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25°C
0
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C
0
IOUT = -15 A; Tj = 150°C
0.01
0.5
µA
11
0.7
V
Notes:
(1)PowerMOS
(2)Parameter
leakage included.
specified by design; not subject to production test.
DocID029238 Rev 4
9/37
Electrical specification
VN7003AH
Table 8: Switching
VCC = 13 V; -40 ºC < Tj < 150 °C, unless otherwise specified
Symbol
Test
conditions
Parameter
td(on)(1)
Turn-on delay time at Tj = 25 °C
td(off)(1)
Turn-off delay time at Tj = 25 °C
(dVOUT/dt)on(1)
Turn-on voltage slope at Tj = 25 °C
(1)
Turn-off voltage slope at Tj = 25 °C
(dVOUT/dt)off
Min.
Typ.
Max.
10
50
120
10
60
100
0.075
0.28
0.7
0.075
0.33
0.7
RL = 0.87 Ω
RL = 0.87 Ω
Unit
µs
V/µs
WON
Switching energy losses at turn-on
(twon)
RL = 0.87 Ω
—
1.8
3.6(2)
mJ
WOFF
Switching energy losses at turn-off
(twoff)
RL = 0.87 Ω
—
2
3.6(2)
mJ
Differential Pulse skew
(tPHL - tPLH)
RL = 0.87 Ω
-50
0
50
µs
tSKEW (1)
Notes:
(1)See Figure 6: "Switching times and Pulse skew"
(2)Parameter
guaranteed by design and characterization; not subject to production test.
Table 9: Logic inputs
7 V < VCC < 28 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0.9
V
INPUT characteristics
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
5.3
IIN = -1 mA
µA
7.5
-0.7
V
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
VSEn(hyst)
Input hysteresis voltage
VSEnCL
10/37
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
IIN = -1 mA
DocID029238 Rev 4
V
µA
V
5.3
7.5
-0.7
V
VN7003AH
Electrical specification
Table 10: Protection
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
ILIMH(1)
DC short circuit current
ILIML
Short circuit current
during thermal cycling
TTSD
Shutdown temperature
4 V < VCC < 18 V
Reset
TRS
Thermal reset of fault
diagnostic indication
Thermal hysteresis
(TTSD - TR)(2)
ΔTJ_SD
Dynamic temperature
Max.
80
135
175
175
VCC = 13 V;
TR < Tj < TTSD
VSEn = 5 V
THYST
Typ.
(2)
temperature(2)
TR
VDEMAG
VCC = 13 V
Min.
A
38
150
175
TRS + 1
TRS + 7
200
IOUT = 2 A; L = 6 mH;
Tj = -40°C
VCC 38
IOUT = 2 A; L = 6 mH;
Tj = 25°C to 150°C
VCC 41
°C
°C
135
VCC = 13 V
Turn-off output voltage
clamp
Unit
°C
7
°C
60
K
V
VCC 46
VCC 52
V
Typ.
Max.
Unit
-12
V
Notes:
(1)Parameter
guaranteed by an indirect test sequence.
(2)Parameter
guaranteed by design and characterization; not subject to production test.
Table 11: CurrentSense
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
VSENSE_CL
Parameter
Test conditions
CurrentSense clamp
voltage
VSEn = 0 V; ISENSE = 1 mA
Min.
-17
VSEn = 0 V; ISENSE = -1 mA
7
V
Current Sense characteristics
KOL(1)
IOUT/ISENSE
IOUT = 200 mA;
VSENSE = 0.5 V;
VSEn = 5 V
8350
16800
25150
K0
IOUT/ISENSE
IOUT = 1 A; VSENSE = 0.5 V;
VSEn = 5 V
9000
16650
24500
Current sense ratio drift
IOUT = 1 A; VSENSE = 0.5 V;
VSEn = 5 V
-30
IOUT/ISENSE
IOUT = 10 A; VSENSE = 4 V;
VSEn = 5 V
13150
Current sense ratio drift
IOUT = 10 A; VSENSE = 4 V;
VSEn = 5 V
-10
IOUT/ISENSE
IOUT = 15 A; VSENSE = 4 V;
VSEn = 5 V
14200
Current sense ratio drift
IOUT = 15 A; VSENSE = 4 V;
VSEn = 5 V
-7
dK0/K0(2)(3)
K1
dK1/K1(2)(3)
K2
dK2/K2(2)(3)
DocID029238 Rev 4
30
16450
19750
10
16450
%
%
19100
7
%
11/37
Electrical specification
VN7003AH
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
K3
dK3/K3(2)(3)
ISENSE0
Parameter
Test conditions
Min.
Typ.
Max.
16450
18670
Unit
IOUT/ISENSE
IOUT = 45 A; VSENSE = 4 V;
VSEn = 5 V
14760
Current sense ratio drift
IOUT = 45 A; VSENSE = 4 V;
VSEn = 5 V
-5
5
%
CurrentSense disabled:
VSEn = 0 V;
0
0.5
µA
CurrentSense disabled;
-1 V < VSENSE < 5 V(3)
-0.5
0.5
µA
CurrentSense enabled:
VSEn = 5 V; VIN = 5 V;
IOUT = 0 A;
0
5
µA
CurrentSense leakage
current
VOUT_CSD(3)
Output voltage for
CurrentSense
shutdown
VSEn = 5 V;
RSENSE = 2.7 kΩ; VIN = 5 V;
IOUT = 15 A
VSENSE_SAT
CurrentSense
saturation voltage
VCC = 7 V; RSENSE = 10 kΩ;
VSEn = 5 V; VIN = 5 V;
IOUT = 15 A; Tj = -40°C
5
V
ISENSE_SAT(3)
CS saturation current
VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V; Tj = 40°C
4
mA
Output saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V; Tj = 40°C
75
A
IOUT_SAT(3)
5
V
OFF-state diagnostic
VOL
OFF-state open-load
voltage detection
threshold
VIN = 0 V; VSEn = 5 V;
2
IL(off2)
OFF-state output sink
current
VIN = 0 V; VOUT = VOL;
Tj = -40°C to 125°C
-100
tDSTKON
OFF-state diagnostic
delay time from falling
edge of INPUT (see
Figure 7: "tDSTKON")
VIN = 5 V to 0 V;
VSEn = 5 V; IOUT = 0 A;
VOUT = 4 V
100
tD_OL_V
Settling time for valid
OFF-state open load
diagnostic indication
from rising edge of SEn
VIN = 0 V; VOUT = 4 V;
VSEn = 0 V to 5 V
tD_VOL
OFF-state diagnostic
delay time from rising
edge of VOUT
VIN = 0 V; VSEn = 5 V;
VOUT = 0 V to 4 V
3
350
5
4
V
-15
µA
700
µs
60
µs
30
µs
6.6
V
30
mA
Fault diagnostic feedback (see Table 12: "Truth table")
12/37
VSENSEH
CurrentSense output
voltage in fault
condition
VCC = 13 V; VIN = 0 V;
VSEn = 5 V; IOUT = 0 A;
VOUT = 4 V; RSENSE = 1 kΩ
5
ISENSEH
CurrentSense output
current in fault
condition
VCC = 13 V; VSENSE = 5 V
7
DocID029238 Rev 4
20
VN7003AH
Electrical specification
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
60
µs
5
20
µs
100
380
µs
200
µs
250
µs
CurrentSense timings (current sense mode)(4)
tDSENSE1H
Current sense settling
time from rising edge of
SEn
VIN = 5 V; VSEn = 0 V to
5 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
tDSENSE1L
Current sense disable
delay time from falling
edge of SEn
VIN = 5 V; VSEn = 5 V to
0 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
tDSENSE2H
Current sense settling
time from rising edge of
INPUT
VIN = 0 V to 5 V;
VSEn = 5 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
ΔtDSENSE2H
Current sense settling
time from rising edge of
IOUT (dynamic response
to a step change of
IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; ISENSE
= 90% of ISENSEMAX;
RL = 0.87 Ω
Current sense turn-off
delay time from falling
edge of INPUT
VIN = 5 V to 0 V; VSEn = 5
V; RSENSE = 1 kΩ;
RL = 0.87 Ω
tDSENSE2L
50
Notes:
(1)Digital
(2)All
filtering is applied for testing
values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
(3)Parameter
(4)Transition
guaranteed by design and characterization; not subject to production test.
delay are measured up to ±10% of final conditions.
Figure 4: IOUT/ISENSE versus IOUT
DocID029238 Rev 4
13/37
Electrical specification
VN7003AH
Figure 5: Current sense precision vs. IOUT
Figure 6: Switching times and Pulse skew
14/37
DocID029238 Rev 4
VN7003AH
Electrical specification
Figure 7: tDSTKON
Table 12: Truth table
Mode
Conditions
Stand by
All logic inputs
low
Normal
Nominal load
connected;
Tj < 150°C
Overload
Overload or
short to GND
causing:
Tj > TTSD or
ΔTj > ΔTj_SD
Undervoltage
OFF-state
diagnostics
Negative
output
voltage
INX
SEn
OUTX
Current Sense
L
L
L
Hi-Z
L
H
L
0
H
L
H
Hi-Z
H
H
H
ISENSE = 1/K * IOUT
H
L
H
Hi-Z
H
H
H
VSENSEH
VCC < VUSD
(falling)
X
X
L
L
Hi-Z
Hi-Z
Short to VCC
L
H
H
Open-load
L
H
H
Inductive loads
turn-off
L
X
VUSD + VUSDhyst
(rising)
External pull-up
0
15/37
Electrical specification
2.4
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Electrical characteristics curves
Figure 8: OFF-state output current
Figure 9: Standby current
Figure 10: IGND(ON) vs. Iout
Figure 11: Logic input high level voltage
Figure 12: Logic input low level voltage
Figure 13: High level logic input current
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Electrical specification
Figure 14: Low level logic input current
Figure 15: Logic input hysteresis voltage
Figure 16: Undervoltage shutdown
Figure 17: On-state resistance vs. Tcase
Figure 18: On-state resistance vs. VCC
Figure 19: Turn-on voltage slope
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Electrical specification
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VN7003AH
Figure 20: Turn-off voltage slope
Figure 21: Won vs. Tcase
Figure 22: Woff vs. Tcase
Figure 23: ILIMH vs. Tcase
Figure 24: Turn-off output voltage clamp
Figure 25: OFF-state open-load voltage
detection threshold
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Electrical specification
Figure 26: Vs clamp vs. Tcase
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Figure 27: Vsenseh vs. Tcase
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Protections
VN7003AH
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of ΔTj_SD. The protection prevents fast thermal
transient effects and, consequently, reduces thermo-mechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered. The
device switches on again as soon as its junction temperature drops to T R.
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
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4
Application information
Application information
Figure 28: Application diagram
4.1
Protection against reverse battery
Figure 29: Simplified internal structure
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Application information
VN7003AH
The device does not need any external components to protect the internal logic in case of a
reverse battery condition. The protection is provided by internal structures.
In addition, due to the fact that the output MOSFET turns on even in reverse battery mode,
thus providing the same low ohmic path as in regular operating conditions, no additional
power dissipation has to be considered.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 13: "ISO 7637-2 electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 13: ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional
performance status
Minimum
number of
pulses or test
time
Burst cycle /
pulse repetition
time
Pulse duration and
pulse generator
internal impedance
Level
US(1)
1
III
-112V
500 pulses
0,5 s
2a
III
+55V
500 pulses
0,2 s
5s
50μs, 2Ω
3a
IV
-220V
1h
90 ms
100 ms
0.1μs, 50Ω
3b
IV
+150V
1h
90 ms
100 ms
0.1μs, 50Ω
4(2)
IV
-7V
1 pulse
min
max
2ms, 10Ω
100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test
B(3)
40V
5 pulse
1 min
400ms, 2Ω
Notes:
(1)U
S
4.3
is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test
pulse from ISO 7637-2:2004(E).
(3)With
40 V external suppressor referred to ground (-40°C < Tj < 150°C).
MCU I/Os protection
If a ground protection network is used and negative transients are present on the V CC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins from latch-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
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Application information
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
CS - analog current sense
Diagnostic information on device and load status are provided by an analog output pin (CS)
delivering the following signal:
Current monitor: current minitor of channel output current
Figure 30: CurrentSense and diagnostic – block diagram
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Application information
4.4.1
VN7003AH
Principle of CurrentSense signal generation
Figure 31: CurrentSense block diagram
Current sense
This output is capable of providing:
Current mirror proportional to the load current in normal operation, delivering current
proportional to the load according to known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage V SENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can
be done using simple equations
Current provided by CurrentSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE * ISENSE = RSENSE * IOUT/K
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Application information
Where :
VSENSE is voltage measurable on RSENSE resistor
ISENSE is current provided from CS pin in current output mode
IOUT is current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between I OUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the CS pin which is
switched to a “current limited” voltage source, VSENSEH .
In any case, the current sourced by the CS in this condition is limited to I SENSEH
Figure 32: Analogue HSD – open-load detection in off-state
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Application information
VN7003AH
Figure 33: Open-load / short to VCC condition
Table 14: CurrentSense pin levels in off-state
Condition
Output
CurrentSense
SEn
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
VOUT > VOL
Open-load
VOUT < VOL
Short to VCC
Nominal
4.4.2
VOUT > VOL
VOUT < VOL
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
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Application information
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
Equation
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Maximum demagnetization energy (VCC = 16 V)
5
Maximum demagnetization energy (VCC = 16 V)
Figure 34: Maximum turn off current versus inductance
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Package and PCB thermal data
6
Package and PCB thermal data
6.1
Octapak thermal data
Figure 35: Octapak on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 36: Octapak on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 15: PCB properties
Dimension
Value
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board Material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on vias
0.025 mm
Footprint dimension (top layer)
6.4 mm x 7mm
Heatsink copper area dimension (bottom layer)
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Footprint, 2 cm2 or 8 cm2
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Package and PCB thermal data
VN7003AH
Figure 37: Rthj-amb vs PCB copper area in open box free air conditions
Figure 38: Octapak thermal impedance junction ambient single pulse
Equation: Pulse calculation formula
ZTHδ = RTH · + ZTHtp (1 - δ)
where δ = tP/T
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Package and PCB thermal data
Figure 39: Thermal fitting model for Octapak
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
Table 16: Thermal parameters
Area/island (cm²)
Footprint
2
8
4L
R1 (°C/W)
0.01
0.01
0.01
0.01
R2 (°C/W)
0.5
0.5
0.5
0.5
R3 (°C/W)
1.6
1.6
1.6
1.6
R4 (°C/W)
10
10
10
2.5
R5 (°C/W)
28
20
12
5
R6 (°C/W)
36
26
18
6
C1 (W.s/°C)
0.001
0.001
0.001
0.001
C2 (W.s/°C)
0.0018
0.0018
0.0018
0.0018
C3 (W.s/°C)
0.11
0.11
0.11
0.11
C4 (W.s/°C)
0.6
0.6
0.6
0.8
C5 (W.s/°C)
0.8
1.4
2.2
3
C6 (W.s/°C)
3
6
9
25
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Package information
7
VN7003AH
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
Octapak package information
Figure 40: Octapak package dimensions
Table 17: Octapak mechanical data
Millimeters
Symbol
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Min.
Typ.
Max.
A
2.20
2.30
2.40
A1
0.90
1.00
1.10
A2
0.03
b
0.38
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0.45
0.52
VN7003AH
Package information
Millimeters
Symbol
Min.
Typ.
b1
0.70
b4
5.20
5.30
5.40
c
0.45
0.50
0.60
c2
0.75
0.80
0.90
D
6.00
6.10
6.20
D1
E
5.15
6.40
E1
6.50
6.60
5.30
e
0.85 BSC
e1
1.60
1.70
1.80
e2
3.30
3.40
3.50
e3
5.00
5.10
5.20
H
9.35
9.70
10.10
L
1.00
—
(L1)
2.80
L2
0.80
L3
0.85
R
V2
7.2
Max.
0.40 BSC
0°
8°
Octapak packing information
Figure 41: Octapack reel 13"
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Package information
VN7003AH
Table 18: Reel dimensions
Description
Value(1)
Base quantity
2500
Bulk quantity
2500
A (max)
330
B (min)
1.5
C (+0.5, -0.2)
13
D
20.2
N
100
W1 (+2 /-0)
16.4
W2 (max)
22.4
Notes:
(1)All
dimensions are in mm.
Figure 42: Octapak carrier tape
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Package information
Figure 43: Octapak schematic drawing of leader and trailer tape
7.3
Octapak marking information
Figure 44: Octapak marking information
Parts marked as "&" are not yet qualified and therefore not yet ready to be used in
production and any consequences deriving from such usage will not be at ST charge. In no
event, ST will be liable for any customer usage of these engineering samples in production.
ST Quality has to be contacted prior to any decision to use these Engineering Samples to
run qualification activity.
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Revision history
8
VN7003AH
Revision history
Table 19: Document revision history
Date
Revision
15-Apr-2016
1
Changes
Initial release
Doc status upgraded to production data
Section "Features"
added AEC-Q100 qualification
ILIMH: updated current limitation feature
Figure 1: "Block diagram"
updated figure
Table 4: "Absolute maximum ratings"
EMAX: updated value and the TDEMAG
Table 5: "Thermal data"
Rthj-board changed to Rthj-case
All typ. values updated
Table 8: "Switching"
02-Aug-2016
2
updated Min., Typ. and Max. columns
Table 10: "Protection"
ILIMH: updated Typ. and Max. values
ILIML: updated Typ. value
ΔTJ_SD: removed temperature condition
Table 11: "CurrentSense"
KOL: added Typ. value
VSENSE_SAT, ISENSE_SAT and IOUT_SAT: updated test conditions
CurrentSense timings (current sense mode): updated test
condition RL
tDSENSE2H: updated Max. value
Added Figure 4: "IOUT/ISENSE versus IOUT"
Added Figure 5: "Current sense precision vs. IOUT"
Added Section 2.4: "Electrical characteristics curves"
Added Figure 34: "Maximum turn off current versus inductance"
Updated Section 7.1: "Octapak package information"
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03-Aug-2016
3
Restored Figure 28: "Application diagram" and Figure 32: "Analogue
HSD – open-load detection in off-state", inadvertently altered in
document revision 2.
02-Nov-2016
4
Updated Applications section
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
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