VN7004CH
High-side driver with CurrentSense analog feedback for
automotive applications
Datasheet - production data
Self limiting of fast thermal transients
Loss of ground and loss of VCC
Reverse battery
Electrostatic discharge protection
Applications
Specially intended for Automotive smart power
distribution, glow plugs, heating systems, DC
motors, relay replacement and high power
resistive and inductive actuators.
Features
Max transient supply voltage
VCC
40 V
Operating voltage range
VCC
4 to 28 V
Typ. on-state resistance (per Ch)
RON
4 mΩ
Current limitation (typ)
ILIMH
135 A
Stand-by current (max)
ISTBY
0.5 µA
AEC-Q100 qualified
General
Single channel smart high-side driver
with CurrentSense analog feedback
Very low standby current
Compatible with 3.0 V and 5 V CMOS
outputs
Diagnostic functions
Overload and short to ground (power
limitation) indication
Thermal shutdown indication
OFF-state open-load detection
Output short to VCC detection
Sense enable/ disable
Protections
Undervoltage shutdown
Overvoltage clamp
Load current limitation
November 2016
Description
The device is a single channel high-side driver
manufactured using ST proprietary VIPower®
technology and housed in the Octapak package.
The device is designed to drive 12 V automotive
grounded loads through a 3 V and 5 V CMOScompatible interface, providing protection and
diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
Table 1: Device summary
Package
Octapak
DocID027769 Rev 6
This is information on a product in full production.
Order codes
Tape and reel
VN7004CHTR
1/36
www.st.com
Contents
VN7004CH
Contents
1
Block diagram and pin description ................................................ 5
2
Electrical specification .................................................................... 7
3
4
5
2.1
Absolute maximum ratings ................................................................ 7
2.2
Thermal data ..................................................................................... 8
2.3
Electrical characteristics .................................................................... 8
2.4
Electrical characteristics curves ...................................................... 15
Protections..................................................................................... 19
3.1
Power limitation ............................................................................... 19
3.2
Thermal shutdown ........................................................................... 19
3.3
Current limitation ............................................................................. 19
3.4
Negative voltage clamp ................................................................... 19
Application information ................................................................ 20
4.1
Protection against reverse battery................................................... 20
4.2
Immunity against transient electrical disturbances .......................... 21
4.3
MCU I/Os protection ........................................................................ 21
4.4
CS - analog current sense .............................................................. 22
7
2/36
Principle of CurrentSense signal generation .................................... 23
4.4.2
Short to VCC and OFF-state open-load detection ........................... 25
Package and PCB thermal data .................................................... 27
5.1
6
4.4.1
Octapak thermal data ...................................................................... 27
Package information ..................................................................... 30
6.1
Octapak package information.......................................................... 30
6.2
Octapak packing information ........................................................... 31
6.3
Octapak marking information .......................................................... 33
Revision history ............................................................................ 34
DocID027769 Rev 6
VN7004CH
List of tables
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pin functions ................................................................................................................................. 5
Table 3: Suggested connections for unused and not connected pins ........................................................ 6
Table 4: Absolute maximum ratings ........................................................................................................... 7
Table 5: Thermal data ................................................................................................................................. 8
Table 6: Power section ............................................................................................................................... 8
Table 7: Switching....................................................................................................................................... 9
Table 8: Logic inputs ................................................................................................................................. 10
Table 9: Protection .................................................................................................................................... 10
Table 10: CurrentSense ............................................................................................................................ 11
Table 11: Truth table ................................................................................................................................. 15
Table 12: ISO 7637-2 - electrical transient conduction along supply line ................................................. 21
Table 13: CurrentSense pin levels in off-state .......................................................................................... 25
Table 14: PCB properties ......................................................................................................................... 27
Table 15: Thermal parameters ................................................................................................................. 29
Table 16: Octapak mechanical data ......................................................................................................... 30
Table 17: Reel dimensions ....................................................................................................................... 32
Table 18: Document revision history ........................................................................................................ 34
DocID027769 Rev 6
3/36
List of figures
VN7004CH
List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Configuration diagram (top view)................................................................................................. 6
Figure 3: Current and voltage conventions ................................................................................................. 7
Figure 4: IOUT/ISENSE vs. IOUT ............................................................................................................. 13
Figure 5: Current sense precision vs. IOUT ............................................................................................. 13
Figure 6: Switching times and pulse skew ................................................................................................ 14
Figure 7: TDSTKON.................................................................................................................................. 14
Figure 8: OFF-state output current ........................................................................................................... 15
Figure 9: Standby current ......................................................................................................................... 15
Figure 10: IGND(ON) vs. Iout ................................................................................................................... 16
Figure 11: Logic input high level voltage .................................................................................................. 16
Figure 12: Logic input low level voltage .................................................................................................... 16
Figure 13: High level logic input current ................................................................................................... 16
Figure 14: Low level logic input current .................................................................................................... 16
Figure 15: Logic input hysteresis voltage ................................................................................................. 16
Figure 16: Undervoltage shutdown ........................................................................................................... 17
Figure 17: On-state resistance vs. Tcase ................................................................................................. 17
Figure 18: On-state resistance vs. VCC ................................................................................................... 17
Figure 19: Turn-on voltage slope .............................................................................................................. 17
Figure 20: Turn-off voltage slope .............................................................................................................. 17
Figure 21: Won vs. Tcase ......................................................................................................................... 17
Figure 22: Woff vs. Tcase ......................................................................................................................... 18
Figure 23: ILIMH vs. Tcase ....................................................................................................................... 18
Figure 24: Turn-off output voltage clamp .................................................................................................. 18
Figure 25: OFF-state open-load voltage detection threshold ................................................................... 18
Figure 26: Vs clamp vs. Tcase ................................................................................................................. 18
Figure 27: Vsenseh vs. Tcase .................................................................................................................. 18
Figure 28: Application diagram ................................................................................................................. 20
Figure 29: Simplified internal structure ..................................................................................................... 20
Figure 30: CurrentSense and diagnostic – block diagram........................................................................ 22
Figure 31: CurrentSense block diagram ................................................................................................... 23
Figure 32: Analogue HSD – open-load detection in off-state ................................................................... 24
Figure 33: Open-load / short to VCC condition ......................................................................................... 25
Figure 34: Maximum turn off current vs. inductance ................................................................................ 26
Figure 35: Octapak on two-layers PCB (2s0p to JEDEC JESD 51-5) ...................................................... 27
Figure 36: Octapak on four-layers PCB (2s2p to JEDEC JESD 51-7) ..................................................... 27
Figure 37: Rthj-amb vs PCB copper area in open box free air conditions ............................................... 28
Figure 38: Octapak thermal impedance junction ambient single pulse .................................................... 28
Figure 39: Thermal fitting model for Octapak ........................................................................................... 29
Figure 40: Octapak package dimensions ................................................................................................. 30
Figure 41: Octapack reel 13" .................................................................................................................... 31
Figure 42: Octapak carrier tape ................................................................................................................ 32
Figure 43: Octapak schematic drawing of leader and trailer tape ............................................................ 33
Figure 44: Octapak marking information................................................................................................... 33
4/36
DocID027769 Rev 6
VN7004CH
1
Block diagram and pin description
Block diagram and pin description
Figure 1: Block diagram
V CC
Reverse
Battery
Protection
Signal Clamp
Undervoltage
IN
Control & Diagnostic
Power
Clamp
DRIVER
Over
temperature
Current
Limitation
OFF State
Open load
SEn
V SENSEH
CS
Current
Sense
LOGIC
OUT
OVERLOAD PROTECTION
( ACTIVE POWER LIMI TATION )
GND
Table 2: Pin functions
Name
VCC
OUTPUT
GND
Function
Battery connection.
Power outputs. All the pins must be connected together.
Ground connection.
INPUT
Voltage controlled input pin with hysteresis. Compatible with 3 V and
5 V CMOS outputs. It controls output switch state.
CS
Analog current sense output pin delivers a current proportional to the
load current.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables
the CurrentSense diagnostic pin.
DocID027769 Rev 6
5/36
Block diagram and pin description
VN7004CH
Figure 2: Configuration diagram (top view)
Table 3: Suggested connections for unused and not connected pins
Connection / pin
CurrentSense
N.C.
Output
Input
SEn
Floating
Not allowed
X(1)
X
X
X
To ground
Through 1 kΩ
resistor
X
Not allowed
Through
15 kΩ resistor
Through
15 kΩ resistor
Notes:
(1)X:
6/36
do not care.
DocID027769 Rev 6
VN7004CH
2
Electrical specification
Electrical specification
Figure 3: Current and voltage conventions
VF = VOUT - VCC when VOUT > VCC and INPUT = LOW
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 4: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in the table below for extended
periods may affect device reliability.
Table 4: Absolute maximum ratings
Symbol
VCC
Parameter
Value
DC supply voltage
38
VCCPK
Maximum transient supply voltage (ISO7637-2:2004 Pulse 5b level
IV clamped to 40 V; RL = 4Ω)
40
Unit
V
-VCC
Reverse DC supply voltage
16
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT DC output current
Internally
limited
A
-IOUT
Reverse DC output current
38
IIN
INPUT DC input current
ISEn
SEn DC input current
ISENSE
EMAX
-1 to 10
CS pin DC output current (VGND = VCC and VSENSE < 0 V)
10
CS pin DC output current in reverse (VCC < 0 V)
-20
Maximum switching energy (single pulse)
TDEMAG = 0.13 ms; Tjstart = 150°C
105
DocID027769 Rev 6
mA
mA
mJ
7/36
Electrical specification
VN7004CH
Symbol
Parameter
Value
Unit
VESD
Electrostatic discharge (JEDEC 22A-114F)
INPUT
CurrentSense
SEn
OUTPUT
VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Tstg
2.2
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
°C
Thermal data
Table 5: Thermal data
Symbol
Parameter
Typ. value
Rthj-case
Thermal resistance junction-case(1)
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5)(2)
58.1
Rthj-amb
51-7)(1)
15.6
Unit
1.45
Thermal resistance junction-ambient (JEDEC JESD
°C/W
Notes:
2.3
(1)Device
mounted on four-layers 2s2p PCB
(2)Device
mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
Electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified.
Table 6: Power section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
4
13
28
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
4
VUSDReset
Undervoltage shutdown
reset
5
V
VUSDhyst
Undervoltage shutdown
hysteresis
IOUT = 15 A; Tj = 150°C
8
mΩ
IOUT = 15 A; VCC = 4 V;
Tj = 25°C
6
0.3
IOUT = 15 A; Tj = 25°C
RON
RON_Rev
Vclamp
8/36
Unit
On-state resistance
RDSON in reverse battery
condition
Clamp voltage
4
VCC = -13 V; IOUT = -15 A;
Tj = 25°C
IS = 20 mA; Tj = -40°C
38
IS = 20 mA;
25°C < Tj < 150°C
41
DocID027769 Rev 6
mΩ
4
46
52
V
VN7004CH
Electrical specification
Symbol
ISTBY
Parameter
Test conditions
Supply current in standby
at VCC = 13 V(1)
Max.
Unit
VCC = 13 V;
VIN = VOUT = VSEn = 0 V;
Tj = 25°C
0.5
µA
VCC = 13 V;
VIN = VOUT = VSEn = 0 V;
Tj = 85°C(2)
1.4
µA
VCC = 13 V;
VIN = VOUT = VSEn = 0 V;
Tj = 125°C
11
µA
300
550
µs
4
6.5
mA
9
mA
Standby mode blanking
time
VCC = 13 V; VIN = 5 V;
VSEn = 0 V; IOUT = 0 A
Supply current
VCC = 13 V; VSEn = 0 V;
VIN = 5 V; IOUT = 0 A
IGND(ON)
Control stage current
consumption in ON-state.
All channels active.
VCC = 13 V; VSEn = 5 V;
VIN = 5 V; IOUT = 15 A
IL(off)
Off-state output current at
VCC = 13 V
tD_STBY
IS(ON)
VF
Output - VCC diode voltage
Min.
60
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25°C
0
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C
0
Typ.
0.01
0.5
µA
11
IOUT = -15 A; Tj = 150°C
0.7
V
Unit
Notes:
(1)PowerMOS
(2)Parameter
leakage included.
specified by design; not subject to production test.
Table 7: Switching
VCC = 13 V; -40 ºC < Tj < 150 °C, unless otherwise specified
Symbol
td(on)(1)
Turn-on delay time at Tj = 25 °C
td(off)(1)
Turn-off delay time at Tj = 25 °C
(dVOUT/dt)on(1)
Turn-on voltage slope at Tj = 25 °C
(1)
Turn-off voltage slope at Tj = 25 °C
(dVOUT/dt)off
Test
conditions
Parameter
RL = 0.87 Ω
RL = 0.87 Ω
Min.
Typ.
Max.
10
50
120
10
60
100
0.075
0.28
0.7
0.075
0.33
0.7
µs
V/µs
WON
Switching energy losses at turn-on
(twon)
RL = 0.87 Ω
—
1.8
3.6(2)
mJ
WOFF
Switching energy losses at turn-off
(twoff)
RL = 0.87 Ω
—
2
3.6(2)
mJ
Differential Pulse skew
(tPHL - tPLH)
RL = 0.87 Ω
-50
0
50
µs
tSKEW (1)
Notes:
(1)See Figure 6: "Switching times and pulse skew"
(2)Parameter
guaranteed by design and characterization; not subject to production test.
DocID027769 Rev 6
9/36
Electrical specification
VN7004CH
Table 8: Logic inputs
7 V < VCC < 28 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
INPUT characteristics
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
0.9
VIN = 0.9 V
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
Input clamp voltage
V
1
V
5.3
IIN = -1 mA
µA
7.5
-0.7
V
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
VSEn(hyst)
Input hysteresis voltage
VSEnCL
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
Input clamp voltage
V
V
5.3
IIN = -1 mA
µA
7.5
-0.7
V
Table 9: Protection
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
ILIMH(1)
DC short circuit current
ILIML
Short circuit current
during thermal cycling
TTSD
Shutdown temperature
4 V < VCC < 18
Reset
TRS
Thermal reset of fault
diagnostic indication
Thermal hysteresis
(TTSD - TR)(2)
ΔTJ_SD
Dynamic temperature
Max.
80
135
175
175
VCC = 13 V;
TR < Tj < TTSD
VSEn = 5 V
THYST
Typ.
V(2)
temperature(2)
TR
VDEMAG
VCC = 13 V
Min.
A
38
150
175
TRS + 1
TRS + 7
200
°C
135
7
Turn-off output voltage
clamp
VCC = 13 V
60
IOUT = 2 A; L = 6 mH;
Tj = -40°C
VCC 38
IOUT = 2 A; L = 6 mH;
Tj = 25°C to 150°C
VCC 41
Notes:
10/36
Unit
(1)Parameter
guaranteed by an indirect test sequence.
(2)Parameter
guaranteed by design and characterization; not subject to production test.
DocID027769 Rev 6
K
V
VCC 46
VCC 52
V
VN7004CH
Electrical specification
Table 10: CurrentSense
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
VSENSE_CL
Parameter
Test conditions
CurrentSense clamp
voltage
VSEn = 0 V; ISENSE = 1 mA
Min.
Typ.
-17
VSEn = 0 V; ISENSE = -1 mA
Max.
Unit
-12
V
7
V
Current Sense characteristics
K1
dK1/K1(1)(2)
K2
dK2/K2(1)(2)
K3
dK3/K3(1)(2)
ISENSE0
IOUT/ISENSE
IOUT = 10 A; VSENSE = 4 V;
VSEn = 5 V
10040
Current sense ratio drift
IOUT = 10 A; VSENSE = 4 V;
VSEn = 5 V
-20
IOUT/ISENSE
IOUT = 15 A; VSENSE = 4 V;
VSEn = 5 V
12530
Current sense ratio drift
IOUT = 15 A; VSENSE = 4 V;
VSEn = 5 V
-15
IOUT/ISENSE
IOUT = 45 A; VSENSE = 4 V;
VSEn = 5 V
14450
Current sense ratio drift
IOUT = 45 A; VSENSE = 4 V;
VSEn = 5 V
-10
10
%
CurrentSense disabled:
VSEn = 0 V;
0
0.5
µA
CurrentSense disabled;
-1 V < VSENSE < 5 V(2)
-0.5
0.5
µA
CurrentSense enabled:
VSEn = 5 V; VIN = 5 V;
IOUT = 0 A;
0
100
µA
CurrentSense leakage
current
16720
23400
20
16710
20890
15
16970
%
%
18850
VOUT_CSD(2)
Output voltage for
CurrentSense
shutdown
VSEn = 5 V;
RSENSE = 2.7 kΩ; VIN = 5 V;
IOUT = 15 A
VSENSE_SAT
CurrentSense
saturation voltage
VCC = 7 V; RSENSE = 10 kΩ;
VSEn = 5 V; VIN = 5 V;
IOUT = 15 A; Tj = -40°C
5
V
ISENSE_SAT(2)
CS saturation current
VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V;
Tj = -40°C
4
mA
Output saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V;
Tj = -40°C
75
A
IOUT_SAT(2)
5
V
OFF-state diagnostic
VOL
OFF-state open-load
voltage detection
threshold
VIN = 0 V; VSEn = 5 V;
2
IL(off2)
OFF-state output sink
current
VIN = 0 V; VOUT = VOL;
Tj = -40°C to 125°C
-100
tDSTKON
OFF-state diagnostic
delay time from falling
edge of INPUT (see
Figure 7: "TDSTKON")
VIN = 5 V to 0 V;
VSEn = 5 V; IOUT = 0 A;
VOUT = 4 V
100
DocID027769 Rev 6
3
350
4
V
-15
µA
700
µs
11/36
Electrical specification
VN7004CH
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
tD_OL_V
Settling time for valid
OFF-state open load
diagnostic indication
from rising edge of SEn
VIN = 0 V; VOUT = 4 V;
VSEn = 0 V to 5 V
tD_VOL
OFF-state diagnostic
delay time from rising
edge of VOUT
VIN = 0 V; VSEn = 5 V;
VOUT = 0 V to 4 V
Min.
Typ.
Max.
Unit
60
µs
30
µs
6.6
V
30
mA
60
µs
5
20
µs
100
380
µs
200
µs
250
µs
5
Fault diagnostic feedback (see Table 11: "Truth table")
VSENSEH
CurrentSense output
voltage in fault
condition
VCC = 13 V; VIN = 0 V;
VSEn = 5 V; IOUT = 0 A;
VOUT = 4 V; RSENSE = 1 kΩ
5
ISENSEH
CurrentSense output
current in fault
condition
VCC = 13 V; VSENSE = 5 V
7
20
CurrentSense timings (current sense mode)(3)
tDSENSE1H
Current sense settling
time from rising edge of
SEn
VIN = 5 V; VSEn = 0 V to
5 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
tDSENSE1L
Current sense disable
delay time from falling
edge of SEn
VIN = 5 V; VSEn = 5 V to
0 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
tDSENSE2H
Current sense settling
time from rising edge of
INPUT
VIN = 0 V to 5 V;
VSEn = 5 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
ΔtDSENSE2H
Current sense settling
time from rising edge of
IOUT (dynamic response
to a step change of
IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; ISENSE
= 90% of ISENSEMAX;
RL = 0.87 Ω
Current sense turn-off
delay time from falling
edge of INPUT
VIN = 5 V to 0 V; VSEn = 5
V; RSENSE = 1 kΩ;
RL = 0.87 Ω
tDSENSE2L
Notes:
(1)All
values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
(2)Parameter
(3)Transition
12/36
guaranteed by design and characterization; not subject to production test.
delay are measured up to ±10% of final conditions.
DocID027769 Rev 6
50
VN7004CH
Electrical specification
Figure 4: IOUT/ISENSE vs. IOUT
Figure 5: Current sense precision vs. IOUT
DocID027769 Rev 6
13/36
Electrical specification
VN7004CH
Figure 6: Switching times and pulse skew
Figure 7: TDSTKON
14/36
DocID027769 Rev 6
VN7004CH
Electrical specification
Table 11: Truth table
Mode
INX
SEn
OUTX
Current Sense
L
Hi-Z
Comments
Stand by
All logic inputs
low
L
L
Nominal load
connected;
Tj < 150°C
L
H
L
0
Normal
H
L
H
Hi-Z
H
H
H
ISENSE = 1/K * IOUT
H
L
H
Hi-Z
H
H
H
VSENSEH
Output cycles with
temperature hysteresis
Hi-Z
Hi-Z
Re-start when
VCC > VUSD + VUSDhyst
(rising)
Overload
Overload or
short to GND
causing:
Tj > TTSD or
ΔTj > ΔTj_SD
Undervoltage
VCC < VUSD
(falling)
X
X
L
L
OFF-state
diagnostics
Short to VCC
L
H
H
Open-load
L
H
H
Inductive loads
turn-off
L
X
VOL
Open-load
VOUT < VOL
Short to VCC
Nominal
4.4.2
VOUT > VOL
VOUT < VOL
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
DocID027769 Rev 6
25/36
Application information
VN7004CH
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
Equation
Figure 34: Maximum turn off current vs. inductance
26/36
DocID027769 Rev 6
VN7004CH
Package and PCB thermal data
5
Package and PCB thermal data
5.1
Octapak thermal data
Figure 35: Octapak on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 36: Octapak on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 14: PCB properties
Dimension
Value
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on vias
0.025 mm
Footprint dimension (top layer)
6.4 mm x 7mm
Heatsink copper area dimension (bottom layer)
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Footprint, 2 cm2 or 8 cm2
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Package and PCB thermal data
VN7004CH
Figure 37: Rthj-amb vs PCB copper area in open box free air conditions
Figure 38: Octapak thermal impedance junction ambient single pulse
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Package and PCB thermal data
Equation: Pulse calculation formula
ZTHδ = RTH · + ZTHtp (1 - δ)
where δ = tP/T
Figure 39: Thermal fitting model for Octapak
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
Table 15: Thermal parameters
Area/island
(cm2)
Footprint
2
8
4L
R1 (°C/W)
0.01
0.01
0.01
0.01
R2 (°C/W)
0.5
0.5
0.5
0.5
R3 (°C/W)
1.6
1.6
1.6
1.6
R4 (°C/W)
10
10
10
2.5
R5 (°C/W)
28
20
12
5
R6 (°C/W)
36
26
18
6
C1 (W.s/°C)
0.001
0.001
0.001
0.001
C2 (W.s/°C)
0.0018
0.0018
0.0018
0.0018
C3 (W.s/°C)
0.11
0.11
0.11
0.11
C4 (W.s/°C)
0.6
0.6
0.6
0.8
C5 (W.s/°C)
0.8
1.4
2.2
3
C6 (W.s/°C)
3
6
9
25
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Package information
6
VN7004CH
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.1
Octapak package information
Figure 40: Octapak package dimensions
Table 16: Octapak mechanical data
Millimeters
Symbol
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Min.
Typ.
Max.
A
2.20
2.30
2.40
A1
0.90
1.00
1.10
A2
0.03
b
0.38
DocID027769 Rev 6
0.15
0.45
0.52
VN7004CH
Package information
Millimeters
Symbol
Min.
Typ.
b1
0.70
b4
5.20
5.30
5.40
c
0.45
0.50
0.60
c2
0.75
0.80
0.90
D
6.00
6.10
6.20
D1
E
5.15
6.40
E1
6.50
6.60
5.30
e
0.85 BSC
e1
1.60
1.70
1.80
e2
3.30
3.40
3.50
e3
5.00
5.10
5.20
H
9.35
9.70
10.10
L
1.00
—
(L1)
2.80
L2
0.80
L3
0.85
R
V2
6.2
Max.
0.40 BSC
0°
8°
Octapak packing information
Figure 41: Octapack reel 13"
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Package information
VN7004CH
Table 17: Reel dimensions
Description
Value(1)
Base quantity
2500
Bulk quantity
2500
A (max)
330
B (min)
1.5
C (+0.5, -0.2)
13
D
20.2
N
100
W1 (+2 /-0)
16.4
W2 (max)
22.4
Notes:
(1)All
dimensions are in mm.
Figure 42: Octapak carrier tape
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Package information
Figure 43: Octapak schematic drawing of leader and trailer tape
6.3
Octapak marking information
Figure 44: Octapak marking information
Parts marked as "&" are not yet qualified and therefore not approved for use in production.
ST is not responsible for any consequences resulting from such use. In no event will ST be
liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to
run a qualification activity.
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Revision history
7
VN7004CH
Revision history
Table 18: Document revision history
Date
Revision
21-Apr-2015
1
Changes
Initial release
Table 4: "Absolute maximum ratings":
VCC_LSC: removed row
EMAX: updated value
Table 6: "Power section":
06-Aug-2015
2
ISTBY, IL(off): updated values
Updated Table 7: "Switching"
Table 9: "Protection":
ILIMH: updated values
Table 10: "CurrentSense":
Kx, dKx/Kx, ISENSE0, IOUT_SAT: updated values
Updated Section "Features"
Table 6: "Power section":
12-Nov-2015
3
ISTBY, IL(off): updated values
Table 10: "CurrentSense":
27-Apr-2016
4
Updated Figure 1: "Block diagram"
Table 10: "CurrentSense":
34/36
dKx/Kx: updated values
K3: updated values
DocID027769 Rev 6
VN7004CH
Revision history
Date
Revision
Changes
Section "Features":
Current limitation (typ): updated value
Table 4: "Absolute maximum ratings":
EMAX: updated TDEMAG parameter and value
Table 5: "Thermal data":
Updated all Typ values and Rthj-case term
Table 7: "Switching":
(dVOUT/dt)on, (dVOUT/dt)off, W ON, W OFF, tSKEW: updated values
Table 9: "Protection":
ILIMH, ILIML: updated typ and max values
ΔTJ_SD: removed Tj test condition
Table 10: "CurrentSense":
12-Jul-2016
5
VSENSE_SAT, ISENSE_SAT, IOUT_SAT: updated test conditions
tDSENSE2H: updated max value
Section 2.3: "Electrical characteristics":
Added Figure 4: "IOUT/ISENSE vs. IOUT" and Figure 5:
"Current sense precision vs. IOUT"
Added Section 2.4: "Electrical characteristics curves"
Section 4.4.2: "Short to VCC and OFF-state open-load detection":
Added Figure 34: "Maximum turn off current vs. inductance"
Section 6.1: "Octapak thermal data":
Updated Figure 35: "Octapak on two-layers PCB (2s0p to
JEDEC JESD 51-5)", Figure 36: "Octapak on four-layers PCB
(2s2p to JEDEC JESD 51-7)", Figure 37: "Rthj-amb vs PCB
copper area in open box free air conditions", Figure 38:
"Octapak thermal impedance junction ambient single pulse",
Figure 39: "Thermal fitting model for Octapak", and Table 15:
"Thermal parameters"
Minor text corrections throughout the document
09-Nov-2016
6
Updated Applications section
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VN7004CH
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
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DocID027769 Rev 6
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