VN772KP-E

VN772KP-E Quad smart power solid state relay for complete H-bridge configurations Datasheet - production data Description The VN772KP-E is a device formed by three monolithic chips housed in a standard SO-28 package: a double high-side and two low-side switches. Both the double high-side and low-side switches are made using STMicroelectronics VIPower® M0-3 Technology. 62 *$3*&)7 Features Type RDS(on) IOUT VCC VN772KP-E 125 mΩ(1) 9 A(2) 36 V The dual high-side switches have built-in thermal shutdown to protect the chips from over temperature and current limiter blocks to protect the device from short circuit. Status output is provided to indicate open-load in OFF and ON-state and overtemperature. 1. Total resistance of one side in bridge configuration 2. Typical current limitation value • ECOPACK®: lead free and RoHS compliant • Automotive Grade: compliant with AEC guidelines • Suited as low voltage bridge This device is suitable to drive a DC motor in a bridge configuration as well as to be used as a quad switch for any low voltage application. The low-side switches are two OMNIFET II types (fully auto protected Power MOSFET in VIPower technology). They have built-in thermal shutdown, linear current limitation and overvoltage clamping. Fault feedback for thermal intervention can be detected by monitoring the voltage at the input pin. • Linear current limitation • Very low standby power dissipation • Short circuit protected • Status flag diagnostic (open drain) • Integrated clamping circuits • Undervoltage protection • ESD protection Table 1. Device summary Order codes Package SO-28 February 2015 This is information on a product in full production. Tube Tape and reel VN772KP-E VN772KPTR-E DocID022022 Rev 3 1/34 www.st.com Contents VN772KP-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics for dual high side switch . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics for low-side switches . . . . . . . . . . . . . . . . . . . . . .11 2.5 Dual high-side switch timing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6 Electrical characterization for dual high-side switch . . . . . . . . . . . . . . . . . 16 2.7 Electrical characterization for low-side switches . . . . . . . . . . . . . . . . . . . 19 3 Application recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 6 2/34 4.1 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 Thermal calculation in clockwise and anti-clockwise operation in steady state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.1 Thermal resistances definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.2 Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.3 Single pulse thermal impedance definition . . . . . . . . . . . . . . . . . . . . . . 27 4.2.4 Pulse calculation formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 SO-28 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DocID022022 Rev 3 VN772KP-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Dual high-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power outputs (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (per each channel) (VCC = 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic input (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Status pin (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protections (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Open-load detection (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 On-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Source drain diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal calculation in clockwise and anti-clockwise operation in steady state mode . . . . 27 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DocID022022 Rev 3 3/34 3 List of figures VN772KP-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 4/34 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Open-load status timing (with external pull-up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Over temperature status timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Static drain source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-on current slope (VIN = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-on current slope (VIN = 3.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input voltage vs input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Switching time resistive load (VIN = 5 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Switching time resistive load (Rg = 10 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Source drain diode forward characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Static drian source on resistance vs ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Static drain source on resistance vs input voltage (ID = 7 A) . . . . . . . . . . . . . . . . . . . . . . . 21 Static drain source on resistance vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Normalized input threshold voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Normalized on resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Turn-off drain source voltage slope (VIN = 3.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Turn-off drain source voltage slope (VIN = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Current limit vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Application diagram bridge drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Recommended motor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DocID022022 Rev 3 VN772KP-E Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. List of figures Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 26 SO-28 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . 28 SO-28 LSD thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . 28 Thermal fitting model of an H-bridge in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SO-28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Tube dimensions (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Tape and reel dimensions (suffix “13TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DocID022022 Rev 3 5/34 5 Block diagram and pin description 1 VN772KP-E Block diagram and pin description Figure 1. Block diagram 9FF 9FF FODPS 2YHUYROWDJH 8QGHUYROWDJH *1' &ODPS ,1387 6285&( 'ULYHU &ODPS ',$* /RJLF &XUUHQWOLPLWHU 'ULYHU 6285&( 2SHQORDG21 &XUUHQWOLPLWHU 2YHUWHPS 2SHQORDG2)) ,1387 2SHQORDG21 2SHQORDG2)) 2YHUWHPS 2YHUYROWDJH &ODPS '5$,1 ,1387 *DWH&RQWURO 6285&(  2YHU 7HPSHUDWXUH /LQHDU &XUUHQW /LPLWHU 2YHUYROWDJH &ODPS '5$,1 67$786 *DWH&RQWURO  6285&(  2YHU 7HPSHUDWXUH /LQHDU &XUUHQW /LPLWHU *$3*&)7 6/34 DocID022022 Rev 3 VN772KP-E Block diagram and pin description Table 2. Pin definition and function No Name Function 1, 3, 25, 28 DRAIN 3 Drain of switch 3 (low-side switch) 2 INPUT 3 Input of switch 3 (low-side switch) 4, 11 N.C. Not connected 5, 10, 19, 24 VCC Drain of switches 1 and 2 (high-side switches) and power supply voltage 6 GND Ground of switches 1 and 2 (high-side switches) 7 INPUT 1 8 DIAGNOSTIC 9 INPUT 2 Input of switch 2 (high-side switch) 12, 14, 15, 18 DRAIN 4 Drain of switch 4 (low-side switch) 13 INPUT 4 Input of switch 4 (low-side switch) 16, 17 SOURCE 4 Source of switch 4 (low-side switch) 20, 21 SOURCE 2 Source of switch 2 (high-side switch) 22, 23 SOURCE 1 Source of switch 1 (high-side switch) 26, 27 SOURCE 3 Source of switch 3 (low-side switch) Input of switch 1 (high-side switches) Diagnostic of switches 1 and 2 (high-side switches) Figure 2. Connection diagram DocID022022 Rev 3 7/34 33 Electrical specifications VN772KP-E 2 Electrical specifications 2.1 Thermal data Table 3. Thermal data Symbol 2.2 Value Max (°C/W) Parameter Rthj-case Thermal resistance junction-case (high side switch) 20 Rthj-case Thermal resistance junction-case (low side switch) 20 Rthj-amb Thermal resistance junction-ambient (with 6 cm2 of Cu heat sink) See Figure 49 Absolute maximum ratings Table 4. Dual high-side switch Symbol Parameter Value Unit VCC DC supply voltage 41 V -VCC Reverse DC supply voltage -0.3 V -IGND DC reverse ground pin current -200 mA IOUT DC output current Internally limited A -IOUT Reverse DC output current -6 A IIN DC input current ±10 mA ISTAT DC status current ±10 mA VESD Electrostatic discharge (human body model: R = 1.5 KΩ; C = 100 pF) – Input – Status – Output – VCC 4000 4000 5000 5000 V V V V Ptot Power dissipation (TC = 25 °C) 6 W Tj Junction operating temperature Internally limited °C Tc Case operating temperature -40 to 150 °C Storage temperature -55 to 150 °C Value Unit Tstg Table 5. Low-side switch Symbol 8/34 Parameter VDS Drain source voltage (VIN = 0 V) Internally clamped V VIN Input voltage Internally clamped V IIN Input current ±20 mA DocID022022 Rev 3 VN772KP-E Electrical specifications Table 5. Low-side switch (continued) Symbol RIN MIN 2.3 Parameter Value Unit 150 Ω Internally limited A Minimum input series impedance ID Drain current IR Reverse DC output current -10.5 A VESD1 Electrostatic discharge (R = 1.5 KΩ, C = 100 pF) 4000 V VESD2 Electrostatic discharge on output pin only (human body model: R = 330 Ω, C = 150 pF) 5000 V Ptot Power dissipation (TC = 25°C) 6 W Tj Operating junction temperature Internally limited °C Electrical characteristics for dual high side switch 8 V < VCC < 36 V; -40°C < Tj < 150°C, unless otherwise specified. Table 6. Power outputs (per each channel) Symbol Parameter VCC(1) Operating supply voltage 5.5 13 36 V VUSD(1) Undervoltage shutdown 3 4 5.5 V VOV(1) Overvoltage shutdown 36 RON IS(1) Test conditions On-state resistance Supply current Min Typ Max Unit V IOUT = 2 A; Tj = 25°C 60 mΩ IOUT = 2 A; VCC > 8 V 120 mΩ Off-state; VCC = 13 V; VIN = VOUT = 0 V 12 40 µA Off-state; VCC = 13 V; VIN = VOUT = 0 V; Tj = 25°C 12 25 µA On-state; VCC = 13 V 5 7 mA 0 50 µA -75 0 µA IL(off1) Off-state output current VIN = VOUT = 0 V; VCC = 36 V; Tj = 125°C IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V IL(off3) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 125°C 5 µA IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 25°C 3 µA 1. Per device. DocID022022 Rev 3 9/34 33 Electrical specifications VN772KP-E Table 7. Switching (per each channel) (VCC = 13 V) Symbol Parameter Test conditions Min Typ Max Unit td(on) Turn-on delay time RL = 6.5 Ω from VIN rising edge to VOUT = 1.3 V — 30 — µs td(off) Turn-off delay time RL =6.5Ω from VIN falling edge to VOUT = 11.7 V — 30 — µs dVOUT/dt(on) Turn-on voltage slope RL = 6.5 Ω from VOUT = 1.3 V to VOUT = 10.4 V — (1) — V/µs dVOUT/dt(off) Turn-off voltage slope RL = 6.5 Ω from VOUT = 11.7 V to VOUT = 1.3 V — (1) — V/µs Max Unit 1.25 V 1. See relative diagram Table 8. Logic input (per each channel) Symbol Parameter Test conditions VIL Input low level IIL Low level input current VIH Input high level IIH High level input current VI(hyst) Input hysteresis voltage VICL Min VIN = 1.25 V 1 µA 3.25 V VIN = 3.25 V 10 0.5 IIN = 1 mA Input clamp voltage Typ µA V 6 6.8 IIN = -1 mA 8 V -0.7 V Table 9. Status pin (per each channel) Symbol Parameter Test conditions Min Typ Max Unit VSTAT Status low output voltage ISTAT = 1.6 mA 0.5 V ILSTAT Status leakage current Normal operation; VSTAT = 5 V 10 µA CSTAT Status pin input capacitance Normal operation; VSTAT = 5 V 100 pF VSCL Status clamp voltage 8 V ISTAT = 1 mA 6 ISTAT = -1 mA 6.8 -0.7 V Table 10. Protections (per each channel) 10/34 Symbol Parameter TTSD Test conditions Min Typ Max Unit Shutdown temperature 150 175 200 °C TR Reset temperature 135 Thyst Thermal hysteresis 7 tSDL Status delay in overload Tj > TTSD conditions DocID022022 Rev 3 °C 15 °C 20 µs VN772KP-E Electrical specifications Table 10. Protections (per each channel) (continued) Symbol Ilim Parameter Test conditions Current limitation Tj = 125°C Min Typ Max Unit 6 9 15 A 15 A 15 A 8.5 5.5 V < VCC < 36 V Vdemag Note: Turn-off output clamp voltage IOUT = 2 A; L = 6 mH VCC - 41 VCC - 48 VCC - 55 V To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 11. Open-load detection (per each channel) Symbol IOL Parameter Test conditions Open-load on-state detection threshold VIN = 5 V tDOL(on) Open-load on-state detection delay VOL tDOL(off) 2.4 Open-load off-state voltage detection threshold Min Typ Max Unit 50 100 200 mA 200 µs 3.5 V 1000 µs IOUT = 0 A VIN = 0 V 1.5 2.5 Open-load detection delay at turnoff Electrical characteristics for low-side switches -40 °C < Tj < 150 °C, unless otherwise specified. Table 12. Off-state Symbol Parameter Test conditions Min Typ 45 Drain source clamp voltage VIN = 0 V; ID = 3.5 A 40 VCLTH Drain source clamp threshold voltage VIN = 0 V; ID = 2 mA 36 VINTH Input threshold voltage VDS = VIN; ID = 1 mA 0.5 VCLAMP IISS Input-source clamp voltage IDSS Zero input voltage drain current (VIN = 0 V) 55 V V 2.5 V 100 150 µA 6.8 8 V -0.3 V VDS = 13 V; VIN = 0 V; Tj = 25°C 30 µA VDS = 25 V; VIN = 0 V 75 µA Supply current from input pin VDS = 0 V; VIN = 5 V VINCL Max Unit IIN = 1 mA 6 IIN = -1 mA -1.0 DocID022022 Rev 3 11/34 33 Electrical specifications VN772KP-E Table 13. On-state Symbol RDS(on) Parameter Test conditions Min Typ Max Unit — — 65 mΩ — — 130 mΩ Static drain source on VIN = 5 V; ID = 3.5 A; Tj = 25°C resistance VIN = 5 V; ID = 3.5 A Tj = 25°C, unless otherwise specified. Table 14. Dynamic Symbol Parameter Test conditions Min Typ Max Unit gfs(1) Forward trans conductance VDD =13 V; ID = 3.5 A — 9 — S COSS Output capacitance — 220 — pF VDS = 13 V; f = 1 MHz; VIN = 0 V 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% Table 15. Switching Symbol td(on) tr td(off) tf td(on) tr td(off) tf (dI/dt)on Qi Parameter Test conditions Min Typ Max Unit — 100 300 ns — 470 1500 ns — 500 1500 ns Fall time — 350 1000 ns Turn-on delay time — 0.75 2.3 µs — 4.6 14 µs — 5.4 16 µs — 3.6 11 µs Turn-on delay time Rise time VDD = 15 V; ID = 3.5 A; Vgen = 5 V; Rgen = RIN MIN = 150 Ω Turn-off delay time Rise time VDD = 15 V; ID = 3.5 A; Vgen = 5 V; Rgen = 2.2 kΩ Turn-off delay time Fall time Turn-on current slope VDD = 15 V; ID = 3.5 A; Vgen = 5 V; Rgen = RIN MIN = 150 Ω — 6.5 A/µs Total input charge VDD =12 V; ID = 3.5 A; VIN = 5 V; Igen = 2.13 mA — 18 nC Table 16. Source drain diode Symbol VSD(1) trr Qrr IRRM Parameter Test conditions Forward on voltage ISD = 3.5 A; VIN = 0 V Reverse recovery time I = 3.5 A; dI/dt = 20 A/µs; Reverse recovery charge SD VDD = 30 V; L = 200 µH Reverse recovery current 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 12/34 DocID022022 Rev 3 Min Typ Max Unit — 0.8 — V — 220 — ns — 0.28 — µC — 2.5 — A VN772KP-E Electrical specifications -40 °C < Tj < 150 °C, unless otherwise specified. Table 17. Protections Symbol 2.5 Parameter Test conditions VIN = 5 V; VDS = 13 V Min Typ 6 9 Ilim Drain current limit tdlim Step response current limit Tjsh Overtemperature shutdown 150 Tjrs Overtemperature reset 135 Igf Fault sink current Eas Starting Tj = 25 °C; VDD = 24 V; Single pulse avalanche VIN = 5 V; Rgen = RIN MIN = 150 Ω; energy L = 24 mH VIN = 5 V; VDS = 13 V; Tj = 125°C 6.5 VIN = 5 V; VDS = 13 V VIN = 5 V; VDS = 13 V; Tj = Tjsh Max Unit 12 A 12 A 4 µs 175 °C °C 15 200 mA mJ Dual high-side switch timing data Figure 3. Switching time waveforms 9287Q   G9287GWRII G9287GWRQ  W 9,1Q GWRQ GWRII W *$3*&)7 DocID022022 Rev 3 13/34 33 Electrical specifications VN772KP-E Table 18. Truth table Conditions Input Output Status Normal operation L H L H H H Current limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Over temperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L H H Output voltage > VOL L H H H L H Output current < IOL L H L H H L Figure 4. Open-load status timing (with external pull-up) 9287!92/ ,287,2/ 9,1Q 967$7Q W'2/RII W'2/RQ *$3*&)7 14/34 DocID022022 Rev 3 VN772KP-E Electrical specifications Figure 5. Over temperature status timing 7M!776' 9,1Q 967$7Q W6'/ W6'/ *$3*&)7 DocID022022 Rev 3 15/34 33 Electrical specifications 2.6 VN772KP-E Electrical characterization for dual high-side switch Figure 6. Off-state output current Figure 7. Input clamp voltage Vicl (V) IL(off1) (uA) 8 2.5 7.8 2.25 Off state Vcc=36V Vin=Vout=0V 2 1.75 Iin=1mA 7.6 7.4 7.2 1.5 1.25 7 1 6.8 0.75 6.6 0.5 6.4 0.25 6.2 6 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 8. High level input current Figure 9. Input high level voltage Vih (V) Iih (uA) 3.6 5 4.5 3.4 Vin=3.25V 4 3.2 3.5 3 3 2.8 2.5 2 2.6 1.5 2.4 1 2.2 0.5 2 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 10. Input low level voltage Figure 11. Input hysteresis voltage Vil (V) Vhyst (V) 2.6 1.5 1.4 2.4 1.3 2.2 1.2 2 1.1 1 1.8 0.9 1.6 0.8 1.4 0.7 1.2 0.6 0.5 1 -50 -25 0 25 50 75 100 125 150 175 -50 16/34 -25 0 25 50 75 Tc (°C) Tc (ºC) DocID022022 Rev 3 100 125 150 175 VN772KP-E Electrical specifications Figure 12. Overvoltage shutdown Figure 13. ILIM vs Tcase Vov (V) Ilim (A) 50 20 48 18 46 16 44 14 42 12 40 10 38 8 36 6 34 4 32 2 30 Vcc=13V 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 100 125 150 175 Figure 15. Turn-off voltage slope dVout/dt(on) (V/ms) dVout/dt(off) (V/ms) 800 600 550 Vcc=13V Rl=6.5Ohm 600 75 Tc (°C) Figure 14. Turn-on voltage slope 700 50 Vcc=13V Rl=6.5Ohm 500 500 450 400 400 300 350 200 300 100 250 200 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 Figure 16. On-state resistance vs Tcase Ron (mOhm) 160 120 150 175 Tc=150°C 110 Iout=2A Vcc=8V; 13V & 36V 120 125 Figure 17. On-state resistance vs VCC Ron (mOhm) 140 100 Tc (ºC) Tc (ºC) 100 90 80 100 70 80 60 Tc=25°C 50 60 40 40 Tc= - 40°C 30 20 20 Iout=5A 10 0 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) 5 10 15 20 25 30 35 40 Vcc (V) DocID022022 Rev 3 17/34 33 Electrical specifications VN772KP-E Figure 18. Status leakage current Figure 19. Status low output voltage Vstat (V) Ilstat (uA) 1 0.05 0.9 Istat=1.6mA 0.8 0.04 0.7 Vstat=5V 0.6 0.03 0.5 0.02 0.4 0.3 0.01 0.2 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 75 100 125 150 175 Tc (ºC) Figure 20. Open-load on-state detection threshold Iol (mA) Figure 21. Open-load off-state voltage detection threshold Vol (V) 150 5 140 4.5 Vcc=13V Vin=5V 130 Vin=0V 4 120 3.5 110 3 100 2.5 90 2 80 1.5 70 1 60 0.5 50 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (ºC) Vscl (V) 8 7.8 Istat=1mA 7.6 7.4 7.2 7 6.8 6.6 6.4 6.2 6 -50 -25 0 25 50 75 -25 0 25 50 75 Tc (ºC) Figure 22. Status clamp voltage 100 125 150 175 Tc (°C) 18/34 50 DocID022022 Rev 3 100 125 150 175 VN772KP-E 2.7 Electrical specifications Electrical characterization for low-side switches Figure 23. Static drain source on resistance Figure 24. Derating curve Figure 25. Transconductance Figure 26. Transfer characteristics Figure 27. Turn-on current slope (VIN = 5 V) Figure 28. Turn-on current slope (VIN = 3.5 V) DocID022022 Rev 3 19/34 33 Electrical specifications VN772KP-E Figure 29. Input voltage vs input charge Figure 30. Capacitance variations Figure 31. Switching time resistive load (VIN = 5 V) Figure 32. Switching time resistive load (Rg = 10 Ω) Figure 33. Output characteristics Figure 34. Step response current limit 20/34 DocID022022 Rev 3 VN772KP-E Electrical specifications Figure 35. Source drain diode forward characteristics Figure 36. Static drian source on resistance vs ID Figure 37. Static drain source on resistance vs Figure 38. Static drain source on resistance vs input voltage (ID = 7 A) input voltage Figure 39. Normalized input threshold voltage vs temperature Figure 40. Normalized on resistance vs temperature DocID022022 Rev 3 21/34 33 Electrical specifications VN772KP-E Figure 41. Turn-off drain source voltage slope (VIN = 3.5 V) Figure 42. Turn-off drain source voltage slope (VIN = 5 V) Figure 43. Current limit vs junction temperature 22/34 DocID022022 Rev 3 VN772KP-E 3 Application recommendations Application recommendations Figure 44. Application diagram bridge drivers Most motor bridge drivers use a reverse battery protection diode (D) inside the supply rail. This diode prevents a reverse current flow back to VBATT in case the bridge becomes disabled via the logic inputs while motor inductance still carries energy. In order to prevent a hazardous overvoltage at circuit supply terminal (VCC), a blocking capacitor (C) is needed to limit the voltage overshoot. As basic orientation, 50 µF per 1 A load current is recommended. As an alternative, a Zener protection (Z) is also suitable. Even if a reverse polarity diode is not present, it is recommended to use a capacitor or Zener at VCC because a similar problem appears in case the supply terminal of the module has intermittent electrical contact to the battery or gets disconnected while the motor is operating. DocID022022 Rev 3 23/34 33 Application recommendations VN772KP-E Figure 45. Recommended motor operation 24/34 DocID022022 Rev 3 VN772KP-E Application recommendations Figure 46. Waveforms DocID022022 Rev 3 25/34 33 Thermal data VN772KP-E 4 Thermal data 4.1 SO-28 thermal data Figure 47. SO-28 PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58mm x 58mm, PCB thickness = 2mm, Cu thickness = 35µm, Copper areas: from minimum pad layout to 6cm2). Figure 48. Chipset configuration LOW SIDE CHIP RthAB channel 3 HIGH SIDE CHIP channel 1,2 RthA RthB RthAC LOW SIDE CHIP channel 4 RthC RthBC Figure 49. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition 1. See definitions in Section 5.2 on page 32. 26/34 DocID022022 Rev 3 VN772KP-E 4.2 Thermal data Thermal calculation in clockwise and anti-clockwise operation in steady state mode Table 19. Thermal calculation in clockwise and anti-clockwise operation in steady state mode HS1 HS2 LS3 LS4 TjHS12 On Off Off On PdHS1 x RthHS + PdLS4 x RthHSLS + Tamb PdHS1 x RthHSLS + PdLS4 PdHS1 x RthHSLS + PdLS4 x x RthLSLS + Tamb RthLS + Tamb Off On On Off PdHS2 x RthHS + PdLS3 x RthHSLS + Tamb PdHS2 x RthHSLS + PdLS3 PdHS2 x RthHSLS + PdLS3 x x RthLS + Tamb RthLSLS + Tamb 4.2.1 TjLS3 TjLS4 Thermal resistances definition Values according to the PCB heatsink area. RthHS = RthHS1 = RthHS2 = high side chip thermal resistance junction to ambient (HS1 or HS2 in on-state) RthLS = RthLS3 = RthLS4 = low side chip thermal resistance junction to ambient RthHSLS = RthHS1LS4 = RthHS2LS3 = mutual thermal resistance junction to ambient between high side and low side chips RthLSLS = RthLS3LS4 = mutual thermal resistance junction to ambient between low side chips 4.2.2 Thermal calculation in transient mode TjHS12 = ZthHS x PdHS12 + ZthHSLS x (PdLS3 + PdLS4) + Tamb TjLS3 = ZthHSLS x PdHS12 + ZthLS x PdLS3 + ZthLSLS x PdLS4 + Tamb TjLS4 = ZthHSLS x PdHS12 + ZthLSLS x PdLS3 + ZthLS x PdLS4 + Tamb Note: Calculation is valid in any dynamic operating condition. Pd values set by user. 4.2.3 Single pulse thermal impedance definition Values according to the PCB heatsink area. ZthHS = high side chip thermal impedance junction to ambient ZthLS = ZthLS3 = ZthLS4 = low side chip thermal impedance junction to ambient ZthHSLS = ZthHS12LS3 = ZthHS12LS4 = mutual thermal impedance junction to ambient between high side and low side chips ZthLSLS = ZthLS3LS4 = mutual thermal impedance junction to ambient between low side chips 4.2.4 Pulse calculation formula Z THδ = R TH ⋅δ+Z THtp (1 – δ) where δ = tP/T DocID022022 Rev 3 27/34 33 Thermal data VN772KP-E Figure 50. SO-28 HSD thermal impedance junction ambient single pulse Figure 51. SO-28 LSD thermal impedance junction ambient single pulse 28/34 DocID022022 Rev 3 VN772KP-E Thermal data Figure 52. Thermal fitting model of an H-bridge in SO-28 Table 20. Thermal parameters Area/island (cm2) Footprint 1 2 6 R1 = R6 (°C/W) 1.5 1.5 1.5 1.5 R2 (°C/W) 2.6 2.6 2.6 2.6 R12 = R17 (°C/W) 3.5 3.5 3.5 3.5 R3 = R13 = R 18 (°C/W) 15.5 15.5 15.5 15.5 R4 = R14 = R19 (°C/W) 10.5 10.5 10.5 10.5 R5 = R15 = R20 (°C/W) 62.28 52.28 44.28 32.28 R7 = R8 = R9 = R10 (°C/W) 150 150 150 150 R11 = R16 (°C/W) 1.5 1.5 1.5 1.5 C1 = C5 (W.s/°C) 0.00035 0.00035 0.00035 0.00035 C2 = C7 = C11 (W.s/°C) 0.024 0.024 0.024 0.024 C3 = C8 = C 12 (W.s/°C) 0.2 0.2 0.2 0.2 C4 = C9 = C13 (W.s/°C) 1.6 1.61 1.7 3.25 C6 = C10 (W.s/°C) 0.00075 0.00075 0.00075 0.00075 DocID022022 Rev 3 29/34 33 Package mechanical data 5 VN772KP-E Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.1 SO-28 mechanical data Figure 53. SO-28 package outline ' % GGG F $ $ K[ƒ &  6($7,1* 3/$1(  PP *$*(3/$1(  3,1 ,'(17,),&$7,21  N $ ( + & / H *$3*36 30/34 DocID022022 Rev 3 VN772KP-E Package mechanical data Table 21. SO-28 mechanical data Dimension Ref. Millimeters Min. Typ Max. A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D(1) 17.70 18.10 E 7.40 7.60 e 1.27 H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 k 0° 8° ddd 0.10 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. DocID022022 Rev 3 31/34 33 Package mechanical data 5.2 VN772KP-E SO-28 Packing information Figure 54. Tube dimensions (no suffix) Figure 55. Tape and reel dimensions (suffix “13TR”) 32/34 DocID022022 Rev 3 VN772KP-E 6 Revision history Revision history Table 22. Document revision history Date Revision Changes 21-Jul-2011 1 Initial release. 18-Sep-2013 2 Updated Disclaimer 12-Feb-2015 3 Updated Section 5.1: SO-28 mechanical data and Section 5.2: SO28 Packing information DocID022022 Rev 3 33/34 33 VN772KP-E IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 34/34 DocID022022 Rev 3