VND5E006ASP-E
Double channel high-side driver with analog current sense
for automotive applications
Datasheet - production data
– Protection against loss of ground and loss
of VCC
– Overtemperature shutdown with auto
restart (thermal shutdown)
– Inrush current active management by
power limitation
– Reverse battery protected with self switch
of the PowerMOS
– Electrostatic discharge protection
PowerSO-16
Features
Max transient supply voltage
VCC
41 V
Operating voltage range
VCC 4.5 to 28 V
Typ on-state resistance (per ch.)
RON
5 mΩ
Current limitation (typ)
ILIMH
100 A
Off-state supply current
IS
2 µA(1)
1. Typical value with all loads connected.
• General
– Very low standby current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– Compliance with European directive
2002/95/EC
– Very low current sense leakage
• Diagnostic functions
– Proportional load current sense
– High current sense precision for wide
currents range
– Current sense disable
– Off-state openload detection
– Output short to VCC detection
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
• Protection
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
October 2013
This is information on a product in full production.
Applications
• All types of resistive, inductive and capacitive
loads
Description
The VND5E006ASP-E is a double channel
high-side driver manufactured using ST
proprietary VIPower™ M0-5 technology and
housed in PowerSO-16 package. The device is
designed to drive 12 V automotive grounded
loads, and to provide protection and diagnostics.
They also implement a 3 V and 5 V CMOS
compatible interface for the use with any
microcontroller.
The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, overtemperature shut-off with auto
restart and overvoltage active clamp. A dedicated
analog current sense pin is associated with every
output channel providing enhanced diagnostic
functions including fast detection of overload and
short-circuit to ground through power limitation
indication, overtemperature indication, shortcircuit to VCC diagnosis and on-state and off-state
open-load detection. The current sensing and
diagnostic feedback of the whole device can be
disabled by pulling the CS_DIS pin high to share
the external sense resistor with similar devices.
DocID17362 Rev 6
1/37
www.st.com
Contents
VND5E006ASP-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1
3.4
4
Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 27
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1
5
Short to VCC and off-state open-load detection . . . . . . . . . . . . . . . . . . 26
PowerSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2
PowerSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/37
DocID17362 Rev 6
VND5E006ASP-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current sense (8 V < VCC < 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Open-load detection (8 V < VCC < 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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3
List of figures
VND5E006ASP-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
4/37
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Delay response time between rising edge of output current and rising edge of current sense
(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum current sense ratio drift vs load current(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Off-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TJ evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Low level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
High level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSO-16 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 28
PowerSO-16 thermal impedance junction ambient single pulse (one channel ON) . . . . . . 29
Thermal fitting model of a double channel HSD in PowerSO-16(1) . . . . . . . . . . . . . . . . . . 29
PowerSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSO-16 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PowerSO-16 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PowerSO-16 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DocID17362 Rev 6
VND5E006ASP-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1. Block diagram
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Table 1. Pin function
Name
VCC
Function
Battery connection.
OUTn
Power output.
GND
Ground connection.
INn
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
CSn
Analog current sense pin, delivers a current proportional to the load current.
CS_DIS
Active high CMOS compatible pin, to disable the current sense pin.
DocID17362 Rev 6
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36
Block diagram and pin description
VND5E006ASP-E
Figure 2. Configuration diagram (top view)
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287B
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Table 2. Suggested connections for unused and not connected pins
6/37
Connection /
pin
Current sense
N.C.
Output
Input
CS_DIS
Floating
Not allowed
X
X
X
X
To ground
Through 1 KΩ
resistor
X
Not allowed
Through 10 KΩ
resistor
Through 10 KΩ
resistor
DocID17362 Rev 6
VND5E006ASP-E
2
Electrical specifications
Electrical specifications
Figure 3. Current and voltage conventions
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2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in this section for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality documents.
Table 3. Absolute maximum ratings
Symbol
Value
Unit
DC supply voltage
28
V
Transient supply voltage (T < 400 ms, RLOAD > 0.5 Ω)
41
V
-VCC
Reverse DC supply voltage
16
V
IOUT
DC output current
Internally limited
A
-IOUT
Reverse DC output current
60
A
DC input current
-1 to 10
mA
DC current sense disable input current
-1 to 10
mA
VCC-41
+VCC
V
V
600
mJ
VCC
VCCPK
IIN
ICSD
Parameter
VCSENSE Current sense maximum voltage
EMAX
Maximum switching energy (single pulse)
(L = 1.4 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C;
IOUT = IlimL(Typ.))
DocID17362 Rev 6
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36
Electrical specifications
VND5E006ASP-E
Table 3. Absolute maximum ratings (continued)
Symbol
Parameter
Value
VESD
Electrostatic discharge (Human Body Model: R = 1.5 KΩ;
C = 100 pF)
– Input
– Current sense
– CS_DIS
– Output
– VCC
4000
2000
4000
5000
5000
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Maximum value
Unit
0.4
°C/W
See Figure 36
°C/W
Tj
Tstg
2.2
Unit
V
Thermal data
Table 4. Thermal data
Symbol
8/37
Parameter
Rthj-case
Thermal resistance junction-case (MAX)
(with one channel ON)
Rthj-amb
Thermal resistance junction-ambient
DocID17362 Rev 6
VND5E006ASP-E
2.3
Electrical specifications
Electrical characteristics
8 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified.
Table 5. Power section
Symbol
Parameter
Test conditions
VCC
Operating supply voltage
VUSD
VUSDhyst
Min.
Typ. Max. Unit
4.5
13
28
V
Undervoltage shutdown
3.5
4.5
V
Undervoltage shutdown
hysteresis
0.5
V
5
mΩ
IOUT = 10 A; Tj = 25 °C
RON
RON REV
Vclamp
IS
IOUT = 10 A; Tj = 150 °C
10
mΩ
IOUT = 10 A; VCC = 5 V; Tj = 25 °C
8
mΩ
Reverse battery on-state
resistance
VCC = -13 V; IOUT = -10 A;
Tj = 25 °C
6
mΩ
Clamp voltage
IS = 20 mA
46
52
V
Off-state; VCC = 13 V; Tj = 25 °C;
VIN = VOUT = VSENSE = VCSD = 0 V
2 (1)
5(1)
µA
On-state; VCC = 13 V; VIN = 5 V;
IOUT = 0 A
3.5
6.5
mA
0.01
3
µA
5
µA
On-state resistance
Supply current
IL(off1)
Off-state output current (2)
41
VIN=VOUT=0V; VCC=13V; Tj=25°C
0
VIN=VOUT=0V; VCC=13V; Tj=125°C
0
1. PowerMOS leakage included.
2. For each channel.
Table 6. Switching (VCC = 13 V; Tj = 25 °C)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
RL = 1.3 Ω (see Figure 6)
—
35
—
µs
td(off)
Turn-off delay time
RL = 1.3 Ω (see Figure 6)
—
20
—
µs
Turn-on voltage slope
RL = 1.3 Ω
—
See
Figure 27
—
V/µs
Turn-off voltage slope
RL = 1.3 Ω
—
See
Figure 28
—
V/µs
WON
Switching energy
losses during twon
RL = 1.3 Ω (see Figure 6)
—
2.5
—
mJ
WOFF
Switching energy
losses during twoff
RL = 1.3 Ω (see Figure 6)
—
1.2
—
mJ
(dVOUT/dt)o
n
(dVOUT/dt)o
ff
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Electrical specifications
VND5E006ASP-E
Table 7. Logic inputs
Symbol
Parameter
Test conditions
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Min.
VIN = 0.9 V
Typ.
Max.
Unit
0.9
V
1
µA
2.1
V
VIN = 2.1 V
10
0.25
IIN = 1 mA
Input clamp voltage
VCSDL
CS_DIS low level voltage
ICSDL
Low level CS_DIS current
VCSDH
CS_DIS high level voltage
ICSDH
High level CS_DIS current
VCSD(hyst
CS_DIS hysteresis voltage
V
5.5
IIN = -1 mA
7
-0.7
V
V
0.9
VCSD = 0.9 V
µA
V
1
µA
2.1
V
VCSD = 2.1 V
10
0.25
µA
V
)
VCSCL
CS_DIS clamp voltage
ICSD = 1 mA
5.5
ICSD = -1 mA
7
-0.7
V
V
Table 8. Protections and diagnostics(1)
Symbol
Parameter
Test conditions
IlimH
DC short circuit current
IlimL
Short circuit current
during thermal cycling
TTSD
Shutdown temperature
TRS
Thermal reset of status
VON
Max.
Unit
70
100
140
A
140
A
VCC = 13 V; TR < Tj < TTSD
Reset temperature
VDEMAG
Typ.
5 V < VCC < 24 V
TR
THYST
VCC = 13 V
Min.
25
150
175
TRS +
1
TRS +
5
A
200
°C
135
Thermal hysteresis
(TTSD-TR)
°C
7
Turn-off output voltage
clamp
IOUT = 2 A; VIN = 0; L = 6 mH
Output voltage drop
limitation
IOUT =1 A; Tj = -40 °C...150 °C
(see Figure 8)
VCC28
VCC31
°C
VCC35
25
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/37
DocID17362 Rev 6
°C
V
mV
VND5E006ASP-E
Electrical specifications
Table 9. Current sense (8 V < VCC < 18 V)
Symbol
Parameter
Test conditions
K0
IOUT/ISENSE
IOUT = 5 A; VSENSE = 0.5 V
Tj = -40 °C...150 °C
K1
IOUT/ISENSE
IOUT = 10 A; VSENSE = 0.5 V
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
dK1/K1(1)
K2
dK2/K2(1)
K3
dK3/K3(1)
ISENSE0
VSENSE
IOUT = 10 A; VSENSE = 0.5 V;
Current sense ratio drift VCSD = 0 V;
Tj = -40 °C...150 °C
IOUT = 15 A; VSENSE = 4 V
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
IOUT/ISENSE
IOUT = 15 A; VSENSE = 4 V;
Current sense ratio drift VCSD = 0 V;
Tj = -40 °C...150 °C
IOUT = 25 A; VSENSE = 4 V
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
IOUT/ISENSE
IOUT = 25 A; VSENSE = 4 V;
Current sense ratio drift VCSD = 0 V;
Tj = -40 °C...150 °C
Analog sense leakage
current
Max analog sense
output voltage
Min.
Typ.
Max.
8300
12640 17600
9200
9602
13220 17300
13220 16703
-13
13
Unit
%
9500 13120 16900
10408 13120 15907
-10
10
%
10600 12920 15600
11278 12920 14644
-7
7
%
IOUT = 0 A; VSENSE = 0 V;
VCSD = 5 V; VIN = 0 V;
Tj = -40 °C...150 °C
0
1
µA
VCSD = 0 V; VIN = 5 V;
Tj = -40 °C...150 °C
0
2
µA
IOUT = 10 A; VSENSE = 0 V;
VCSD = VIN = 5 V
0
1
µA
IOUT = 25 A; VCSD = 0 V
5
V
Analog sense output
VSENSEH(2) voltage in fault
conditions
VCC = 13 V; RSENSE = 10 KΩ
8
V
Analog sense output
ISENSEH(2) current in fault
conditions
VCC = 13 V; VSENSE = 5 V
7
mA
Delay response time
tDSENSE1H from falling edge of
CS_DIS pin
VSENSE < 4 V, 5 A < Iout < 25 A
ISENSE = 90 % of ISENSE max
(see Figure 4)
50
100
µs
Delay response time
tDSENSE1L from rising edge of
CS_DIS pin
VSENSE < 4 V, 5 A < Iout < 25 A
ISENSE = 10 % of ISENSE max
(see Figure 4)
5
20
µs
DocID17362 Rev 6
11/37
36
Electrical specifications
VND5E006ASP-E
Table 9. Current sense (8 V < VCC < 18 V) (continued)
Symbol
Parameter
Test conditions
Delay response time
tDSENSE2H from rising edge of
INPUT pin
VSENSE < 4 V, 5 A < Iout < 25 A
ISENSE = 90 % of ISENSE max
(see Figure 4)
Delay response time
between rising edge of
ΔtDSENSE2
output current and
H
rising edge of current
sense
VSENSE < 4V,
ISENSE = 90 % of ISENSEMAX,
IOUT = 90 % of IOUTMAX
IOUTMAX =10 (see Figure 7)
Delay response time
tDSENSE2L from falling edge of
INPUT pin
VSENSE < 4 V, 5 A < Iout < 25 A
ISENSE = 10 % of ISENSE max
(see Figure 4)
Min.
Typ.
Max.
Unit
110
600
µs
300
µs
250
µs
100
1. Parameter guaranteed by design; it is not tested.
2. Fault conditions includes: power limitation, overtemperature and open-load off-state detection.
Table 10. Open-load detection (8 V < VCC < 18 V)
Symbol
Parameter
Test conditions
Typ.
Max.
Unit
VOL
Open-load off-state
voltage detection
threshold
VIN = 0 V, 8 V < VCC < 18 V
2
—
4
V
IOL
Open-load on-state
current detection
threshold
VIN = 5 V, 8 V < VCC < 18 V
ISENSE = 5 µA
10
—
100
mA
180
—
1200
µs
-120
—
0
µA
—
20
µs
Output short circuit to
tDSTKON VCC detection delay at See Figure 5
turn off
12/37
Min.
IL(off2)
Off-state output current VIN = 0 V; VSENSE = 0 V
at VOUT = 4 V
VOUT rising from 0 V to 4 V
td_vol
Delay response from
output rising edge to
VSENSE rising edge in
open-load
VIN = 0 V; VOUT = 4 V
VSENSE = 90 % of VSENSEH
DocID17362 Rev 6
VND5E006ASP-E
Electrical specifications
Figure 4. Current sense delay characteristics
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Figure 5. Open-load off-state delay timing
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Figure 6. Switching characteristics
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DocID17362 Rev 6
13/37
36
Electrical specifications
VND5E006ASP-E
Figure 7. Delay response time between rising edge of output current and rising edge
of current sense (CS enabled)
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Figure 8. Output voltage drop limitation
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14/37
DocID17362 Rev 6
VND5E006ASP-E
Electrical specifications
Figure 9. IOUT/ISENSE vs IOUT
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Figure 10. Maximum current sense ratio drift vs load current(1)
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1. Parameter guaranteed by design; it is not tested.
DocID17362 Rev 6
15/37
36
Electrical specifications
VND5E006ASP-E
Table 11. Truth table
Input
Output
Sense (VCSD = 0 V)(1)
Normal operation
L
H
L
H
0
Nominal
Overtemperature
L
H
L
L
0
VSENSEH
Undervoltage
L
H
L
L
0
0
H
X
(no power limitation)
Cycling
(power limitation)
Nominal
Conditions
Overload
H
VSENSEH
Short circuit to GND
(Power limitation)
L
H
L
L
0
VSENSEH
Open-load off-state
(with external pull up)
L
H
VSENSEH
Short circuit to VCC
(external pull up
disconnected)
L
H
H
H
VSENSEH
< Nominal
Negative output voltage
clamp
L
L
0
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
16/37
DocID17362 Rev 6
VND5E006ASP-E
Electrical specifications
Table 12. Electrical transient requirements (part 1/3)
ISO 7637-2:
2004(E)
Test levels(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
Test Pulse
III
IV
1
-75 V
-100 V
5000
pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37 V
+50 V
5000
pulses
0.2 s
5s
50 μs, 2 Ω
3a
-100 V
-150 V
1h
90 ms
100 ms
0.1 μs, 50 Ω
3b
+75 V
+100 V
1h
90 ms
100 ms
0.1 μs, 50 Ω
4
-6 V
-7 V
1 pulse
100 ms, 0.01 Ω
5b(2)
+65 V
+87 V
1 pulse
400 ms, 2 Ω
1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy
allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy
along the time and to transfer a part of it to the load.
Table 13. Electrical transient requirements (part 2/3)
Test level results(1)
ISO 7637-2:
2004(E)
Test Pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b(2)(3)
C
C
1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy
allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy
along the time and to transfer a part of it to the load.
3. Suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in
Table 3: Absolute maximum ratings.
Table 14. Electrical transient requirements (part 3/3)
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure
to disturbance and cannot be returned to proper operation without replacing the
DocID17362 Rev 6
17/37
36
Electrical specifications
2.4
VND5E006ASP-E
Waveforms
Figure 11. Normal operation
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Figure 12. Overload or short to GND
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18/37
DocID17362 Rev 6
VND5E006ASP-E
Electrical specifications
Figure 13. Intermittent overload
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Figure 14. Off-state open-load with external circuitry
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DocID17362 Rev 6
19/37
36
Electrical specifications
VND5E006ASP-E
Figure 15. Short to VCC
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Figure 16. TJ evolution in overload or short to GND
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Figure 19. Input clamp voltage
Figure 20. Input high level voltage
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4
3.5
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3
2.5
2
1.5
1
0.5
0
-50
7F>&@
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0
25
50
75
100
125
150
175
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Figure 21. Input low level voltage
Figure 22. Input hysteresis voltage
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DocID17362 Rev 6
7F>&@
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21/37
36
Electrical specifications
VND5E006ASP-E
Figure 23. On-state resistance vs Tcase
Figure 24. On-state resistance vs VCC
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Figure 25. Undervoltage shutdown
Figure 26. ILIMH vs Tcase
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Figure 28. Turn-off voltage slope
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Figure 27. Turn-on voltage slope
7F>&@
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DocID17362 Rev 6
$* 9
VND5E006ASP-E
Electrical specifications
Figure 29. CS_DIS clamp voltage
Figure 30. Low level CS_DIS voltage
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Figure 31. High level CS_DIS voltage
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DocID17362 Rev 6
23/37
36
Application information
3
VND5E006ASP-E
Application information
Figure 32. Application schematic
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9&&
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Note:
Channel 2 has the same internal circuit as channel 1.
3.1
Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2 2004 (E) table.
3.2
MCU I/Os protection
When negative transients are present on the VCC line, the control pins are pulled negative to
approximately -1.5 V. ST suggests to insert a resistor (Rprot) in line to prevent the
microcontroller I/O pins from latching-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 1
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC - VIH) / IIHmax
Calculation example:
For VCCpeak = -1.5 V and Ilatchup ≥ 20 mA; VOHμC ≥ 4.5 V
75 Ω ≤ Rprot ≤ 240 kΩ.
Recommended values: Rprot = 10 kΩ, CEXT = 10 nF.
24/37
DocID17362 Rev 6
VND5E006ASP-E
3.3
Application information
Current sense and diagnostic
The current sense pin performs a double function (see Figure 33: Current sense and
diagnostic):
•
Current mirror of the load current in normal operation, delivering a current
proportional to the load one according to a known ratio KX.
The current ISENSE can be easily converted to a voltage VSENSE by means of an
external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5V
minimum (see parameter VSENSE in Table 9: Current sense (8 V < VCC < 18 V)). The
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8 V < VCC < 18 V)).
•
Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a
maximum current ISENSEH in case of the following fault conditions (refer to Truth table):
–
Power limitation activation
–
Overtemperature
–
Short to VCC in off-state
–
Open-load in off-state with additional external components.
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.
Figure 33. Current sense and diagnostic
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DocID17362 Rev 6
25/37
36
Application information
3.3.1
VND5E006ASP-E
Short to VCC and off-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
Off-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
For proper open-load detection in off-state, the external pull-up resistor must be selected
according to the following formula:
VOUT
Pull − up _ ON
=
RPD ⋅ VPU − RPU ⋅ RPD ⋅ I L (off 2)
RPU + RPD
> VOL max = 4V
For the values of VOLmin,VOLmax, and IL(off2) see Table 10: Open-load detection
(8 V < VCC < 18 V).
26/37
DocID17362 Rev 6
VND5E006ASP-E
3.4
Application information
Maximum demagnetization energy (VCC = 13.5 V)
Figure 34. Maximum turn-off current versus inductance
, $
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A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
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Note:
W
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
DocID17362 Rev 6
27/37
36
Package and PCB thermal data
VND5E006ASP-E
4
Package and PCB thermal data
4.1
PowerSO-16 thermal data
Figure 35. PowerSO-16 PC board(1)
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1. Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x
86mm, PCB thickness=1.6mm, Cu thickness=70μm (front and back side), Copper areas: from minimum
pad lay-out to 8cm2).
Figure 36. Rthj-amb vs PCB copper area in open box free air condition (one channel
ON)
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28/37
DocID17362 Rev 6
VND5E006ASP-E
Package and PCB thermal data
Figure 37. PowerSO-16 thermal impedance junction ambient single pulse (one
channel ON)
ZTH (°C/W)
100
Cu=8 cm2
Cu=2 cm2
Cu=foot print
10
1
0.1
0.0001
0.001
0.01
0.1
Ti
( )
Time
(s)
1
10
100
1000
AG00104V1
Figure 38. Thermal fitting model of a double channel HSD in PowerSO-16(1)
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1. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
DocID17362 Rev 6
29/37
36
Package and PCB thermal data
VND5E006ASP-E
Equation 2: pulse calculation formula
Z
THδ
where
= R
TH
⋅δ+Z
THtp
(1 – δ)
δ = tp ⁄ T
Table 15. Thermal parameters
2
30/37
Area/island (cm )
Footprint
2
8
R1=R7 (°C/W)
0.05
R2=R8 (°C/W)
0.4
R3 (°C/W)
1
R4 (°C/W)
7
R5 (°C/W)
12
10
8
R6 (°C/W)
22
18
12
C1=C7 (W.s/°C)
0.01
C2=C8 (W.s/°C)
0.1
C3 (W.s/°C)
1
C4 (W.s/°C)
2
C5 (W.s/°C)
3
4
7
C6 (W.s/°C)
5
6
12
DocID17362 Rev 6
VND5E006ASP-E
Package information
5
Package information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSO-16 mechanical data
Figure 39. PowerSO-16 package dimensions
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DocID17362 Rev 6
31/37
36
Package information
VND5E006ASP-E
Table 16. PowerSO-16 mechanical data
mm
Dim.
Min.
Typ.
Max.
A1
0
0.05
0.1
A2
3.4
3.5
3.6
A3
1.2
1.3
1.4
A4
0.15
0.2
0.25
a
0.2
b
0.27
0.35
0.43
c
0.23
0.27
0.32
D
9.4
9.5
9.6
D1
7.4
7.5
7.6
d
0
0.05
0.1
E (1)
13.85
14.1
14.35
E1
9.3
9.4
9.5
E2
7.3
7.4
7.5
E3
5.9
6.1
6.3
0.8
e
e1
5.6
F
0.5
G
1.2
L
0.8
1
R1
0.25
R2
T
32/37
1.1
0.8
2°
5°
T1
6° (typ.)
T2
10° (typ.)
DocID17362 Rev 6
8°
VND5E006ASP-E
5.3
Package information
Packing information
Figure 40. PowerSO-16 tube shipment (no suffix)
$
Base Q.ty
Bulk Q.ty
A
B
C (± 0.1)
Tube length (± 0.5)
&
50
1000
4.9
17.2
0.8
532
All dimensions are in mm.
%
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Figure 41. PowerSO-16 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
600
600
330
1.5
13
20.2
24.4
60
30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (+ 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
All dimensions are in mm.
24
4
24
1.5
1.5
11.5
6.5
2
End
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
AG00108V1
DocID17362 Rev 6
33/37
36
Package information
VND5E006ASP-E
Figure 42. PowerSO-16 suggested pad layout
$* 9
34/37
DocID17362 Rev 6
VND5E006ASP-E
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Order codes
Order codes
Table 17. Device summary
Order codes
Package
PowerSO-16
Tube
Tape and reel
VND5E006ASP-E
VND5E006ASPTR-E
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Revision history
7
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Revision history
Table 18. Document revision history
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Date
Revision
Changes
18-Apr-2010
1
Initial release.
02-Jul-2010
2
Updated Features list.
21-Jul-2010
3
Updated Table 9: Current sense (8 V < VCC < 18 V).
19-Jan-2011
4
Added Section 3.4: Maximum demagnetization energy
(VCC = 13.5 V)
Table 3: Absolute maximum ratings:
– EMAX: updated value and test condition
Table 4: Thermal data
– Added Rthj-case row
19-Sep-2013
5
Updated Disclaimer.
28-Oct-2013
6
Updated footnote 2 into the Table 12: Electrical transient
requirements (part 1/3) and Table 13: Electrical transient
requirements (part 2/3).
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VND5E006ASP-E
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