VND5E008MY-E
Double channel high-side driver with analog current sense
for automotive applications
Datasheet - production data
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shutdown
– Reverse battery protection with self switch
on of the Power MOSFET
– Electrostatic discharge protection
PowerSSO-36
Features
Applications
Max transient supply voltage
VCC
41 V
Operating voltage range
VCC
4.5 to 28 V
Typ on-state resistance (per ch.)
RON
8 mΩ
Current limitation (typ)
ILIMH
76 A
Off-state supply current
IS
2 µA(1)
1. Typical value with all loads connected
• General
– Inrush current active management by
power limitation
– Very low standby current
– 3.0V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– Compliant with European directive
2002/95/EC
– Proportional load current sense
– High current sense precision for wide
current range
– Very low current sense leakage
• Diagnostic functions
– Current sense disable
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
October 2013
This is information on a product in full production.
• All types of resistive, inductive and capacitive
loads
Description
The VND5E008MY-E is a double channel highside driver manufactured using
STMicroelectronics® proprietary VIPower® M0-5
technology and housed in PowerSSO-36
package. The device is designed to drive 12 V
automotive grounded loads, and to provide
protection and diagnostics. It also implements a
3 V and 5 V CMOS compatible interface for the
use with any microcontroller.
The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, overtemperature shut-off with auto
restart and overvoltage active clamp. A dedicated
analog current sense pin is associated with every
output channel providing enhanced diagnostic
functions including fast detection of overload and
short-circuit to ground through power limitation
indication and overtemperature indication.
The current sensing and diagnostic feedback of
the whole device can be disabled by pulling the
CS_DIS pin high to share the external sense
resistor with similar devices.
DocID018699 Rev 5
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www.st.com
Contents
VND5E008MY-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 25
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1
5
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/35
DocID018699 Rev 5
VND5E008MY-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current sense (8 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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3
List of figures
VND5E008MY-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
4/35
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Delay response time between rising edge of output current and rising edge of current sense
(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TJ evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Low level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
High level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 27
PowerSSO-36 thermal impedance junction ambient single pulse (one channel ON). . . . . 27
Thermal fitting model of a double channel HSD in PowerSSO-36 . . . . . . . . . . . . . . . . . . . 28
PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID018699 Rev 5
VND5E008MY-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1. Block diagram
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Table 1. Pin function
Name
VCC
OUT1,2
Function
Battery connection
Power output
GND
Ground connection
IN1,2
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state
CS1,2
Analog current sense pin, delivers a current proportional to the load current
CS_DIS
Active high CMOS compatible pin, to disable the current sense pin
DocID018699 Rev 5
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34
Block diagram and pin description
VND5E008MY-E
Figure 2. Configuration diagram (top view)
287
287
287
287
287
287
287
287
287
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,1
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Table 2. Suggested connections for unused and not connected pins
6/35
Connection / pin
Current Sense
N.C.
Output
Input
CS_DIS
Floating
Not allowed
X
X
X
X
To ground
Through 1 KΩ
resistor
X
Not
allowed
Through 10 KΩ
resistor
Through 10 KΩ
resistor
DocID018699 Rev 5
VND5E008MY-E
2
Electrical specifications
Electrical specifications
Figure 3. Current and voltage conventions
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2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 3. Absolute maximum rating
Symbol
Value
Unit
DC supply voltage
28
V
Transient supply voltage (T 0.5Ω)
41
V
Reverse DC supply voltage
16
V
Maximum supply voltage for full protection to short-circuit
(acc. AEC-Q100-012)
18
V
-IGND
DC reverse ground pin current
200
mA
IOUT
DC output current
Internally limited
A
-IOUT
Reverse DC output current
50
A
DC input current
-1 to 10
mA
DC current sense disable input current
-1 to 10
mA
VCC - 41
+VCC
V
V
260
mJ
VCC
VCCPK
-VCC
VCC_LSC
IIN
ICSD
Parameter
VCSENSE Current sense maximum voltage
EMAX
Maximum switching energy (single pulse)
(L = 0.85 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C;
IOUT = IlimL(Typ.))
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Electrical specifications
VND5E008MY-E
Table 3. Absolute maximum rating (continued)
Symbol
Value
Unit
VESD
Electrostatic discharge
(Human Body Model: R = 1.5 KΩ; C = 100 pF)
– VCC, OUTPUT
– INPUT, CS_DIS
– CURRENT SENSE
5000
4000
2000
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Max Value
Unit
0.85
°C/W
See Figure 33 in the
Thermal section
°C/W
Tj
Tstg
2.2
Parameter
Thermal data
Table 4. Thermal data
Symbol
8/35
Parameter
Rthj-case
Thermal resistance junction-case (MAX)
(with one channel ON)
Rthj-amb
Thermal resistance junction-ambient (MAX)
DocID018699 Rev 5
VND5E008MY-E
2.3
Electrical specifications
Electrical characteristics
8 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified
Table 5. Power section
Symbol
Parameter
Test conditions
VCC
Operating supply voltage
VUSD
VUSDhyst
Min. Typ. Max. Unit
4.5
13
28
V
Undervoltage shutdown
3.5
4.5
V
Undervoltage shutdown
hysteresis
0.5
V
8
mΩ
IOUT = 6 A; Tj = 25 °C
RON
RON REV
Vclamp
IS
IL(off)
On-state resistance
IOUT = 6 A; Tj = 150 °C
15
mΩ
IOUT = 6A; VCC = 5V; Tj = 25 °C
11
mΩ
Reverse battery on-state
resistance
VCC = -13 V; IOUT = -6 A; Tj = 25 °C
Clamp Voltage
IS = 20 mA
Supply current
Off-state output
current (2)
8
41
mΩ
46
52
V
Off-state; VCC = 13 V; Tj = 25 °C;
VIN = VOUT = VSENSE = VCSD = 0 V
2(1)
5(1)
µA
On-state; VCC = 13 V; VIN = 5 V;
IOUT = 0 A
3.5
6.5
mA
0.01
3
µA
5
µA
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25 °C
0
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C
1. PowerMOS leakage included.
2. For each channel.
Table 6. Switching (VCC = 13V; Tj = 25°C)
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
td(on)
Turn-on delay time
RL = 2.2 Ω (see Figure 7)
—
30
—
µs
td(off)
Turn-off delay time
RL = 2.2 Ω (see Figure 7)
—
15
—
µs
Turn-on voltage slope
RL = 2.2 Ω
—
See
Figure 20
—
V/µs
Turn-off voltage slope
RL = 2.2 Ω
—
See
Figure 21
—
V/µs
WON
Switching energy
losses during twon
RL = 2.2 Ω (see Figure 7)
—
1.2
—
mJ
WOFF
Switching energy
losses during twoff
RL = 2.2 Ω (see Figure 7)
—
0.43
—
mJ
(dVOUT/dt)
on
(dVOUT/dt)
off
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Electrical specifications
VND5E008MY-E
Table 7. Current sense (8 V < VCC < 18 V)
Symbol
K0
K1
dK1/K1(1)
K2
dK2/K2(1)
K3
dK3/K3(1)
ISENSE0
10/35
Parameter
Test conditions
IOUT/ISENSE
IOUT = 0.25 A; VSENSE = 0.5 V;
Tj = -40 °C...150 °C
IOUT/ISENSE
IOUT = 6 A; VSENSE = 0.5 V
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
IOUT = 6 A; VSENSE = 0.5 V
Current sense ratio drift VCSD = 0 V;
TJ= -40 °C to 150 °C
IOUT = 10 A; VSENSE = 4 V
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
IOUT/ISENSE
IOUT = 10 A; VSENSE = 4 V;
Current sense ratio drift VCSD = 0 V;
Tj = -40 °C to 150 °C
IOUT = 25 A; VSENSE = 4 V
Tj = -40 °C...150 °C
Tj = 25 °C...150 °C
IOUT/ISENSE
IOUT = 25 A; VSENSE = 4 V;
Current sense ratio drift VCSD= 0V;
Tj = -40 °C to 150 °C
Analog sense leakage
current
Min.
Typ.
Max.
3658
6000
8926
3910
4336
6000
6000
8928
8044
-12
4948
5298
12
6000
6000
-7
5455
5535
%
7372
6762
7
6000
6000
Unit
%
6762
6282
-5
5
%
IOUT = 0 A; VSENSE = 0 V;
VCSD = 5 V; VIN = 0 V;
Tj = -40 °C...150 °C
0
1
µA
VCSD = 0V; VIN = 5V;
Tj = -40 °C...150 °C
0
2
µA
IOUT = 6 A; VSENSE = 0 V;
VCSD = VIN = 5 V
0
1
µA
5
VSENSE
Max analog sense
output voltage
IOUT = 15 A; VCSD = 0 V
VSENSEH
Analog sense output
voltage in
overtemperature
condition(2)
VCC = 13 V; RSENSE = 10 KΩ
8
V
ISENSEH
Analog sense output
current in
overtemperature
condition(2)
VCC = 13 V; VSENSE = 5 V
9
mA
tDSENSE1H
Delay Response time
from falling edge of
CS_DIS pin
VSENSE < 4V, 1.5A < IOUT < 25A
ISENSE = 90% of ISENSE max
(see Figure 4)
50
100
µs
tDSENSE1L
Delay Response time
from rising edge of
CS_DIS pin
VSENSE < 4V, 1.5A < IOUT < 25A
ISENSE = 10% of ISENSE max
(see Figure 4)
5
20
µs
DocID018699 Rev 5
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VND5E008MY-E
Electrical specifications
Table 7. Current sense (8 V < VCC < 18 V) (continued)
Symbol
Parameter
tDSENSE2H
Test conditions
Delay Response time
from rising edge of
INPUT pin
VSENSE < 4V, 1.5A < IOUT < 25A
ISENSE = 90% of ISENSE max
(see Figure 4)
Delay response time
between rising edge of
ΔtDSENSE2H output current and
rising edge of current
sense
tDSENSE2L
Delay Response time
from falling edge of
INPUT pin
Min.
Typ.
Max.
Unit
70
300
µs
300
µs
250
µs
VSENSE < 4 V,
ISENSE = 90 % of ISENSEMAX,
IOUT = 90 % of IOUTMAX
IOUTMAX = 5 A (see Figure 10)
VSENSE < 4V, 1.5A < IOUT < 25A
ISENSE = 10% of ISENSE max
(see Figure 4)
100
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation and overtemperature.
Table 8. Protections and diagnostics(1)
Symbol
Parameter
Test conditions
VCC = 13 V
IlimH
DC Short circuit
current
IlimL
Short circuit current
VCC = 13V; TR < Tj < TTSD
during thermal cycling
TTSD
Shutdown
temperature
TR
Reset temperature
TRS
Thermal reset of
STATUS
THYST
VDEMAG
VON
Min.
Typ.
Max.
Unit
53
76
106
A
106
A
5 V < VCC < 18 V
21
150
175
TRS +
1
TRS +
5
A
200
°C
135
Thermal hysteresis
(TTSD-TR)
°C
7
Turn-off output voltage
IOUT = 2 A; VIN = 0; L = 6 mH
clamp
Output voltage drop
limitation
VCC29
IOUT = 0.4 A; Tj = -40 °C...150 °C
(see Figure 9)
°C
VCC32
°C
VCC36
25
V
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles
Table 9. Logic inputs
Symbol
Parameter
Test conditions
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
VIN = 0.9 V
DocID018699 Rev 5
Min.
Typ.
Max.
Unit
0.9
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1
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2.1
V
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Electrical specifications
VND5E008MY-E
Table 9. Logic inputs (continued)
Symbol
Parameter
Test conditions
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
CS_DIS low level voltage
ICSDL
Low level CS_DIS current
VCSDH
CS_DIS high level voltage
ICSDH
High level CS_DIS current
VCSD(hyst
CS_DIS hysteresis voltage
Max.
Unit
10
μA
0.25
V
5.5
IIN = -1 mA
VCSDL
Typ.
VIN = 2.1 V
IIN = 1 mA
Input clamp voltage
Min.
7
-0.7
V
V
0.9
V
1
μA
2.1
V
VCSD = 0.9 V
VCSD = 2.1 V
10
0.25
μA
V
)
VCSCL
CS_DIS clamp voltage
ICSD = 1 mA
5.5
ICSD = -1 mA
7
-0.7
Figure 4. Current sense delay characteristics
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VND5E008MY-E
Electrical specifications
Figure 5. IOUT/ISENSE vs IOUT
Figure 6. Maximum current sense ratio drift vs load current
dK/K [%]
20
15
10
A
5
0
-5
B
-10
-15
-20
0
5
10
15
Iout [A]
A: Max, Tj = -40 C to 150 C
Note:
20
25
30
B: Min, Tj = -40 C to 150 C
Parameter guaranteed by design; it is not tested.
DocID018699 Rev 5
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Electrical specifications
VND5E008MY-E
Table 10. Truth table
Input
Output
Sense (Vcsd = 0V)(1)
Normal operation
L
H
L
H
0
Nominal
Overtemperature
L
H
L
L
0
VSENSEH
Undervoltage
L
H
L
L
0
0
H
X
(no power limitation)
Cycling
(power limitation)
Nominal
Conditions
Overload
H
VSENSEH
Short circuit to GND
(Power limitation)
L
H
L
L
0
VSENSEH
Negative output voltage
clamp
L
L
0
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Figure 7. Switching characteristics
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Figure 8. Delay response time between rising edge of output current and rising edge
of current sense (CS enabled)
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Electrical specifications
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Table 11. Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test levels(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
Test pulse
III
IV
1
-75 V
-100 V
5000
pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37 V
+50 V
5000
pulses
0.2 s
5s
50 µs, 2 Ω
3a
-100 V
-150 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
+75 V
+100 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4
-6 V
-7 V
1 pulse
100 ms, 0.01 Ω
5b(2)
+65 V
+87 V
1 pulse
400 ms, 2 Ω
1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy
allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy
along the time and to transfer a part of it to the load.
Table 12. Electrical transient requirements (part 2)
Test level results(1)
ISO 7637-2:
2004(E)
Test pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b(2)(3)
C
C
1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b
2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy
allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy
along the time and to transfer a part of it to the load.
3. Suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in
Table 3: Absolute maximum rating.
Table 13. Electrical transient requirements (part 3)
16/35
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
DocID018699 Rev 5
VND5E008MY-E
2.4
Electrical specifications
Waveforms
Figure 10. Normal operation
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Electrical specifications
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Figure 12. Intermittent overload
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Figure 17. Input high level voltage
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Figure 19. Input hysteresis voltage
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Figure 20. On-state resistance vs Tcase
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Figure 21. On-state resistance vs VCC
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Figure 23. ILIMH vs Tcase
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Figure 25. Turn-off voltage slope
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Figure 26. CS_DIS clamp voltage
Figure 27. Low level CS_DIS voltage
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Application information
3
VND5E008MY-E
Application information
Figure 29. Application schematic
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Channel 2 has the same internal circuit as channel 1.
3.1
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCCPK max rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.2
MCU I/Os protection
When negative transients are present on the VCC line, the control pin is pulled negative to
approximately -1.5 V. ST suggests to insert a resistor (Rprot) in line to prevent the
microcontroller I/O pins from latching-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 1
-VCCpeak / Ilatchup ≤ Rprot ≤ (VOHμC - VIH) / IIHmax
Calculation example:
For VCCpeak = - 1.5 V; Ilatchup ≥ 20 mA; VOHμC ≥ 4.5 V
75 Ω ≤ Rprot ≤ 240 kΩ.
Recommended values: Rprot =10 kΩ, CEXT =10 nF.
22/35
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VND5E008MY-E
3.3
Application information
Current sense and diagnostic
The current sense pin performs a double function (see Figure 30: Current sense and
diagnostic):
•
Current mirror of the load current in normal operation, delivering a current
proportional to the load one according to a known ratio KX.
The current ISENSE can be easily converted to a voltage VSENSE by means of an
external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5V
minimum (see parameter VSENSE in Table 7: Current sense (8 V < VCC < 18 V)). The
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 7: Current sense (8 V < VCC < 18 V)).
•
Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a
maximum current ISENSEH in case of the following fault conditions (refer to
Table 10: Truth table):
–
Power limitation activation
–
Overtemperature
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.
DocID018699 Rev 5
23/35
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Application information
VND5E008MY-E
Figure 30. Current sense and diagnostic
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3.4
Application information
Maximum demagnetization energy (VCC = 13.5V)
Figure 31. Maximum turn-off current versus inductance
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