VND5E025AY-E
Double channel high-side driver with analog current sense
for automotive applications
Datasheet − production data
Features
Max transient supply voltage
VCC
Operating voltage range
VCC 4.5 V to 28 V
Typ on-state resistance (per ch.) RON
41V
25 mΩ
PowerSSO-36
– Inrush current active management by
power limitation
Current limitation (typ)
ILIMH
47 A
Off state supply current
IS
2 µA(1)
Applications
1. Typical value with all loads connected.
■
■
■
General
– Very low standby current
– 3 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– Compliance with European directive
2002/95/EC
– Very low current sense leakage
Diagnostic functions
– Proportional load current sense
– OFF-state open-load detection
– Current sense disable
– Thermal shutdown indication
– Output short to VCC detection
– Over load and short to ground (power
limitation) indication
Protection
– Undervoltage shutdown
– Over voltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Over temperature shutdown with
autorestart (thermal shutdown)
– Reverse battery protection with self switch
on of the Power MOSFET
– Electrostatic discharge protection
September 2013
This is information on a product in full production.
■
All types of resistive, inductive and capacitive
loads
Description
The VND5E025AY-E is a double-channel
high-side driver manufactured using
STMicroelectronics® proprietary VIPower®
M0-5 technology and housed in PowerSSO-36
package. The VND5E025AY-E is designed to
drive 12 V automotive grounded loads, and to
provide protection and diagnostics. It also
implements a 3 V and 5 V CMOS-compatible
interface for use with any microcontroller.
The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, overtemperature shut-off with autorestart and overvoltage active clamp.
A dedicated analog current sense pin is
associated with every output channel providing
enhanced diagnostic functions including fast
detection of overload and short-circuit to ground
through power limitation indication,
overtemperature indication, short-circuit to VCC
diagnosis.
The current sensing and diagnostic feedback of
the whole device can be disabled by pulling the
CS_DIS pin high to share the external sense
resistor with similar devices.
Doc ID 17703 Rev 4
1/37
www.st.com
1
Contents
VND5E025AY-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1
3.4
4
Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 28
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1
5
Short to VCC and off-state open-load detection . . . . . . . . . . . . . . . . . . . 26
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1
ECOPACK®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/37
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VND5E025AY-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current sense (8 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Open-load detection (8 V < VCC < 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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List of figures
VND5E025AY-E
List of figures
Figure 1.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2.
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3.
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4.
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5.
Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6.
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7.
Delay response time between rising edge of output current and rising edge of current sense
(CS enabled)14
Figure 8.
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9.
IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. TJ evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. High-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Low-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 23. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 28. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 29. Low-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. High-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 33. Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 34. PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 35. Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . . 30
Figure 36. PowerSSO-36 thermal impedance junction ambient single pulse (one channel on) . . . . . 30
Figure 37. Thermal fitting model of a double-channel HSD in PowerSSO-36 . . . . . . . . . . . . . . . . . . 31
Figure 38. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 39. PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 40. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4/37
Doc ID 17703 Rev 4
VND5E025AY-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
VCC
Reverse
Battery
Protection
Signal Clamp
Control & Diagnostic 2
Undervoltage
IN1
Control & Diagnostic 1
Power
Clamp
DRIVER
IN2
CH 1
VON
Limitation
Over
temp.
Current
Limitation
CS_
DIS
VSENSEH
CS1
Current
Sense
CS2
CH 2
Fault
OUT2
OUT1
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
LOGIC
GND
Table 1.
Pin function
Name
VCC
OUT1,2
Function
Battery connection
Power output
GND
Ground connection
IN1,2
Voltage controlled input pins with hysteresis, CMOS compatible. They controls
output switch state
CS1,2
Analog current sense pins, they deliver a current proportional to the load current
CS_DIS
Active high CMOS compatible pin, to disable the current sense pin
Doc ID 17703 Rev 4
5/37
Block diagram and pin description
Figure 2.
VND5E025AY-E
Configuration diagram (top view)
/$
/$
/$
/$
065
065
065
065
065
065
065
065
065
065
065
065
065
065
/$
/$
/$
/$
/$
/$
*/
*/
/$
/$
$4
$4
/$
/$
/$
/$
(/%
$4@%*4
5"#7 $$
("1($'5
Table 2.
Suggested connections for unused and not connected pins
Connection /
pin
Current sense
N.C.
Output
Input
CS_DIS
Floating
Not allowed
X(1)
X
X
X
To ground
Through 1 KΩ
resistor
X
Not allowed
Through 10 KΩ
resistor
Through 10 KΩ
resistor
1. X: do not care.
6/37
Doc ID 17703 Rev 4
VND5E025AY-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
VFn
OUT1
CS_DIS
VCSD
VOUT1
ISENSE1
IIN1
CS1
IN1
VIN1
VCC
IOUT1
ICSD
IOUT2
IIN2
VSENSE1
OUT2
IN2
ISENSE2
VIN2
VOUT2
CS2
GND
VSENSE2
IGND
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the Table 3 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions in table below for extended periods may affect device reliability.
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
41
V
-VCC
Reverse DC supply voltage
16
V
Maximum supply voltage for full protection to short-circuit
(AEC-Q100-012)
18
V
Internally limited
A
35
A
DC input current
-1 to 10
mA
DC current sense disable input current
-1 to 10
mA
VCC - 41
+VCC
V
V
29
mJ
VCC_LSC
IOUT
DC output current
-IOUT
Reverse DC output current
IIN
ICSD
VCSENSE Current sense maximum voltage
EMAX
Maximum switching energy (single pulse)
(L = 0.26 mH; RL = 0 Ω; VBAT = 13.5 V; Tjstart = 150°C;
IOUT = IlimL(Typ.))
Doc ID 17703 Rev 4
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Electrical specifications
Table 3.
Absolute maximum ratings (continued)
Symbol
Parameter
Unit
VESD
4000
2000
4000
5000
5000
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Maximum value
Unit
1.4
°C/W
See Figure 35 in the
thermal section
°C/W
Tstg
V
Thermal data
Table 4.
Symbol
Thermal data
Parameter
Rthj-case Thermal resistance junction-case (with one channel on)
Rthj-amb
8/37
Value
Electrostatic discharge
(human body model: R = 1.5 KΩ; C = 100 pF)
– IN
– CS
– CS_DIS
– OUT
– VCC
Tj
2.2
VND5E025AY-E
Thermal resistance junction-ambient (MAX)
Doc ID 17703 Rev 4
VND5E025AY-E
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for 8 V < VCC < 28 V; -40°C < Tj < 150°C, unless
otherwise specified.
Table 5.
Power section
Symbol
Parameter
VCC
Operating supply voltage
VUSD
VUSDhyst
Test conditions
Min.
Typ. Max.
4.5
13
28
V
Undervoltage shutdown
3.5
4.5
V
Undervoltage shutdown
hysteresis
0.5
IOUT = 3 A; Tj = 25°C
RON
RON REV
Vclamp
IS
IL(off)
Unit
ON-state resistance
25
IOUT = 3 A; Tj = 150°C
50
IOUT = 3 A; VCC = 5 V; Tj = 25°C
35
Reverse battery
ON-state resistance
VCC = -13 V; IOUT = -3 A;
Tj = 25°C
25
Clamp voltage
IS = 20 mA
Supply current
OFF-state
output current (2)
V
41
mΩ
mΩ
46
52
V
Off-state: VCC = 13 V;Tj = 25°C;
VIN = VOUT = VSENSE = VCSD = 0 V
2(1)
5(1)
µA
On-state: VCC = 13 V; VIN = 5 V;
IOUT = 0 A
3.5
6.5
mA
0.01
3
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25°C
0
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C
0
µA
5
1. PowerMOS leakage included.
2. For each channel.
Table 6.
a
Symbol
Switching (VCC = 13 V; Tj = 25 °C)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
RL = 4.3 Ω (see Figure 6)
—
20
—
µs
td(off)
Turn-off delay time
RL = 4.3 Ω (see Figure 6)
—
20
—
µs
(dVOUT/dt)on
Turn-on voltage
slope
RL = 4.3 Ω
—
See
Figure 26
—
V/µs
(dVOUT/dt)off
Turn-off voltage
slope
RL = 4.3 Ω
—
See
Figure 27
—
V/µs
WON
Switching energy
losses during twon
RL = 4.3 Ω (see Figure 6)
—
0.25
—
mJ
WOFF
Switching energy
losses during twoff
RL = 4.3 Ω (see Figure 6)
—
0.3
—
mJ
Doc ID 17703 Rev 4
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Electrical specifications
Table 7.
)
Symbol
K0
K1
dK1/K1(1)
K2
dK2/K2(1)
K3
dK3/K3(1)
ISENSE0
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VND5E025AY-E
Current sense (8 V < VCC < 18 V)
Parameter
Test conditions
Min. Typ. Max. Unit
IOUT/ISENSE
IOUT = 0.5 A; VSENSE = 0.5 V
Tj = -40°C to 150°C
IOUT/ISENSE
IOUT = 2 A; VSENSE = 0.5 V
Tj = -40°C to 150°C
Tj = 25°C to 150°C
Current sense ratio drift
IOUT = 2 A; VSENSE = 0.5 V;
VCSD = 0 V;
Tj = -40°C to 150°C
IOUT/ISENSE
IOUT = 3 A; VSENSE = 4 V
Tj = -40 °C to 150 °C
Tj = 25 °C to 150 °C
Current sense ratio drift
IOUT = 3 A; VSENSE = 4 V;
VCSD = 0 V;
Tj = -40°C to 150°C
IOUT/ISENSE
IOUT = 10 A; VSENSE = 4 V
Tj = -40°C to 150°C
Tj = 25°C to 150°C
Current sense ratio drift
IOUT = 10 A; VSENSE = 4 V;
VCSD = 0 V;
Tj = -40°C to 150°C
-3
3
IOUT = 0 A; VSENSE = 0 V;
VCSD = 5 V; VIN = 0 V;
Tj = -40°C to 150°C
0
1
IOUT = 0 A; VSENSE = 0 V;
VCSD = 0 V; VIN = 5 V;
Tj = -40°C to 150°C
0
2
IOUT = 3 A; VSENSE = 0 V;
VCSD = VIN = 5 V;
0
1
IOUT = 15 A; VCSD = 0 V
5
Analog sense leakage
current
1000 2900 5000
1900 3000 3810
2240 3000 3520
-9
9
%
2230 3000 3550
2460 3000 3350
-6
6
%
2710 2900 3150
2780 2900 3080
%
µA
VSENSE
Max analog sense output
voltage
VSENSEH
Analog sense output
VCC = 13 V; RSENSE = 10 KΩ
voltage in fault condition(2)
8
V
ISENSEH
Analog sense output
VCC = 13 V; VSENSE = 5 V
current in fault condition(2)
9
mA
tDSENSE1H
VSENSE < 4 V;
Delay response time from 0.5 A < IOUT < 10 A;
falling edge of CS_DIS pin ISENSE = 90% of ISENSE max
(see Figure 4)
20
100
µs
tDSENSE1L
VSENSE < 4 V;
Delay response time from 0.5 A < IOUT < 10 A;
rising edge of CS_DIS pin ISENSE = 10 % of ISENSE max
(see Figure 4)
5
20
µs
Doc ID 17703 Rev 4
V
VND5E025AY-E
Table 7.
Electrical specifications
Current sense (8 V < VCC < 18 V) (continued)
Symbol
Parameter
Test conditions
tDSENSE2H
Delay response time from
rising edge of
IN pin
Delay response time
between rising edge of
ΔtDSENSE2H
output current and rising
edge of current sense
tDSENSE2L
Delay response time from
falling edge of
IN pin
Min. Typ. Max. Unit
VSENSE < 4 V;
0.5 A < IOUT < 10 A;
ISENSE = 90 % of ISENSE max
(see Figure 4)
70
VSENSE < 4V;
ISENSE = 90 % of ISENSEMAX,
IOUT = 90 % of IOUTMAX
IOUTMAX = 3 A (see Figure 7)
VSENSE < 4 V;
0.5 A < IOUT < 10 A;
ISENSE = 10 % of ISENSE max
(see Figure 4)
5
300
µs
100
µs
50
µs
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open-load OFF-state detection.
Table 8.
Open-load detection (8 V < VCC < 18 V)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VOL
Open-load off-state voltage
detection threshold
VIN = 0 V; 8 V < VCC < 18 V
2
—
4
V
IOL
Open-load on-state current
detection threshold
VIN = 5 V;
8 V < VCC < 18 V;
ISENSE = 5 µA
—
45
mA
Output short circuit to Vcc
detection delay at turn off
See Figure 5
—
1200
µs
—
20
µs
—
0
µA
tDSTKON
180
td_vol
Delay response from output
VIN = 0 V; VOUT = 4 V;
rising edge to VSENSE rising
VSENSE = 90 % of VSENSEH
edge in open-load
ILOFF2
Off-state output current
Table 9.
Symbol
VOUT = 4 V
-75
Protections and diagnostics(1)
Parameter
Test conditions
VCC = 13 V
IlimH
DC short-circuit
current
IlimL
Short-circuit current
VCC = 13 V; TR < Tj < TTSD
during thermal cycling
TTSD
Shutdown
temperature
TR
Reset temperature
TRS
Thermal reset of
status
Min.
Typ.
Max.
Unit
33
47
66
A
5 V < VCC < 18 V
66
12
150
175
TRS + 1
TRS + 5
135
Doc ID 17703 Rev 4
A
200
°C
°C
°C
11/37
Electrical specifications
Table 9.
Symbol
THYST
VND5E025AY-E
Protections and diagnostics(1) (continued)
Parameter
Test conditions
Thermal hysteresis
(TTSD - TR)
IOUT = 2 A; VIN = 0 V;
L
= 6 mH; Tj = -40°C
Turn-off output voltage
VDEMAG
clamp
I
= 2 A; V = 0;
OUT
IN
L = 6 mH; 25°C < Tj < 150°C
VON
Min.
Max.
Unit
7
°C
VCC - 39 VCC - 46 VCC - 52
V
VCC - 41 VCC - 46 VCC - 52
V
25
mV
IOUT = 0.1 A;
Tj = -40°C to150°C
(see Figure 8)
Output voltage drop
limitation
Typ.
1. To ensure long term reliability under heavy overload or short-circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Table 10.
Symbol
Parameter
VIL
Low-level input voltage
IIL
Low-level input current
VIH
High-level input voltage
IIH
High-level input current
VI(hyst)
Input hysteresis voltage
VICL
Test conditions
VIN = 0.9 V
Min.
ICSDL
Low-level CS_DIS current
VCSDH
High-level CS_DIS voltage
ICSDH
High-level CS_DIS current
VCSD(hyst)
CS_DIS hysteresis voltage
CS_DIS clamp voltage
Max.
Unit
0.9
V
1
µA
2.1
V
10
0.25
7
V
-0.7
0.9
VCSD = 0.9 V
µA
2.1
V
10
0.25
ICSD = -1 mA
Doc ID 17703 Rev 4
V
1
VCSD = 2.1 V
ICSD = 1 mA
µA
V
5.5
IIN = -1 mA
Low-level CS_DIS voltage
Typ.
VIN = 2.1 V
IIN = 1 mA
Input clamp voltage
VCSDL
VCSCL
12/37
Logic inputs
µA
V
5.5
7
V
-0.7
VND5E025AY-E
Electrical specifications
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
CURRENT SENSE
tDSENSE2H
Figure 5.
tDSENSE1L
tDSENSE1H
tDSENSE2L
Open-load off-state delay timing
OUTPUT STUCK TO VCC
VIN
VOUT > VOL
VSENSEH
VCS
tDSTKON
Figure 6.
Switching characteristics
VOUT
tWon
tWoff
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
tr
10%
tf
t
INPUT
td(on)
td(off)
t
Doc ID 17703 Rev 4
13/37
Electrical specifications
Figure 7.
VND5E025AY-E
Delay response time between rising edge of output current and rising
edge of current sense (CS enabled)
VIN
ΔtDSENSE2H
t
IOUT
IOUTMAX
90% IOUTMAX
t
ISENSE
ISENSEMAX
90% ISENSEMAX
t
Figure 8.
Output voltage drop limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Iout
Von/Ron(T)
14/37
Doc ID 17703 Rev 4
VND5E025AY-E
Electrical specifications
Figure 9.
IOUT/ISENSE vs IOUT
,RXW,VHQVH
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&
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(
,RXW>$@
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Figure 10. Maximum current sense ratio drift vs load current
G..>@
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%0LQ7M &WR&
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1. Parameter guaranteed by design; it is not tested.
Doc ID 17703 Rev 4
15/37
Electrical specifications
Table 11.
VND5E025AY-E
Truth table
Input
Output
Sense (VCSD = 0 V)(1)
Normal operation
L
H
L
H
0
Nominal
Overtemperature
L
H
L
L
0
VSENSEH
Undervoltage
L
H
L
L
0
0
H
X
(no power limitation)
Cycling
(power limitation)
Nominal
Conditions
Overload
H
VSENSEH
Short-circuit to GND
(Power limitation)
L
H
L
L
0
VSENSEH
short-circuit to VCC
(external pull up
disconnected)
L
H
H
H
VSENSEH
< Nominal
Negative output voltage
clamp
L
L
0
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
16/37
Doc ID 17703 Rev 4
VND5E025AY-E
Electrical specifications
Table 12.
ISO 7637-2:
2004(E)
Electrical transient requirements (part 1)
Test levels(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
Test pulse
III
IV
1
-75 V
-100 V
5000
pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37 V
+50 V
5000
pulses
0.2 s
5s
50 µs, 2 Ω
3a
-100 V
-150 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
+75 V
+100 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4
-6 V
-7 V
1 pulse
100 ms, 0.01 Ω
5b(2)
+65 V
+87 V
1 pulse
400 ms, 2 Ω
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 13.
Electrical transient requirements (part 2)
Test level results(1)
ISO 7637-2:
2004(E)
Test pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
(2)(3)
C
C
5b
1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b
2. Valid in case of external load dump clamp: 40 V maximum referred to ground.
3. Suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in
Table 3: Absolute maximum ratings.
Table 14.
Electrical transient requirements (part 3)
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 17703 Rev 4
17/37
Electrical specifications
2.4
VND5E025AY-E
Waveforms
Figure 11.
Normal operation
1RUPDORSHUDWLRQ
,1387
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1RPLQDOORDG
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Figure 12. Overload or short to GND
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, /LP/!
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18/37
Doc ID 17703 Rev 4
VND5E025AY-E
Electrical specifications
Figure 13. Intermittent overload
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,/LP/ !
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Figure 14. Short to VCC
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Doc ID 17703 Rev 4
19/37
Electrical specifications
VND5E025AY-E
Figure 15. TJ evolution in overload or short to GND
7- HYROXWLRQLQ
2YHUORDGRU6KRUWWR*1'
,1387
6HOIOLPLWDWLRQRIIDVWWKHUPDOWUDQVLHQWV
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,ORII>Q$@
9LQ 9
7F> &@
7F> &@
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Figure 18. Input clamp voltage
Figure 19. High-level input voltage
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,LQ P$
7F> &@
7F>&@
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Figure 20. Low-level input voltage
Figure 21. Input hysteresis voltage
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9LO>9@
7F> &@
*$3*&)7
Doc ID 17703 Rev 4
7F> &@
*$3*&)7
21/37
Electrical specifications
VND5E025AY-E
Figure 22. On-state resistance vs Tcase
Figure 23. On-state resistance vs VCC
5RQ>P2KP@
5RQ>P2KP@
7F &
7F &
,RXW $
9FF 9
7F &
7F &
9FF>9@
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Figure 24. Undervoltage shutdown
Figure 25. ILIMH vs Tcase
9XVG>9@
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*$3*&)7
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Figure 26. Turn-on voltage slope
Figure 27. Turn-off voltage slope
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22/37
7F> &@
7F> &@
7F> &@
*$3*&)7
Doc ID 17703 Rev 4
*$3*&)7
VND5E025AY-E
Electrical specifications
Figure 28. CS_DIS clamp voltage
Figure 29. Low-level CS_DIS voltage
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Figure 30. High-level CS_DIS voltage
9FVGK>9@
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*$3*&)7
Doc ID 17703 Rev 4
23/37
Application information
3
VND5E025AY-E
Application information
Figure 31. Application schematic
9
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0&8
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287
5SURW
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*1'
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1. Channel 2 has the same internal circuit as channel 1.
3.1
Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCCPK max rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.2
MCU I/Os protection
When negative transients are present on the VCC line, the control pins are pulled negative to
approximately -1.5 V.
ST suggests the insertion of resistors (Rprot) in the lines to prevent the microcontroller I/O
pins from latching up.
The values of these resistors provide a compromise between the leakage current of the
microcontroller, the current required by the HSD I/Os (input levels compatibility) and the
latch-up limit of the microcontroller I/Os.
24/37
Doc ID 17703 Rev 4
VND5E025AY-E
Application information
Equation 1
-VCCpeak / Ilatchup ≤ Rprot ≤ (VOHµC - VIH) / IIHmax
Calculation example:
For VCCpeak = -1.5 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
75 Ω ≤ Rprot ≤ 240 kΩ.
Recommended values: Rprot =10 kΩ, CEXT = 10 nF
3.3
Current sense and diagnostic
The current sense pin performs a double function (see Figure 32: Current sense and
diagnostic):
●
Current mirror of the load current in normal operation, delivering a current
proportional to the load one according to a known ratio KX.
The current ISENSE can be easily converted to a voltage VSENSE by means of an
external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5 V
minimum (see parameter VSENSE in Table 7: Current sense (8 V < VCC < 18 V)). The
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 7: Current sense (8 V < VCC < 18 V)).
●
Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a
maximum current ISENSEH in case of the following fault conditions (refer to
Table 11: Truth table):
–
Power limitation activation
–
Over temperature
–
Short to VCC in off-state
–
Open-load in off-state with additional external components.
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high-impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.
Doc ID 17703 Rev 4
25/37
Application information
VND5E025AY-E
Figure 32. Current sense and diagnostic
938
9%$7
9&&
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9
38B &0'
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3.3.1
Short to VCC and off-state open-load detection
Short to VCC
A short-circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device OFF-state. Small or no current is delivered by the current sense
during the ON-state depending on the nature of the short-circuit.
Off-state open-load with external circuitry
Detection of an open load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
An external pull-down resistor RPD connected between output and GND is mandatory to
avoid misdetection in case of floating outputs in off-state (see Figure 32: Current sense and
diagnostic).
26/37
Doc ID 17703 Rev 4
VND5E025AY-E
Application information
RPD must be selected in order to ensure VOUT < VOLmin unless pulled-up by the external
circuitry:
Equation 2
V OUT
Pull-up_OFF
= R PD ⋅ I L(off2)f < V OLmin = 2V
RPD ≤ 22 kΩ is recommended.
For proper open load detection in off-state, the external pull-up resistor must be selected
according to the following formula:
Equation 3
V OUT
( R PD ⋅ V PU ) – ( R PU ⋅ R PD ⋅ I L(off2)r )
= ----------------------------------------------------------------------------------------------- > V OLmax = 4V
( R PU + R PD )
Pull-up_ON
For the values of VOLmin,VOLmax, IL(off2)r and IL(off2)f (see Table 8: Open-load detection
(8 V < VCC < 18 V)).
Doc ID 17703 Rev 4
27/37
Application information
3.4
VND5E025AY-E
Maximum demagnetization energy (VCC = 13.5 V)
Figure 33. Maximum turn off current versus inductance
A: Tjstart = 150 °C single pulse
B: Tjstart = 100 °C repetitive pulse
C: Tjstart = 125 °C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
1. Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not
exceed the temperature specified above for curves A and B.
28/37
Doc ID 17703 Rev 4
VND5E025AY-E
Package and PCB thermal data
4
Package and PCB thermal data
4.1
PowerSSO-36 thermal data
Figure 34. PowerSSO-36 PC board
1. Layout condition of Rth and Zth measurements (Board finish thickness 1.6 mm +/- 10%; Board double
layer; Board dimension 129 mm x 60 mm; Board Material FR4; Cu thickness 0.070 mm; Thermal vias
separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm; Footprint
dimension 4.1 mm x 6.5 mm).
Doc ID 17703 Rev 4
29/37
Package and PCB thermal data
VND5E025AY-E
Figure 35. Rthj-amb vs PCB copper area in open box free air condition (one channel
on)
Figure 36. PowerSSO-36 thermal impedance junction ambient single pulse (one
channel on)
Equation 4: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
30/37
Doc ID 17703 Rev 4
VND5E025AY-E
Package and PCB thermal data
Figure 37. Thermal fitting model of a double-channel HSD in PowerSSO-36
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 15.
Thermal parameters
Area/island (cm2)
Footprint
R1 = R7 (°C/W)
0.3
R2 = R8 (°C/W)
0.9
R3 (°C/W)
5
R4 (°C/W)
8
R5 (°C/W)
2
8
18
10
10
R6 (°C/W)
27
23
14
C1 = C7 (W.s/°C)
0.001
C2 = C8 (W.s/°C)
0.005
C3 (W.s/°C)
0.04
C4 (W.s/°C)
0.5
C5 (W.s/°C)
1
2
2
C6 (W.s/°C)
3
6
9
Doc ID 17703 Rev 4
31/37
Package information
VND5E025AY-E
5
Package information
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSSO-36 mechanical data
Figure 38. PowerSSO-36 package dimensions
32/37
Doc ID 17703 Rev 4
VND5E025AY-E
Package information
Table 16.
PowerSSO-36 mechanical data
l
millimeters
Symbol
Min
Typ
Max
A
2.15
-
2.45
A2
2.15
-
2.35
a1
0
-
0.1
b
0.18
-
0.36
c
0.23
-
0.32
D
10.10
-
10.50
E
7.4
-
7.6
e
-
0.5
-
e3
-
8.5
-
F
-
2.3
-
G
-
-
0.1
H
10.1
-
10.5
h
-
-
0.4
k
0°
-
8°
L
0.55
-
0.85
M
-
4.3
-
N
-
-
10°
O
-
1.2
Q
-
0.8
-
S
-
2.9
-
T
-
3.65
-
U
-
1.0
-
X(1)
4.3
-
5.2
Y(1)
6.9
-
7.5
1. Corresponding to internal variation C.
Doc ID 17703 Rev 4
33/37
Package information
5.3
VND5E025AY-E
Packing information
Figure 39. PowerSSO-36 tube shipment (no suffix)
C
Base q.ty
Bulk q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 40. PowerSSO-36 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base q.ty
Bulk q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
Tape hole spacing
Component spacing
Hole diameter
Hole diameter
Hole position
Compartment depth
Hole spacing
All dimensions are in mm.
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
Start
Top
cover
tape
No components
Components
Empty components pockets
saled with cover tape.
User direction of feed
34/37
Doc ID 17703 Rev 4
No components
500mm min
500mm min
VND5E025AY-E
6
Device summary
Device summary
Table 17.
Device summary
Order codes
Package
PowerSSO-36
Tube
Tape and reel
VND5E025AY-E
VND5E025AYTR-E
Doc ID 17703 Rev 4
35/37
Revision history
7
VND5E025AY-E
Revision history
Table 18.
36/37
Document revision history
Date
Revision
Changes
29-Jul-2010
1
Initial release.
05-Aug-2010
2
Updated following figures:
– Figure 35: Rthj-amb vs PCB copper area in open box free air
condition (one channel on)
– Figure 36: PowerSSO-36 thermal impedance junction ambient
single pulse (one channel on)
Updated Table 15: Thermal parameters
19-Jul-2012
3
Changed document status from “Preliminary data“ to “Production
data“
19-Sep-2013
4
Updated Disclaimer
Doc ID 17703 Rev 4
VND5E025AY-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
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