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VND5T100AJTR-E

VND5T100AJTR-E

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    LSOP

  • 描述:

    IC PWR DRVR N-CHAN 1:1 PWRSSO12

  • 数据手册
  • 价格&库存
VND5T100AJTR-E 数据手册
VND5T100AJ-E Datasheet Double channel high-side driver with analog current sense for 24 V automotive applications Features Description 12 1 PowerSSO-12 Parameter Value Max. transient supply voltage VCC 58 V Operating voltage range VCC 8 to 36 V Typ. on-state resistance (per channel) RON 100 mΩ Current limitation (typ.) ILIM 22 A Off-state supply current IS 2 µA(1) 1. Typical value with all loads connected. Product status link • • VND5T100AJ-E Product summary Order code VND5T100AJ-ETR Package PowerSSO-12 Packing Tape and reel • • AEC-Q100 qualified General – Very low standby current – 3.0 V CMOS compatible input – Optimized electromagnetic emission – Very low electromagnetic susceptibility – Compliant with European directive 2002/95/EC – Fault reset standby pin (FR_Stby) Diagnostic functions – Proportional load current sense – High current sense precision for wide range currents – Off-state openload detection – Output short to VCC detection – Overload and short to ground latch-off – Thermal shutdown latch-off – Very low current sense leakage Protections – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss of VCC – – Thermal shutdown Electrostatic discharge protection Applications • All types of resistive, inductive and capacitive loads DS7125 - Rev 4 - June 2022 For further information contact your local STMicroelectronics sales office. www.st.com VND5T100AJ-E Description The VND5T100AJ-E is a monolithic device made using STMicroelectronics VIPower technology, intended for driving resistive or inductive loads with one side connected to the ground. Active VCC pin voltage clamp protects the device against low energy spikes. The device integrates an analog current sense, which delivers a current proportional to the load current. Fault conditions such as overload, overtemperature, or short to VCC are reported via the current sense pin. Output current limitation protects the device in overload conditions. The device latches off in case of overload or thermal shutdown. The device is reset by a low level pass on the fault reset standby pin. A permanent low level on the inputs and on the fault reset standby pins disables all outputs and sets the device in standby mode. DS7125 - Rev 4 page 2/31 VND5T100AJ-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram VCC Signal Clamp Control & Diagnostic 2 Undervoltage IN1 Control & Diagnostic 1 Power Clamp DRIVER IN2 CH1 VON Limitation Over Temperature Current Limitation OFF-state Open-load FR_Stby VSENSEH CS1 Current Sense CS2 CH2 OUT2 LOGIC OUT1 OVERLOAD PROTECTION (ACTIVE POWER LIMITATION) GND GAPGCFT00643 Table 1. Pin function Name VCC OUT1, 2 Function Battery connection. Power outputs. GND Ground connection. IN1, 2 Voltage controlled input pins with hysteresis, CMOS compatible. They control output switch state. CS1, 2 Analog current sense pins, they deliver a current proportional to the load current. FR_Stby In case of latch-off for overtemperature/overcurrent condition, a low pulse on the FR_Stby pin is needed to reset the channel. The device enters in standby mode if all inputs and the FR_Stby pin are low. DS7125 - Rev 4 page 3/31 VND5T100AJ-E Block diagram and pin description Figure 2. Configuration diagram PowerSSO-12 (top view) TAB = VCC CS1 1 12 VCC IN1 2 11 OUT1 FR_STBY 3 10 OUT1 GND 4 9 OUT2 IN2 5 8 OUT2 CS2 6 7 VCC PowerSSO-12 GAPGCFT000109 Table 2. Suggested connections for unused and not connected pins Connection/pin CurrentSense NC Output Input FR_Stby Floating Not allowed X(1) X X X To ground Through 10 kΩ resistor X Not allowed Through 10 kΩ resistor Through 10 kΩ resistor 1. X: do not care. DS7125 - Rev 4 page 4/31 VND5T100AJ-E Electrical specification 2 Electrical specification Figure 3. Current and voltage conventions IS VCC IFR_Stby OUTn FR_Stby VFR_Stby IINn CSn INn VINn VCC VFn IOUTn VOUTn ISENSEn VSENSEn GND IGND GAPGCFT00195_v2 2.1 Absolute maximum ratings Stressing the device above the ratings listed in the Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions reported in this section for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Value Unit VCC DC supply voltage 58 V -VCC Reverse DC supply voltage 0.3 V -IGND DC reverse ground pin current 200 mA IOUT DC output current Internally limited A -IOUT Reverse DC output current 20 A DC input current -1 to 10 mA IFR_Stby Fault reset standby DC input current -1 to 1.5 mA -ICSENSE DC reverse CS pin current 200 mA VCSENSE Current sense maximum voltage (VCC - 58) to VCC V IIN EMAX Maximum switching energy (L = 1.9 mH; VBAT = 32 V; TJstart = 150 °C; IOUT = IlimL (typ.)) 70 mJ Lsmax Maximum stray inductance in short circuit condition RL = 300 mΩ, VBAT = 32 V, TJstart = 150 °C, IOUT = IlimH (max.) 40 μH VESD VESD TJ DS7125 - Rev 4 Parameter Electrostatic discharge (human body model: R = 1.5 kΩ, C = 100 pF) Charge device model (CDM-AEC-Q100-011) Junction operating temperature IN1, 2 4000 CS1, 2 2000 FR_Stby 4000 OUT1, 2 5000 VCC 5000 V 750 V -40 to 150 °C page 5/31 VND5T100AJ-E Thermal data Symbol Tstg 2.2 Parameter Storage temperature Value Unit -55 to 150 °C Thermal data Table 4. Thermal data Symbol DS7125 - Rev 4 Parameter RthJC Thermal resistance, junction-to-case (with one channel ON) RthJA Thermal resistance, junction-to-ambient Value Unit 6 °C/W See Figure 27 °C/W page 6/31 VND5T100AJ-E Electrical characteristics 2.3 Electrical characteristics 8 V < VCC < 36 V, -40 °C < TJ < 150 °C, unless otherwise specified. Table 5. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit 8 24 36 V 5 V VCC Operating supply voltage VUSD Undervoltage shutdown 3.5 Undervoltage shutdown hysteresis 0.5 VUSDhyst RON Vclamp IOUT = 1.5 A, TJ = 25 °C On-state resistance(1) 100 IOUT = 1.5 A, TJ = 150 °C IS = 20 mA Clamp voltage V 200 58 mΩ 64 70 V 2(2) 5(2) µA 4.2 6 mA 0.01 3 Off-state, VCC = 24 V, TJ = 25 °C, VIN = VOUT = VSENSE = 0 V, IS VFR_Stby = 0 V Supply current On-state, VCC = 24 V, VIN = 5 V, IOUT = 0 A VIN = VOUT = 0 V, IL(off) VCC = 24 V, TJ = 25 °C Off-state output current VIN = VOUT = 0 V, VCC = 24 V, TJ = 125 °C VF Output - VCC diode voltage 0 µA 0 5 -IOUT = 1.5 A, TJ = 150 °C 0.7 V Max. Unit 1. For each channel. 2. Power MOSFET leakage included. Table 6. Switching (VCC = 24 V, TJ = 25 °C) Symbol Parameter Test conditions Min. Typ. td(on) Turn-on delay time RL = 16 Ω 27 µs td(off) Turn-off delay time RL = 16 Ω 38 µs (dVOUT/dt)(on) Turn-on voltage slope RL = 16 Ω 1 V/µs (dVOUT/dt)(off) Turn-off voltage slope RL = 16 Ω 0.65 V/µs WON Switching energy losses during twon RL = 16 Ω 0.23 mJ WOFF Switching energy losses during twoff RL = 16 Ω 0.26 mJ Table 7. Logic inputs Symbol DS7125 - Rev 4 Parameter VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage Test conditions VIN = 0.9 V Min. Typ. Max. Unit 0.9 V 1 µA 2.1 V VIN = 2.1 V 10 0.25 µA V page 7/31 VND5T100AJ-E Electrical characteristics Symbol VICL Parameter Test conditions Min. IIN = 1 mA Input clamp voltage 5.5 IIN = -1 mA VFR_Stby_L Fault_reset_standby low level voltage IFR_Stby_L Low level fault_reset_standby current VFR_Stby_H Fault_reset_standby high level voltage IFR_Stby_H High level fault_reset_standby current VFR_Stby = 2.1 V VFR_Stby(hyst) Fault_reset_standby hysteresis voltage VFR_Stby_CL Fault_reset_standby clamp voltage Typ. Max. 7 -0.7 0.9 VFR_Stby = 0.9 V V V 1 µA 2.1 V 10 0.25 IFR_Stby = 15 mA (t < 10 ms) Unit V 11 IFR_Stby = -1 mA µA 15 -0.7 V V treset Overload latch-off reset time See Figure 4 2 24 µs tstby Standby delay See Figure 5 120 1200 µs Figure 4. treset definition treset FR_Stby IN OUTPUT CS Overload Channel GAPGCFT000112 Figure 5. tstby definition FR_Stby INPUTn IGND tstby tstby GAPGCFT000111_v2 DS7125 - Rev 4 page 8/31 VND5T100AJ-E Electrical characteristics Table 8. Protections and diagnostics Symbol Parameter Test conditions IlimH DC short circuit current IlimL Short circuit current during thermal cycling TTSD Shutdown temperature TR Reset temperature TRS Thermal reset of status THYST VCC = 24 V Min. Typ. Max. 16 22 30 5 V < VCC < 36 V Unit A 30 VCC = 24 V, TR < TJ < TTSD 6 A 150 175 TRS + 1 TRS + 5 200 °C °C 135 °C Thermal hysteresis (TTSD - TR) VDEMAG Turn-off output voltage clamp IOUT = 1.5 A, VIN = 0 V, L = 6 mH VON Output voltage drop limitation IOUT = 50 mA, TJ = -40 °C to 150 °C 7 °C VCC - 58 VCC - 64 VCC - 70 V 25 mV Table 9. Current sense (8 V < VCC < 36 V) Symbol K1 dK1/K1(1) Parameter IOUT/ISENSE Current sense ratio drift Test conditions IOUT/ISENSE K3 dK3/K3(1) K4 dK4/K4(1) ISENSE0 VSENSE DS7125 - Rev 4 Current sense ratio drift IOUT/ISENSE Current sense ratio drift IOUT/ISENSE Current sense ratio drift Analog sense leakage current Max analog sense output voltage Max. 930 IOUT = 350 mA, VSENSE = 1 V, TJ = 25 °C to 150 °C 1050 2020 IOUT = 350 mA, VSENSE = 1 V, TJ = -40 °C to 150 °C -15 15 1225 1835 IOUT = 0.8 A, VSENSE = 2 V, TJ = 25 °C to 150 °C dK2/K2(1) Typ. IOUT = 350 mA, VSENSE = 1 V, TJ = -40 °C to 150 °C IOUT = 0.8 A, VSENSE = 2 V, TJ = -40 °C to 150 °C K2 Min. IOUT = 0.8 A, VSENSE = 2 V, TJ = -40 °C to 150 °C Unit 2185 1547 % 1528 1310 1745 -12 12 IOUT = 1.5 A, VSENSE = 2 V, TJ = -40 °C to 150 °C 1340 IOUT = 1.5 A, VSENSE = 2 V, TJ = 25 °C to 150 °C 1405 1655 IOUT = 1.5 A, VSENSE = 2 V, TJ = -40 °C to 150 °C -8 8 % 1715 1525 IOUT = 6 A, VSENSE = 4 V, TJ = -40 °C to 150 °C 1450 IOUT = 6 A, VSENSE = 4 V, TJ = 25 °C to 150 °C 1475 1560 IOUT = 6 A, VSENSE = 4 V, TJ = -40 °C to 150 °C -5 5 IOUT = 0 A, VSENSE = 0 V, VIN = 0 V, TJ = -40 °C to 150 °C 0 1 IOUT = 0 A, VSENSE = 0 V, VIN = 5 V, TJ = -40 °C to 150 °C 0 IOUT = 6 A, RSENSE = 3.9 kΩ 5 % 1600 1522 % µA 2 V page 9/31 VND5T100AJ-E Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit VSENSEH Analog sense output voltage in fault condition(2) VCC = 24 V, RSENSE = 3.9 kΩ 7.5 8.5 9.5 V ISENSEH Analog sense output current in fault condition(2) VCC = 24 V, VSENSE = 5 V 4.9 9 12 mA 100 200 µs 150 µs 5 20 µs Min. Typ. Max. Unit 2 - 4 V 180 - 1800 µs -120 - 0 µA - 20 µs - 50 µs VSENSE < 4 V, 0.07 A < IOUT < 6 A, tDSENSE2H Delay response time from rising edge of INPUT pins ISENSE = 90% of ISENSEMAX, (see Figure 6) VSENSE < 4 V, ΔtDSENSE2H ISENSE = 90 % of ISENSEMAX, Delay response time between rising edge of output current and rising edge IOUT = 90 % of IOUTMAX, of current sense IOUTMAX = 1.5 A (see Figure 10) VSENSE < 4 V, tDSENSE2L Delay response time from falling edge 0.07 A < IOUT < 6 A, of INPUT pins ISENSE = 10% of ISENSEMAX, (see Figure 6) 1. Specified by design, not tested in production. 2. Fault condition includes: power limitation, overtemperature and openload in off-state condition. Table 10. Openload detection (VFR_Stby = 5 V) Symbol Parameter VOL Openload off-state voltage detection threshold tDSTKON Output short circuit to VCC detection delay at turn off Test conditions VIN = 0 V, 8 V < VCC < 36 V VFR_Stby = 5 V VFR_Stby = 5 V (see Figure 7) VIN = 0 V, VSENSE = 0 V, IL(off2) Off-state output current at VOUT = 4 V VOUT rising from 0 V to 4 V VFR_Stby = 5 V VOUT = 4 V, VIN = 0 V, td_vol Delay response from output rising edge to VSENSE rising edge in openload VSENSE = 90 % of VSENSEH, RSENSE = 3.9 kΩ VFR_Stby = 5 V tDFRSTK_ON DS7125 - Rev 4 Output short circuit to VCC detection delay at FR_Stby activation Input1, 2 = low (see Figure 9) page 10/31 VND5T100AJ-E Electrical characteristics Figure 6. Current sense delay characteristics INPUT LOAD CURRENT SENSE CURRENT tDSENSE2L tDSENSE2H GAPGCFT000117 Figure 7. Openload off-state delay timing Output stuck at VCC VIN VOUT > VOL VSENSEH VCS tDSTKON NOTE: VFR_stby = 5 V. GAPGCFT000113 DS7125 - Rev 4 page 11/31 VND5T100AJ-E Electrical characteristics Figure 8. Switching characteristics VOUT tWon tWoff 90% 80% (dVOUT/dt)(off) (dVOUT/dt)(on) tr tf 10% t INPUT td(on) td(off) t GAPGCFT000114 Figure 9. Output stuck to VCC detection delay time at FR_Stby activation FR_Stby VSENSEH VCS tDFRSTK_ON Input1,2 = Low GAPGCFT00038_v2 DS7125 - Rev 4 page 12/31 VND5T100AJ-E Electrical characteristics Figure 10. Delay response time between rising edge of ouput current and rising edge of current sense VIN ΔtDSENSE2H t IOUT IOUTMAX 90% IOUTMAX t ISENSE ISENSEMAX 90% ISENSEMAX t GAPGCFT000115 Figure 11. Output voltage drop limitation VCC - VOUT TJ = 150 °C TJ = 25 °C TJ = -40 °C VON IOUT VON /RON (T) AG00074V1 DS7125 - Rev 4 page 13/31 VND5T100AJ-E Electrical characteristics Figure 12. Device behavior in overload condition treset treset FAULT_RESET INn OUTPUTn VSENSEH CSn overload overload reset overload diag reset OVERLOAD(*) CHANNELn 1 2 3 4 5 6 7 8 1: OUTPUTn and CSn controlled by INn 2: FAULT_RESET from ‘0’ to ‘1’ → no action on CSn pin 3: overload latch-off. INn high → CSn high 4: FAULT_RESET low AND Temp channeln < overload_reset → overload latch reset after t_reset 4 to 5: FAULT_RESET low AND INn high → thermal cycling, CSn high 5: FAULT_RESET high → latch-off reset disabled 6 to 7: overload event and FAULT_RESET high → latch-off, no thermal cycling 7 to 8: overload diagnostic disabled/enabled by the input 8: overload latch-off reset by FAULT_RESET (*) OVERLOAD = thermal shutdown OR power limitation GAPGCFT000116_v2 Table 11. Truth table Conditions Standby Normal operation Overload Overtemperature/short to ground Undervoltage Short to VBAT Openload off-state (with pull-up) Negative output voltage clamp DS7125 - Rev 4 Fault reset standby Input Output Sense L L L 0 X L L 0 X H H Nominal X L L 0 X H H > Nominal X L L 0 L H Cycling VSENSEH H H Latched VSENSEH X X L 0 L L H 0 H L H VSENSEH X H H < Nominal L L H 0 H L H VSENSEH X H H 0 X L Negative 0 page 14/31 VND5T100AJ-E Electrical characteristics Table 12. Electrical transient requirements (part 1) Number of ISO 7637-2: 2004 (E) Test levels(1) Test pulse III IV 1 -450 V -600 V 2a 37 V 50 V 3a - 150 V - 200 V 3b + 150 V 4 5b(2) pulses or Burst cycle/pulse test times repetition time 5000 Delays and impedence 0.5 s 5s 1 ms, 50 Ω 0.2 s 5s 50 µs, 2 Ω 1h 90 ms 100 ms 0.1 µs, 50 Ω + 200 V 1h 90 ms 100 ms 0.1 µs, 50 Ω - 12 V - 16 V 1 pulse 100 ms, 0.01 Ω + 123 V + 174 V 1 pulse 350 ms, 1 Ω pulses 5000 pulses 1. The above test levels must be considered referred to VCC = 24.5 V except for pulse 5b. 2. Valid in case of external load dump clamp: 58 V maximum referred to ground. Table 13. Electrical transient requirements (part 2) Test level results ISO 7637-2: 2004 (E) Test pulse III IV 1 C C 2a C C 3a C C 3b(1) E E 3b(2) C C 4 C C 5b(3) C C 1. Without capacitor between VCC and GND. 2. With 10 nF between VCC and GND. 3. External load dump clamp, 58 V maximum, referred to ground. Table 14. Electrical transient requirements (part 3) Class DS7125 - Rev 4 Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. page 15/31 VND5T100AJ-E Electrical characteristics (curves) 2.4 Electrical characteristics (curves) Figure 13. Off-state output current Figure 14. High level input current Iloff [µA] IIH [μA] GAPGCFT00056 1.4 4.5 1.2 3.5 3.0 0.8 2.5 Off-state, VCC = 24 V, VIN = VOUT = 0 V 0.6 2.0 1.5 0.4 1.0 0.2 0.5 -25 0 25 50 75 Tc [ °C] 100 125 150 175 0.0 -50 6.8 50 75 100 125 150 175 GAPGCFT00059 2.0 1.8 IIN = 1 mA 1.6 6.4 1.4 6.2 1.2 6.0 1.0 5.8 0.8 5.6 0.6 5.4 0.4 5.2 0.2 -25 0 25 50 75 100 125 150 175 0.0 -50 -25 0 25 50 75 100 125 150 TC [°C] TC [°C] Figure 17. High level input voltage Figure 18. Input hysteresis voltage VIH [V] 175 Vihyst [V] GAPGCFT00060 4.0 GAPGCFT00061 1.0 0.9 3.5 0.8 3.0 0.7 2.5 0.6 0.5 2.0 0.4 1.5 0.3 1.0 0.2 0.5 0.1 -25 0 25 50 TC [°C] DS7125 - Rev 4 25 VIL [V] GAPGCFT00058 7.0 0.0 -50 0 Figure 16. Low level input voltage VICL [V] 5.0 -50 -25 TC [°C] Figure 15. Input clamp voltage 6.6 VIN = 2.1 V 4.0 1.0 0.0 -50 GAPGCFT00057 5.0 75 100 125 150 175 0.0 -50 -25 0 25 50 75 100 125 150 175 TC [°C] page 16/31 VND5T100AJ-E Electrical characteristics (curves) Figure 19. On-state resistance vs TC Figure 20. On-state resistance vs VCC RON [mΩ] RON [mΩ] GAPGCFT00062 200 120 160 TC =125°C 140 IOUT =1.5A VCC =24V 120 100 100 80 80 60 60 TC =25°C TC = - 40°C 40 40 20 20 0 -50 TC =150°C 180 160 140 GAPGCFT00063 200 180 0 -25 0 25 50 75 100 125 150 5 175 10 15 20 25 TC [°C] Figure 21. Turn-on voltage slope 35 40 Figure 22. Turn-off voltage slope (dVout/dt)on [V/μs] (dVout/dt)Off [V/μs] GAPGCFT00065 2.0 GAPGCFT00066 1.4 1.8 1.6 1.2 VCC=24V RL=16Ω 1.4 VCC =24V RL =16Ω 1.0 1.2 0.8 1.0 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 -50 30 VCC [V] 0.0 -50 -25 0 25 50 75 100 125 150 -25 0 25 175 50 75 100 125 150 175 TC [°C] TC [°C] Figure 23. ILIMH vs TC IlimH [A] GAPGCFT00064 23.0 22.5 VCC =24V 22.0 21.5 21.0 20.5 20.0 19.5 -50 -25 0 25 50 75 100 125 150 175 TC [°C] DS7125 - Rev 4 page 17/31 VND5T100AJ-E Application information 3 Application information Figure 24. Application schematic +5V VCC Rprot FR_Stby DId MCU Rprot IN Rprot CS OUT GND Cext RSENSE VGND DGND GAPGCFT000119 3.1 GND protection network against reverse battery 3.1.1 Solution 1: resistor in the ground line (RGND only) This solution can be used with any load type. The following is an indication on how to dimension the RGND resistor. 1. RGND ≤ 600 mV / (IS(on)max.) 2. RGND ≥ (-VCC) / (-IGND) Where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC < 0 V: during reverse battery situations) is: PD = (-VCC)2 / RGND This resistor can be shared among several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max. becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND produces a shift (IS(on)max. * RGND) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor, then ST suggests solution 2 is used (see below). DS7125 - Rev 4 page 18/31 VND5T100AJ-E Load dump protection 3.1.2 Solution 2: diode (DGND) in the ground line A resistor (RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values, if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2 2004 (E) Table 12, Table 13 and Table 14. 3.3 MCU I/Os protection If a ground protection network is used and negative transient is present on the VCC line, the control pins are pulled negative. ST suggests that a resistor (Rprot) has to be inserted in line to prevent the microcontroller I/Os pins from latching-up. The value of these resistors is a compromise between the leakage current of the microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation: Rprot range calculation -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -600 V and Ilatchup ≥ 20 mA; VOHμC ≥ 4.5 V 30 kΩ ≤ Rprot ≤ 180 kΩ. Recommended value: Rprot = 60 kΩ. DS7125 - Rev 4 page 19/31 VND5T100AJ-E Maximum demagnetization energy (VCC = 24 V) 4 Maximum demagnetization energy (VCC = 24 V) Figure 25. Maximum turn off current versus inductance GAPGCFT00810 100 Single pulse TJstart = 150 °C Repetitive pulse TJstart = 100 °C Repetitive pulse TJstart = 125 °C A I (A) C B 10 1 1 10 100 1000 L (mH) Note: DS7125 - Rev 4 Values are generated with RL = 0 Ω. In case of repetitive pulses, TJstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. page 20/31 VND5T100AJ-E Package and PCB thermal data 5 Package and PCB thermal data 5.1 PowerSSO-12 thermal data Figure 26. PowerSSO-12 PCB GAPGCFT000120 Layout condition of Rth and Zth measurements (board finish thickness 1.6 mm ±10%; board double layer; board dimension 77 mm x 86 mm; board material FR4; Cu thickness 0.070 mm (front and back side); thermal vias separation 1.2 mm; thermal via diameter 0.3 mm ±0.08 mm; Cu thickness on vias 0.025 mm; footprint dimension 4.1 mm x 6.5 mm). Figure 27. RthJA vs PCB copper area in open box free air condition (one channel ON) RthJA (°C/W) GAPGCFT000124 65 60 55 RthJA 50 45 40 35 30 0 2 4 PCB Cu heatsink area DS7125 - Rev 4 6 8 10 (cm2) page 21/31 VND5T100AJ-E PowerSSO-12 thermal data Figure 28. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON) Zth (°C/W) GAPGCFT000125 100 Cu = 8 cm2 Cu = 2 cm2 Cu = footprint 10 1 0.1 0.0001 t (s) 0.1 0.01 0.001 1 10 100 1000 Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-12 PdCh1 PdCh2 TJ TJ C1 C2 R1 R2 C7 C8 R7 R8 C3 C4 C5 C6 R3 R4 R5 R6 GAPGCFT00438 The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Equation: pulse calculation formula Zthδ = Rth · δ + Zthtp (1 - δ) Where δ = tP/T DS7125 - Rev 4 page 22/31 VND5T100AJ-E PowerSSO-12 thermal data Table 15. Thermal parameters DS7125 - Rev 4 Area/island (cm2) Footprint R1 = R7 (°C/W) 0.8 R2 = R8 (°C/W) 1.5 R3 (°C/W) 3 R4 (°C/W) 2 8 8 8 7 R5 (°C/W) 22 15 10 R6 (°C/W) 26 20 15 C1 = C7 (W.s/°C) 0.0008 C2 = C8 (W.s/°C) 0.005 C3 (W.s/°C) 0.05 C4 (W.s/°C) 0.2 0.1 0.1 C5 (W.s/°C) 0.27 0.8 1 C6 (W.s/°C) 3 6 9 page 23/31 VND5T100AJ-E Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 PowerSSO-12 package information Figure 30. PowerSSO-12 package dimensions DS7125 - Rev 4 page 24/31 VND5T100AJ-E PowerSSO-12 package information Table 16. PowerSSO-12 mechanical data Symbol Millimeters Min. Typ. Max. θ 0° θ1 0° θ2 5° 15° θ3 5° 15° A 1.25 1.70 A1 0.00 0.10 A2 1.10 1.60 b 0.23 0.41 b1 0.20 c 0.19 c1 0.19 D 8° 0.25 0.39 0.25 0.20 0.23 4.90 BSC D2 3.60 D3 2.90 4.20 e 0.80 BSC E 6.00 BSC E1 3.90 BSC E2 1.90 2.50 E3 1.20 h 0.25 0.50 L 0.40 1.27 L1 1.00 REF N 12 R 0.07 R1 0.07 S 0.20 Table 17. PowerSSO-12 tolerance of form and position DS7125 - Rev 4 Symbol Millimeters aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 page 25/31 VND5T100AJ-E PowerSSO-12 packing information 6.2 PowerSSO-12 packing information Figure 31. PowerSSO-12 tube shipment (no suffix) All dimensions are in mm. B C A GAPGCFT000123 Figure 32. PowerSSO-12 tape and reel shipment (suffix “TR”) Reel dimensions Tape dimensions End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed DS7125 - Rev 4 page 26/31 VND5T100AJ-E Revision history Table 18. Document revision history Date Revision Changes 08-Mar-2011 1 Initial release. 25-Sep-2013 2 Disclaimer updated. Table 4: Thermal data: 22-Mar-2016 3 – Rthj-case: updated value Updated Section 5.1: PowerSSO-12 mechanical data. Updated PowerSSO-12 cover image and Device summary on cover page. Updated Table 5. Power section. Added notes in Table 12. Electrical transient requirements (part 1) 21-Jun-2022 4 Updated Figure 24. Application schematic. Moved Section 3.4: Maximum demagnetization energy (VCC = 24 V) to Section 4 Maximum demagnetization energy (VCC = 24 V) Updated Section 6.1 PowerSSO-12 package information. Minor text changes. DS7125 - Rev 4 page 27/31 VND5T100AJ-E Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 2.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.1 GND protection network against reverse battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.1 Solution 1: resistor in the ground line (RGND only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Maximum demagnetization energy (VCC = 24 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.1 6 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.1 PowerSSO-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 DS7125 - Rev 4 page 28/31 VND5T100AJ-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suggested connections for unused and not connected pins . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching (VCC = 24 V, TJ = 25 °C). . . . . . . . . . . . . . . . . . Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protections and diagnostics. . . . . . . . . . . . . . . . . . . . . . . Current sense (8 V < VCC < 36 V) . . . . . . . . . . . . . . . . . . Openload detection (VFR_Stby = 5 V). . . . . . . . . . . . . . . . . Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical transient requirements (part 1) . . . . . . . . . . . . . . Electrical transient requirements (part 2) . . . . . . . . . . . . . . Electrical transient requirements (part 3) . . . . . . . . . . . . . . Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . PowerSSO-12 tolerance of form and position . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . DS7125 - Rev 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 . 6 . 7 . 7 . 7 . 9 . 9 10 14 15 15 15 23 25 25 27 page 29/31 VND5T100AJ-E List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. DS7125 - Rev 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration diagram PowerSSO-12 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . treset definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tstby definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Openload off-state delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output stuck to VCC detection delay time at FR_Stby activation . . . . . . . . . . . . . . . . . . . . Delay response time between rising edge of ouput current and rising edge of current sense . Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-state resistance vs TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILIMH vs TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum turn off current versus inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-12 PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RthJA vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . . . . . PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . . . Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-12 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 . 8 . 8 11 11 12 12 13 13 14 16 16 16 16 16 16 17 17 17 17 17 18 20 21 21 22 22 24 26 26 page 30/31 VND5T100AJ-E IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS7125 - Rev 4 page 31/31
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