VND7012AYTR-E

VND7012AY-E Double channel high-side driver with MultiSense analog feedback for automotive applications Datasheet - preliminary data PowerSSO-36 – Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin – Loss of ground and loss of VCC – Reverse battery through self turn-on – Electrostatic discharge protection *$3*&)7 Applications Features Max transient supply voltage VCC 41 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 12 mΩ Current limitation (typ) ILIMH 75 A Standby current (max) ISTBY 0.5 µA • General – Double channel smart high side driver with MultiSense analog feedback – Very low standby current – Compatible with 3 V and 5 V CMOS outputs • MultiSense diagnostic functions – Multiplexed analog feedback of: load current with high precision proportional current mirror, VCC supply voltage and TCHIP device temperature – Overload and short to ground (power limitation) indication – Thermal shutdown indication – Off-state open-load detection – Output short to VCC detection – Sense enable/ disable • Protections – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients July 2014 • All types of Automotive resistive, inductive and capacitive loads • Specially intended for Automotive Turn Indicators (up to 3 x P27W or SAE1156 and 2 x R5W paralleled or Automotive Headlamps) Description The VND7012AY-E is a double channel high-side driver manufactured using ST proprietary VIPower® M0-7 technology and housed in PowerSSO-36 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to VCC and off-state open-load. A sense enable pin allows off-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. DocID022886 Rev 6 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/46 www.st.com 1 Contents VND7012AY-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4 Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 27 4.2 Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 28 4.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 MultiSense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.5 5 7 2/46 Principle of MultiSense signal generation . . . . . . . . . . . . . . . . . . . . . . . 31 4.4.2 TCASE and VCC monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.3 Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . 34 Maximum demagnetization energy (VCC = 16 V) . . . . . . . . . . . . . . . . . . . 35 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1 6 4.4.1 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2 PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DocID022886 Rev 6 VND7012AY-E 8 Contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DocID022886 Rev 6 3/46 List of tables VND7012AY-E List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. 4/46 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching (VCC = 13 V; -40 °C < Tj < 150 °C, unless otherwise specified). . . . . . . . . . . . . 11 Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MultiSense multiplexer addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . . 28 MultiSense pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DocID022886 Rev 6 VND7012AY-E List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IOUT/ISENSE vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Current sense precision vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Switching times and Pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MultiSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MultiSense timings (chip temperature and VCC sense mode) . . . . . . . . . . . . . . . . . . . . . . 20 TDSKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 IGND(ON) vs. Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Logic Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Logic Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Logic Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FaultRST Input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 On-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 On-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Won vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Woff vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 OFF-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Vsense clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Vsenseh vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MultiSense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MultiSense block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Analogue HSD – open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PowerSSO-36 PCB board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . . 37 PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) . . . . . 38 Thermal fitting model of a double-channel HSD in PowerSSO-16 . . . . . . . . . . . . . . . . . . 38 PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DocID022886 Rev 6 5/46 Block diagram and pin description 1 VND7012AY-E Block diagram and pin description Figure 1. Block diagram 9&& ,QWHUQDOVXSSO\ 9&&±*1' &ODPS 8QGHUYROWDJH VKXWGRZQ &+ &KDQQHO &RQWURO 'LDJQRVWLF &KDQQHO )DXOW567 9&&±287 &ODPS &+ ,1387 ,1387 *DWH'ULYHU 6(/ 7 9&& 287387 921 /LPLWDWLRQ 6(/ &XUUHQW /LPLWDWLRQ 08; 6(Q 0XOWLVHQVH  3RZHU/LPLWDWLRQ 2YHUWHPSHUDWXUH 7 6KRUWWR9&& 2SHQ/RDGLQ2)) &XUUHQW 6HQVH )DXOW 96(16(+ *1' 287387 ("1($'5 Table 1. Pin functions Name VCC OUTPUT0,1 GND INPUT0,1 MultiSense SEn 6/46 Function Battery connection. Power output. Ground connection. Voltage controlled input pin with hysteresis, compatible with 3V and 5V CMOS outputs. They control output switch state. Multiplexed analog sense output pin; delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. Active high compatible with 3V and 5V CMOS outputs; it enables the MultiSense diagnostic pin. SEL0,1 Active high compatible with 3V and 5V CMOS outputs; they address the MultiSense multiplexer. FaultRST Active low compatible with 3V and 5V CMOS outputs; unlatches the output in case of fault; if kept low, sets the outputs in auto-restart mode. DocID022886 Rev 6 VND7012AY-E Block diagram and pin description Figure 2. Configuration diagram (top view) 287387 287387 287387 287387 287387 287387 1& 1& 1& 1& 1& 1& 1& 6(Q 1& 6(/ 6(/ 1&                                 7$%9FF     287387 287387 287387 287387 287387 287387 1& 1& 1& 1& 1& 1& 1& ,1387 ,1387 0XOWL6HQVH *1' )DXOW567 3RZHU6623$&.$*(   ("1($'5 Table 2. Suggested connections for unused and not connected pins Connection/pin MultiSense N.C. Output Input Floating Not allowed X(1) X X To ground Through 1 kΩ resistor X Not allowed SEn, SELx, FaultRST X Through 15 kΩ Through 15 kΩ resistor resistor 1. X: do not care. DocID022886 Rev 6 7/46 Electrical specification 2 VND7012AY-E Electrical specification Figure 3. Current and voltage conventions ,6 9&& )DXOW567 ,6(Q ,287 287387 96(Q 9287 ,6(16( 6(Q ,6(/ 6(/ 96(/ 9)5 9&& 9)Q ,)5 0XOWL6HQVH 96(16( ,,1 6 ,1 ,1387 ,*1' *$3*&)7 Note: VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol 8/46 Parameter Value VCC DC supply voltage 38 -VCC Reverse DC supply voltage 16 VCCPK Maximum transient supply voltage (ISO7637-2:2004 Pulse 5b level IV clamped to 40 V; RL = 4 Ω) 40 VCCJS Maximum jump start voltage for single pulse short circuit protection 28 -IGND DC reverse ground pin current 200 IOUT OUTPUT0,1 DC output current Internally limited -IOUT Reverse DC output current IIN INPUT0,1 DC input current ISEn SEn DC input current ISEL SEL0,1 DC input current IFR FaultRST DC input current V mA A 22 -1 to 10 DocID022886 Rev 6 Unit mA VND7012AY-E Electrical specification Table 3. Absolute maximum ratings (continued) Symbol Value Unit FaultRST DC input voltage 7.5 V MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 MultiSense pin DC output current in reverse (VCC < 0 V) -20 EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150°C) 144 mJ VESD Electrostatic discharge (JDEC 22 A-114 F) – INPUT0,1 – MultiSense – SEn, SEL0,1, FaultRST – OUTPUT0,1 – VCC 4000 2000 4000 4000 4000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V VFR ISENSE Tj Tstg 2.2 Parameter mA Junction operating temperature -40 to 150 Storage temperature -55 to 150 °C Thermal data Table 4. Thermal data Symbol Parameter Typ. value Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8)(1)(2) Unit 4 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)(3) 50.6 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7)(1)(2) 16.6 °C/W 1. One channel ON. 2. Device mounted on four-layers 2s2p PCB 3. Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace DocID022886 Rev 6 9/46 Electrical specification 2.3 VND7012AY-E Main electrical characteristics 7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified. Table 5. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit VCC Operating supply voltage VUSD Undervoltage shutdown 4 VUSDReset Undervoltage shutdown reset 5 VUSDhyst Undervoltage shutdown hysteresis 4 RON RON_REV Vclamp ISTBY tD_STBY IS(ON) IGND(ON) 10/46 On-state On-state resistance in reverse battery Clamp voltage Supply current in standby at VCC = 13 V (2) 28 V 0.3 IOUT = 7 A; Tj = 25°C resistance(1) 13 12 IOUT = 7 A; Tj = 150°C 24 IOUT = 7 A; VCC = 4 V; Tj = 25°C 18 IOUT = -7 A; VCC = -13 V; Tj = 25°C 12 IS = 20 mA; 25°C < Tj < 150°C 41 IS = 20 mA; Tj = -40 °C 38 46 mΩ mΩ 52 V V VCC = 13 V; VIN0,1 = VOUT0,1 = VFR = VSEn 0 V; VSEL0,1 = 0 V; Tj = 25°C 0.5 µA VCC = 13 V; VIN0,1 = VOUT0,1 = VFR = VSEn 0 V; VSEL0,1 = 0 V; Tj = 85°C (3) 0.5 µA VCC = 13 V; VIN0,1 = VOUT0,1 = VFR = VSEn 0 V; VSEL0,1 = 0 V; Tj = 125°C 3 µA 300 550 µs 5 8 mA 10 mA VCC = 13 V; VIN0,1 = VOUT0,1 = 0 V; Standby mode blanking VFR = VSEL0,1 = 0 V; time VSEn = 5 V to 0 V Supply current VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V; VIN0,1 = 5 V; IOUT0 = 0 A; IOUT1 = 0 A Control stage current consumption in ON state. All channels active. VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V; VIN0,1 = 5 V; IOUT0 = 7 A; IOUT1 = 7 A DocID022886 Rev 6 60 VND7012AY-E Electrical specification Table 5. Power section Symbol IL(off) Parameter Test conditions Min. Typ. Max. Unit VIN0,1 = VOUT0,1 = 0 V; VCC = 13 V; Off-state output current Tj = 25°C at VCC = 13 V (1) =V = 0 V; V = 13 V; V IN0,1 OUT0,1 0 Output - VCC diode voltage(1) 0.5 µA CC 0 Tj = 125°C VF 0.01 3 IOUT = -7 A; Tj = 150 °C 0.7 V 1. For each channel. 2. PowerMOS leakage included. 3. Parameter specified by design; not subject to production test. Table 6. Switching (VCC = 13 V; -40 °C < Tj < 150 °C, unless otherwise specified)(1) Symbol Parameter td(on) Turn-on delay time at Tj = 25 °C td(off) Turn-off delay time at Tj = 25 °C Test conditions RL = 1.84 Ω (dVOUT/dt)on Turn-on voltage slope at Tj = 25 °C (dVOUT/dt)off Turn-off voltage slope at Tj = 25 °C RL = 1.84 Ω Min. Typ. Max. Unit 10 50 120 10 45 100 0.1 0.45 0.7 0.2 0.5 0.8 µs V/µs WON Switching energy losses at turn-on (twon) RL = 1.84 Ω — 0.6 1.4(2) mJ WOFF Switching energy losses at turn-off (twoff) RL = 1.84 Ω — 0.6 1.3(2) mJ tSKEW Differential pulse skew (tPHL - tPLH) see Figure 6 RL = 1.84 Ω -60 -10 40 µs Max. Unit 0.9 V 1. See Figure 6: Switching times and Pulse skew. 2. Parameter guaranteed by design and characterization, not subject to production test. Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) Symbol Parameter Test conditions Min. Typ. INPUT0,1 characteristics VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage VIN = 0.9 V 1 µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA IIN = -1 mA µA V 5.3 7.2 V -0.7 FaultRST characteristics VFRL Input low level voltage DocID022886 Rev 6 0.9 V 11/46 Electrical specification VND7012AY-E Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) (continued) Symbol Parameter IFRL Low level input current VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL Test conditions VIN = 0.9 V Min. Typ. Max. 1 µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage Unit µA V 5.3 7.5 V IIN = -1 mA -0.7 SEL0,1 characteristics (7 V < VCC < 18 V) VSELL Input low level voltage ISELL Low level input current VSELH Input high level voltage ISELH High level input current VSEL(hyst) Input hysteresis voltage VSELCL 0.9 VIN = 0.9 V 1 µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V µA V 5.3 7.2 V IIN = -1 mA -0.7 SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL Input clamp voltage 0.9 VIN = 0.9 V 1 µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA V µA V 5.3 7.2 V IIN = -1 mA -0.7 Table 8. Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C) Symbol Parameter ILIMH(1) DC short circuit current ILIML Short circuit current during thermal cycling TTSD Shutdown temperature VCC = 13 V Reset TRS Thermal reset of fault diagnostic indication Min. Typ. Max. 60 75 96 4 V < VCC < 18 V(2) 96 VCC = 13 V; TR < Tj < TTSD temperature(2) TR THYST 12/46 Test conditions VFR = 0 V; VSEn = 5 V Thermal hysteresis (TTSD - TR)(2) A 25 150 175 TRS + 1 TRS + 5 200 °C 135 5 DocID022886 Rev 6 Unit VND7012AY-E Electrical specification Table 8. Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued) Symbol ΔTJ_SD tLATCH_RST VDEMAG VON Parameter Test conditions Min. Typ. Dynamic temperature 60 VFR = 5 V to 0 V; VSEn = 5 V; VIN0,1 = 5 V; VSEL0,1 = 0 V Fault reset time for output unlatch(2) Turn-off output voltage clamp Output voltage drop limitation Max. 3 K 10 20 IOUT = 2 A; L = 6 mH; Tj = -40 °C VCC - 38 IOUT = 2 A; L = 6 mH; Tj = 25°C to 150°C VCC - 41 VCC - 46 VCC - 52 IOUT = 0.7 A Unit µs V 20 mV 1. Parameter guaranteed by an indirect test sequence. 2. Parameter guaranteed by design and characterization; not subject to production test. Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) Symbol VSENSE_CL Parameter MultiSense clamp voltage Test conditions Min. VSEn = 0 V; ISENSE = 1 mA -17 VSEn = 0 V; ISENSE = -1 mA Typ. Max. Unit -12 V 7 V Current Sense characteristics IOUT/ISENSE IOUT = 10 mA; VSENSE = 0.5 V; VSEn = 5 V 1400 Current sense ratio drift at calibration point ICAL = 130 mA; IOUT = 10 mA to 250 mA; VSENSE = 0.5 V; VSEn = 5 V -35 KLED IOUT/ISENSE IOUT = 250 mA; VSENSE = 0.5 V; VSEn = 5 V 2490 5100 8000 K0 IOUT/ISENSE IOUT = 0.7 A; VSENSE = 0.5 V; VSEn = 5 V 2560 5120 7680 Current sense ratio drift IOUT = 0.7 A; VSENSE = 0.5 V; VSEn = 5 V -25 IOUT/ISENSE IOUT = 1.4 A; VSENSE = 4 V; VSEn = 5 V 3480 Current sense ratio drift IOUT = 1.4 A; VSENSE = 4 V; VSEn = 5 V -20 IOUT/ISENSE IOUT = 7 A; VSENSE = 4 V; VSEn = 5 V 3410 Current sense ratio drift IOUT = 7 A; VSENSE = 4 V; VSEn = 5 V -10 IOUT/ISENSE IOUT = 21 A; VSENSE = 4 V; VSEn = 5 V 3810 Current sense ratio drift IOUT = 21 A; VSENSE = 4 V; VSEn = 5 V -5 KOL dKcal/Kcal(1)(2) dK0/K0(1)(2) K1 dK1/K1(1)(2) K2 dK2/K2(1)(2) K3 dK3/K3(1)(2) DocID022886 Rev 6 35 25 4900 % 5120 10 4300 % 6470 20 4280 % % 4660 5 % 13/46 Electrical specification VND7012AY-E Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued) Symbol Parameter Test conditions Max. Unit 0 0.5 µA -0.5 0.5 µA MultiSense enabled: VSEn = 5 V; All channel ON; IOUTX = 0 A; ChX diagnostic selected; – E.g. Ch0: VIN0 = 5 V; VIN1 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; IOUT1 = 7 A 0 2 µA MultiSense enabled: VSEn = 5 V; ChX channel OFF; ChX diagnostic selected; – E.g. Ch0: VIN0 = 0 V; VIN1 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT1 = 7 A 0 2 µA MultiSense disabled: VSEn = 0 V; MultiSense disabled: -1 V < VSENSE < 5 V(1) ISENSE0 MultiSense leakage current Min. Typ. VOUT_MSD(1) VSEn = 5 V; RSENSE = 2.7 kΩ Output Voltage for – MultiSense shutdown E.g. Ch0: VIN0 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 7 A VSENSE_SAT VCC = 7 V; RSENSE = 2.7 K; Multisense saturation VSEn = 5 V; VIN0 = 5 V; voltage VSEL0,1 = 0 V; IOUT0 = 21 A; Tj = 150°C 5 V ISENSE_SAT(1) VCC = 7 V; VSENSE = 4 V; CS saturation current VSEn = 5 V; VIN0 = 5 V; VSEL0,1 = 0 V; Tj = 150°C 4 mA VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0,1 = 0 V; Tj = 150°C 23 A VSEn = 5 V; ChX OFF; ChX diagnostic selected – E.g: Ch0 VIN0 = 0 V; VSEL0 = 0 V; VSEL1 = 0 V; 2 IOUT_SAT(1) Output saturation current 5 V Off-state diagnostic VOL IL(off2) 14/46 Off-state open-load voltage detection threshold OFF state output sink VIN = 0 V; VOUT = VOL; current Tj = -40°C to 125°C DocID022886 Rev 6 -100 3 4 V -15 µA VND7012AY-E Electrical specification Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued) Symbol Parameter Test conditions tDSTKON VSEn = 5 V; ChX ON to OFF transition Off-state diagnostic ChX diagnostic selected delay time from – E.g: Ch0 falling edge of INPUT VIN0 = 5 V to 0 V; (see XXX) VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; VOUT = 4 V tD_OL_V Settling time for valid OFF-state open load diagnostic indication from rising edge of SEn tD_VOL VSEn = 5 V; ChX OFF ChX diagnostic selected Off-state diagnostic – E.g: Ch0 delay time from rising VIN0 = 0 V; VSEL0 = 0 V; edge of VOUT VSEL1 = 0 V; VOUT = 0 V to 4 V Min. Typ. Max. Unit 100 350 700 µs 60 µs 5 30 µs VIN0 = 0 V; VIN1 = 0 V; VFR = 0 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT0 = 4 V; VSEn = 0 V to 5 V Chip temperature analog feedback VSENSE_TC dVSENSE_TC/dT(1) MultiSense output voltage proportional to chip temperature Temperature coefficient VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 KΩ; Tj = -40°C 2.325 2.41 2.495 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 KΩ; Tj = 25°C 1.985 2.07 2.155 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 KΩ; Tj = 125°C 1.435 1.52 1.605 V Tj = -40°C to 150°C -5.5 mV/K VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T T0) Transfer function VCC supply voltage analog feedback VSENSE_VCC MultiSense output voltage proportional to VCC supply voltage Transfer function(3) VCC = 13 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 KΩ 3.16 3.23 3.3 V 6.6 V VSENSE_VCC = VCC / 4 Fault diagnostic feedback (see Table 10) VSENSEH MultiSense output voltage in fault condition VCC = 13 V; RSENSE = 1 kΩ – E.g: Ch0 in open load VIN0 = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; VOUT = 4 V DocID022886 Rev 6 5 15/46 Electrical specification VND7012AY-E Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued) Symbol ISENSEH Parameter MultiSense output current in fault condition Test conditions Min. Typ. Max. Unit 7 20 30 mA 60 µs 5 20 µs 100 250 µs 100 µs 250 µs VCC = 13 V; VSENSE = 5 V MultiSense timings (current sense mode - see Figure 7)(4) tDSENSE1H Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 kΩ; RL = 1.84 Ω tDSENSE1L Current sense disable delay time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 kΩ; RL = 1.84 Ω tDSENSE2H Current sense VIN = 0 V to 5 V; settling time from VSEn = 5 V; RSENSE = 1 kΩ; rising edge of INPUT RL = 1.84 Ω ΔtDSENSE2H tDSENSE2L Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 1.84 Ω Current sense turn- VIN = 5 V to 0 V; off delay time from VSEn = 5 V; RSENSE = 1 kΩ; falling edge of INPUT RL = 1.84 Ω 50 MultiSense timings (chip temperature sense mode - see Figure 8)(4) tDSENSE3H VSENSE_TC settling VSEn = 0 V to 5 V; time from rising edge VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 kΩ of SEn 60 µs tDSENSE3L VSENSE_TC disable delay time from falling edge of SEn 20 µs VSEn = 5 V to 0 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 kΩ MultiSense timings (VCC voltage sense mode - see Figure 8)(4) tDSENSE4H VSENSE_VCC settling VSEn = 0 V to 5 V; time from rising edge VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 kΩ of SEn 60 µs tDSENSE4L VSENSE_VCC disable delay time from falling edge of SEn 20 µs 20 µs VSEn = 5 V to 0 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 kΩ MultiSense timings (Multiplexer transition times)(4) tD_XtoY 16/46 VIN0 = 5 V; VIN1 = 5 V; MultiSense transition VSEn = 5 V; VSEL1 = 0 V; delay from ChX to VSEL0 = 0 V to 5 V; ChY IOUT0 = 0A; IOUT1 = 3 A; RSENSE = 1 kΩ DocID022886 Rev 6 VND7012AY-E Electrical specification Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued) Symbol Parameter Max. Unit tD_CStoTC VIN0 = 5 V; VSEn = 5 V; MultiSense transition VSEL0 = 0 V; delay from current VSEL1 = 0 V to 5 V; sense to TC sense IOUT0 = 3.5 A; RSENSE = 1 kΩ 60 µs tD_TCtoCS VIN0 = 5 V; VSEn = 5 V; MultiSense transition VSEL0 = 0 V; delay from TC sense VSEL1 = 5 V to 0 V; to current sense IOUT0 = 3.5 A; RSENSE = 1 kΩ 20 µs tD_CStoVCC VIN1 = 5 V; VSEn = 5 V; MultiSense transition VSEL0 = 5 V; delay from current VSEL1 = 0 V to 5 V; sense to VCC sense IOUT1 = 3.5A; RSENSE = 1 kΩ 60 µs tD_VCCtoCS V = 5 V; VSEn = 5 V; MultiSense transition IN1 VSEL0 = 5 V; delay from VCC VSEL1 = 5 V to 0 V; sense to current IOUT1 = 3.5 A; sense RSENSE = 1 kΩ 20 µs tD_TCtoVCC VCC = 13 V; Tj = 125°C; MultiSense transition VSEn = 5 V; delay from TC sense VSEL0 = 0 V to 5 V; to VCC sense VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs tD_VCCtoTC VCC = 13 V; Tj = 125°C; MultiSense transition VSEn = 5 V; delay from VCC VSEL0 = 5 V to 0 V; sense to TC sense VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs 20 µs MultiSense transition delay from stable tD_CStoVSENSEH current sense on ChX to VSENSEH on ChY Test conditions Min. VIN0 = 5 V; VIN1 = 0 V; VSEn = 5 V; VSEL1 = 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 7 A; VOUT1 = 4 V; RSENSE = 1 kΩ Typ. 1. Parameter specified by design; not subject to production test. 2. All values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified. 3. VCC sensing and TC sensing are referred to GND potential. 4. Transition delay are measured up to +/- 10% of final conditions. DocID022886 Rev 6 17/46 Electrical specification VND7012AY-E Figure 4. IOUT/ISENSE vs. IOUT ϵϬϬϬ ϴϬϬϬ TTSD or ΔTj > ΔTj_SD Short to VCC Off-state diagnostics Open-load Negative output voltage L Comments Refer to Table 11 H H Refer to Table 11 Outputs configured for auto-restart Outputs configured for latch off Refer to Table 11 L X Refer to Table 11 Output latches off L L Hi-Z Hi-Z H Refer to Table 11 H VUSD + VUSDhyst (rising) External pull up Refer to Table 11 Table 11. MultiSense multiplexer addressing MultiSense output SEn SEL1 SEL0 MUXchannel Normal mode Overload Off-state diag.(1) Negative output L X X Hi-Z H L L Channel 0 diagnostic ISENSE = 1/K * IOUT0 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H L H Channel 1 diagnostic ISENSE = 1/K * IOUT1 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H H L TCHIP Sense VSENSE = VSENSE_TC H H H VCC Sense VSENSE = VSENSE_VCC 1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0 Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH DocID022886 Rev 6 21/46 Electrical specification 2.4 VND7012AY-E Electrical characteristics curves Figure 10. OFF-state output current Figure 11. Standby current ,67%—$@ ,ORII>Q$@     2II6WDWH 9FF 9 9LQ 9RXW   9FF 9                              7>ƒ&@ 7>ƒ&@ ("1($'5 Figure 12. IGND(ON) vs. Iout ("1($'5 Figure 13. Logic Input high level voltage 9L+9)5+96(/+96(Q+>9@ ,*1'21>P$@         9FF 9 ,RXW ,RXW $                                  7>ƒ&@ 7>ƒ&@ ("1($'5 Figure 14. Logic Input low level voltage ("1($'5 Figure 15. High level logic input current ,L+,)5+,6(/+,6(Q+>—$@ 9LO/9)5/96(//96(Q/>9@                                7>ƒ&@         7>ƒ&@ ("1($'5 22/46  DocID022886 Rev 6 ("1($'5 VND7012AY-E Electrical specification Figure 16. Low level logic input current ,L/,)5/,6(//,6(Q/>—$@ Figure 17. Logic Input hysteresis voltage 9LK\VW9)5K\VW96(/K\VW96(QK\VW>9@                                         7>ƒ&@ 7>ƒ&@ ("1($'5 ("1($'5 Figure 18. FaultRST Input clamp voltage 9)5&/>9@ Figure 19. Undervoltage shutdown 986'>9@     ,LQ P$            ,LQ P$                    7>ƒ&@      7>ƒ&@ ("1($'5 Figure 20. On-state resistance vs. Tcase 5RQ>P2KP@ ("1($'5 Figure 21. On-state resistance vs. VCC 5RQ>P2KP@    7  ƒ&   7  ƒ&  ,RXW $ 9FF 9    7  ƒ&   7  ƒ&                          9FF>9@ 7>ƒ&@ ("1($'5 DocID022886 Rev 6 ("1($'5 23/46 Electrical specification VND7012AY-E Figure 22. Turn-on voltage slope Figure 23. Turn-off voltage slope G9RXWGW2Q>9—V@ G9RXWGW2II>9—V@       9FF 9 5O ȍ  9FF 9 5O ȍ                               7>ƒ&@      7>ƒ&@ ("1($'5 ("1($'5 Figure 25. Woff vs. Tcase Figure 24. Won vs. Tcase :RQ>P-@ :RII>P-@                                      7>ƒ&@      7>ƒ&@ ("1($'5 ("1($'5 Figure 26. ILIMH vs. Tcase Figure 27. OFF-state open-load voltage detection threshold 92/>9@ ,OLPK>$@    9FF 9                         ("1($'5 24/46          7>ƒ&@ 7>ƒ&@ DocID022886 Rev 6 ("1($'5 VND7012AY-E Electrical specification Figure 28. Vsense clamp vs. Tcase Figure 29. Vsenseh vs. Tcase 96(16(+>9@ 96(16(B&/>9@        ,LQ P$             ,LQ P$                7>ƒ&@          7>ƒ&@ ("1($'5 DocID022886 Rev 6 ("1($'5 25/46 Protections VND7012AY-E 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔTj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (see Table 8, FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG (see Table 8), allowing the inductor energy to be dissipated without damaging the device. 26/46 DocID022886 Rev 6 VND7012AY-E 4 Application information Application information Figure 30. Application diagram 9 9'' 287 9&& )5 287 5SURW ,1387 5SURW 287 /RJLF 'OG 6(Q 5SURW 287 6(/ 287 5SURW &6 $'&LQ &XUUHQWPLUURU 5SURW *1' &H[W 5VHQVH 287 *1' ("1($'5 4.1 GND protection network against reverse battery Figure 31. Simplified internal structure 9FF 9 5SURW 5SURW ,1387 6(Q 0&8 'OG 5SURW )DXOW567 287387 5SURW 0XOWLVHQVH *1' 5VHQVH *1' ("1($'5 DocID022886 Rev 6 27/46 Application information VND7012AY-E The device does not need any external components to protect the internal logic in case of a reverse battery condition. The protection is provided by internal structures. In addition, due to the fact that the output MOSFET turns on even in reverse battery mode, thus providing the same low ohmic path as in regular operating conditions, no additional power dissipation has to be considered. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12. Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function does not perform as designed during the test but returns automatically to normal operation after the test”. Table 12. ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US(1) 1 III -112V 500 pulses 0,5 s 2a III +55V 500 pulses 0,2 s 5s 50μs, 2Ω 3a IV -220V 1h 90 ms 100 ms 0.1μs, 50Ω 3b IV +150V 1h 90 ms 100 ms 0.1μs, 50Ω 4(2) IV -7V 1 pulse min max 2ms, 10Ω 100ms, 0.01Ω Load dump according to ISO 16750-2:2010 Test B(3) 40V 5 pulse 1 min 400ms, 2Ω 1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. 2. Test pulse from ISO 7637-2:2004(E). 3. With 40 V external suppressor referred to ground (-40°C < Tj < 150°C). 4.3 MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs. 28/46 DocID022886 Rev 6 VND7012AY-E Application information The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation 1 VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup ≥ 20mA; VOHμC ≥ 4.5V 7.5 kΩ ≤ Rprot ≤ 140 kΩ. Recommended values: Rprot = 15 kΩ 4.4 MultiSense - analog current sense Diagnostic information on device and load status are provided by an analog output pin (MultiSense) delivering the following signals: • Current monitor: current mirror of channel output current • VCC monitor: voltage propotional to VCC • TCASE: voltage propotional to chip temperature Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in Table 11. DocID022886 Rev 6 29/46 Application information VND7012AY-E 9&& Figure 32. MultiSense and diagnostic – block diagram 5HYHUVH %DWWHU\ ,QWHUQDO6XSSO\ 9&&±*1' &ODPS 8QGHUYROWDJH VKXWGRZQ &RQWURO 'LDJQRVWLF 9&&±287 &ODPS )DXOW567 ,1387 *DWH'ULYHU 9&& 7 6(/ 6(/ 921 /LPLWDWLRQ 9&& 6(Q &XUUHQW /LPLWDWLRQ 021,725 0XOWL6HQVH 08; ,6(16( 53527 7(03 3RZHU/LPLWDWLRQ 2YHUWHPSHUDWXUH )DXOW 'LDJQRVWLF 7HPS 021,725 6KRUWWR9&& 2SHQ/RDGLQ2)) 7RX&$'& .IDFWRU 56(16( &XUUHQW 6HQVH &855(17 021,725 )DXOW ,287 287 96(16(+ *1' ("1($'5 30/46 DocID022886 Rev 6 VND7012AY-E 4.4.1 Application information Principle of MultiSense signal generation Figure 33. MultiSense block diagram 9FF ).054 6HQVH026 0DLQ026 287 &XUUHQWVHQVH 9EDW0RQLWRU 0XOWLVHQVH6ZLWFK%ORFN 7HPSHUDWXUHPRQLWRU )DXOW 08/7,6(16( 7RX&$'& 53527 56(16( *$3*&)7 Current monitor When current mode is selected in the MultiSense, this output is capable to provide: • Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K • Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by MultiSense output: ISENSE = IOUT/K DocID022886 Rev 6 31/46 Application information VND7012AY-E Voltage on RSENSE: VSENSE = RSENSE . ISENSE = RSENSE . IOUT/K Where : • VSENSE is voltage measurable on RSENSE resistor • ISENSE is current provided from MultiSense pin in current output mode • IOUT is current flowing through output • K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin which is switched to a “current limited” voltage source, VSENSEH (see Table 9). In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH (see Table 9). Figure 34. Analogue HSD – open-load detection in off-state 9 9EDW 9EDW Q)9 Q) N *1' 0LFURFRQWUROOHU *1' 9&& 9'' )5 287 N ,1387 ([WHUQDO 3XOO8S VZLWFK 287 /RJLF N 6(Q 287 6(/ N 287 287387 &6 287 &XUUHQWPLUURU N *1' $'&LQ N 5VHQVH Q)9 287 N *1' *1' Q) *1' *1' *1' *1' ("1($'5 32/46 DocID022886 Rev 6 VND7012AY-E Application information Figure 35. Open-load / short to VCC condition 9,1 96(16( 3XOOXSFRQQHFWHG 96(16(+ 2SHQORDG 96(16(  96(16( 3XOOXS GLVFRQQHFWHG W'67.21 6KRUWWR9&& 96(16(+ *$3*&)7 Table 13. MultiSense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL MultiSense SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H TCASE and VCC monitor In this case, MultiSense output operates in voltage mode and output level is referred to device GND. Care must be taken in case a GND network protection is used, because of a voltage shift is generated between device GND and the microcontroller input GND reference. Figure 36 shows link between VMEASURED and real VSENSE signal. DocID022886 Rev 6 33/46 Application information VND7012AY-E Figure 36. GND voltage shift 9%$7 Q)9 0XOWLVHQVHYROWDJHPRGH 96(16(+ 9&&PRQLWRU 7&$6(PRQLWRU )DXOW567 9&& ,1 287 6(Q 6(/ 6(/ 53527 90($685(' 56(16( 93527 96(16( 0XOWLVHQVH 7RX&$'& 53527 N *1' '*1' '!0'#&4 VCC monitor Battery monitoring channel provides VSENSE = VCC / 4. Case temperature monitor Case temperature monitor is capable to provide information about the actual device temperature. Since a diode is used for temperature sensing, the following equation describes the link between temperature and output VSENSE level: VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C). 4.4.3 Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable VPU to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. 34/46 DocID022886 Rev 6 VND7012AY-E Application information RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: Equation 2 V PU – 4 R PU < ----------------------------------------I L ( off2 )min @ 4V Maximum demagnetization energy (VCC = 16 V) Figure 37. Maximum turn off current versus inductance 91'$