VND7040AJ-E
Double channel high-side driver with MultiSense analog feedback
for automotive applications
Datasheet - production data
– Configurable latch-off on overtemperature
or power limitation with dedicated fault
reset pin
– Loss of ground and loss of VCC
– Reverse battery with external components
– Electrostatic discharge protection
PowerSSO-16
GAPGCFT00327
Applications
• All types of Automotive resistive, inductive and
capacitive loads
Features
Max transient supply voltage
VCC
40 V
Operating voltage range
VCC
4 to 28 V
Typ. on-state resistance (per Ch) RON
40 mΩ
Current limitation (typ)
ILIMH
34 A
Standby current (max)
ISTBY
0.5 µA
• General
– Double channel smart high side driver with
MultiSense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS
outputs
• MultiSense diagnostic functions
– Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
– Off-state open-load detection
– Output short to VCC detection
– Sense enable/ disable
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
October 2014
This is information on a product in full production.
• Specially intended for Automotive Signal
Lamps (up to P27W or SAE1156 and R5W
paralleled or LED Rear Combinations)
Description
The VND7040AJ-E is a double channel high-side
driver manufactured using ST proprietary
VIPower® technology and housed in
PowerSSO-16 package. The device is designed
to drive 12 V automotive grounded loads through
a 3 V and 5 V CMOS-compatible interface,
providing protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and off-state open-load. A sense
enable pin allows off-state diagnosis to be
disabled during the module low-power mode as
well as external sense resistor sharing among
similar devices.
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1/48
www.st.com
Contents
VND7040AJ-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1
Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3
Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4
Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 30
4.1.1
4.2
Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 31
4.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4
Multisense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.5
5
2/48
4.4.1
Principle of Multisense signal generation . . . . . . . . . . . . . . . . . . . . . . . 34
4.4.2
TCASE and VCC monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4.3
Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . 37
Maximum demagnetization energy (VCC = 16 V) . . . . . . . . . . . . . . . . . . . 38
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1
6
Diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.2
PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DocID018823 Rev 9
VND7040AJ-E
Contents
7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DocID018823 Rev 9
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3
List of tables
VND7040AJ-E
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
4/48
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified). . . . . . . . . . . . . . 11
Logic inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MultiSense multiplexer addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . 31
Multisense pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DocID018823 Rev 9
VND7040AJ-E
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current sense precision vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Switching times and Pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MultiSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MultiSense timings (chip temperature and VCC sense mode) . . . . . . . . . . . . . . . . . . . . . . 20
TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Latch functionality - behavior in hard short circuit condition (TAMB $@
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47
Electrical specification
VND7040AJ-E
Figure 21. Low level logic input current
Figure 22. Logic Input hysteresis voltage
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Figure 23. FaultRST Input clamp voltage
Figure 24. Undervoltage shutdown
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Figure 25. On-state resistance vs. Tcase
Figure 26. On-state resistance vs. VCC
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VND7040AJ-E
Electrical specification
Figure 27. Turn-on voltage slope
Figure 28. Turn-off voltage slope
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Figure 29. Won vs. Tcase
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Figure 32. OFF-state open-load voltage
detection threshold
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47
Electrical specification
VND7040AJ-E
Figure 33. Vsense clamp vs. Tcase
Figure 34. Vsenseh vs. Tcase
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VND7040AJ-E
3
Protections
3.1
Power limitation
Protections
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as soon
as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the FaultRST
pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the
maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently,
reduces thermo-mechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon as
its junction temperature drops to TR (see Table 8, FaultRST = Low) or remains off
(FaultRST = High).
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as
the other components of the system (e.g. bonding wires, wiring harness, connectors, loads,
etc.) from excessive current flow. Consequently, in case of short circuit, overload or during
load power-up, the output current is clamped to a safety level, ILIMH, by operating the output
power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain
value, VDEMAG (see Table 8), allowing the inductor energy to be dissipated without
damaging the device.
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47
Application information
4
VND7040AJ-E
Application information
Figure 35. Application diagram
+5V
VDD
OUT
V CC
Rprot
OUT
FaultRST
INPUT
Rprot
OUT
Logic
OUT
Dld
Rprot
SEn
Rprot
SEL
OUTPUT
Rprot
ADC in
Multisense
Current mirror
GND
Cext
Rsense
OUT
R GND
D GND
GND
GND
GND
GND
GND
4.1
GND protection network against reverse battery
Figure 36. Simplified internal structure
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GND
VND7040AJ-E
4.1.1
Application information
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns automatically
to normal operation after the test”.
Table 12. ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle / pulse
repetition time
Pulse duration and
pulse generator
internal impedance
Level
US(1)
1
III
-112V
500 pulses
0,5 s
2a
III
+55V
500 pulses
0,2 s
5s
50μs, 2Ω
3a
IV
-220V
1h
90 ms
100 ms
0.1μs, 50Ω
3b
IV
+150V
1h
90 ms
100 ms
0.1μs, 50Ω
4(2)
IV
-7V
1 pulse
min
max
2ms, 10Ω
100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test B(3)
40V
5 pulse
1 min
400ms, 2Ω
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. Test pulse from ISO 7637-2:2004(E).
3.
With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).
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47
Application information
4.3
VND7040AJ-E
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 1
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20mA; VOHμC ≥ 4.5V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(Multisense) delivering the following signals:
•
Current monitor: current mirror of channel output current
•
VCC monitor: voltage propotional to VCC
•
TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in Table 11.
32/48
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VND7040AJ-E
Application information
VCC
Figure 37. Multisense and diagnostic – block diagram
Internal Supply
VCC – GND
Clamp
Undervoltage
shut-down
Control & Diagnostic
VCC – OUT
Clamp
FaultRST
INPUT
Gate Driver
VCC
T
SEL1
SEL0
VON
Limitation
VCC
SEn
Current
Limitation
MONITOR
MultiSense
MUX
ISENSE
RPROT
TEMP
Fault
Diagnostic
Power Limitation
Overtemperature
Temp
MONITOR
Short to VCC
Open-Load in OFF
To uC ADC
K factor
RSENSE
Current
Sense
CURRENT
MONITOR
Fault
IOUT
OUT
VSENSEH
GND
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47
Application information
4.4.1
VND7040AJ-E
Principle of Multisense signal generation
Figure 38. Multisense block diagram
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Current monitor
When current mode is selected in the Multisense, this output is capable to provide:
•
Current mirror proportional to the load current in normal operation, delivering
current proportional to the load according to known ratio named K
•
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation
can be done using simple equations
Current provided by Multisense output: ISENSE = IOUT/K
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VND7040AJ-E
Application information
Voltage on RSENSE: VSENSE = RSENSE . ISENSE = RSENSE . IOUT/K
Where :
•
VSENSE is voltage measurable on RSENSE resistor
•
ISENSE is current provided from Multisense pin in current output mode
•
IOUT is current flowing through output
•
K factor represent the ratio between PowerMOS cells and SenseMOS cells; its spread
includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the Multisense pin
which is switched to a “current limited” voltage source, VSENSEH (see Table 9).
In any case, the current sourced by the Multisense in this condition is limited to ISENSEH (see
Table 9).
The typical behavior in case of overload or hard short circuit is shown in Figure 10,
Figure 11 and Figure 12.
Figure 39. Analogue HSD – open-load detection in off-state
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47
Application information
VND7040AJ-E
Figure 40. Open-load / short to VCC condition
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Condition
Output
VOUT > VOL
Open-load
VOUT < VOL
4.4.2
Short to VCC
VOUT > VOL
Nominal
VOUT < VOL
Multisense
SEn
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because of a
voltage shift is generated between device GND and the microcontroller input GND
reference.
Figure 41 shows link between VMEASURED and real VSENSE signal.
36/48
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VND7040AJ-E
Application information
Figure 41. GND voltage shift
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VCC monitor
Battery monitoring channel provides VSENSE = VCC / 4.
Case temperature monitor
Case temperature monitor is capable to provide information about actual device
temperature. Since diode is used for temperature sensing, following equation describe link
between temperature and output VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40oC to +150oC).
4.4.3
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with to following
equation:
Equation 2
R
PU
V
–4
PU
< -----------------------------------------------I
L ( off2 )min @ 4V
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Application information
4.5
VND7040AJ-E
Maximum demagnetization energy (VCC = 16 V)
Figure 42. Maximum turn off current versus inductance
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A: Tjstart = 150 °C single pulse
B: Tjstart = 100 °C repetitive pulse
C: Tjstart = 125 °C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
38/48
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
DocID018823 Rev 9
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Package and PCB thermal data
5
Package and PCB thermal data
5.1
PowerSSO-16 thermal data
Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
("1($'5
Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
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("1($'5
Table 14. PCB properties
Dimension
Value
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal via separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on via
0.025 mm
Footprint dimension (top layer)
2.2 mm x 3.9 mm
Heatsink copper area dimension (bottom layer)
DocID018823 Rev 9
Footprint, 2 cm2 or 8 cm2
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Package and PCB thermal data
VND7040AJ-E
Figure 45. Rthj-amb vs PCB copper area in open box free air condition (one channel
on)
57+MDPE
57+MDPE
("1($'5
Figure 46. PowerSSO-16 thermal impedance junction ambient single pulse (one
channel on)
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Equation 3: pulse calculation formula
Z
THδ
= R
TH
•
δ+Z
where δ = tP/T
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THtp
(1 – δ)
VND7040AJ-E
Package and PCB thermal data
Figure 47. Thermal fitting model of a double-channel HSD in PowerSSO-16
("1($'5
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the
embedded protections (power limitation or thermal cycling during thermal shutdown) are not
triggered.
Table 15. Thermal parameters
Area/island
(cm2)
Footprint
2
8
4L
R1 = R7 (°C/W)
2.3
R2 = R8 (°C/W)
1.8
R3 (°C/W)
7
7
7
5
R4 (°C/W)
16
6
6
4
R5 (°C/W)
30
20
10
3
R6 (°C/W)
26
20
18
7
C1 = C7 (W.s/°C)
0.00045
C2 = C8 (W.s/°C)
0.03
C3 (W.s/°C)
0.1
C4 (W.s/°C)
0.2
0.3
0.3
0.4
C5 (W.s/°C)
0.4
1
1
4
C6 (W.s/°C)
3
5
7
18
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Package information
VND7040AJ-E
6
Package information
6.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at www.st.com.
ECOPACK® is an ST trademark.
6.2
PowerSSO-16 package information
Figure 48. PowerSSO-16 package dimensions
("1($'5
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VND7040AJ-E
Package information
Table 16. PowerSSO-16 mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
Θ
0°
Θ1
0°
Θ2
5°
15°
Θ3
5°
15°
8°
A
1.70
A1
0.00
0.10
A2
1.10
1.60
b
0.20
0.30
b1
0.20
c
0.19
c1
0.19
D
D1
0.25
0.28
0.25
0.20
0.23
4.90 BSC
3.60
4.20
e
0.50 BSC
E
6.00 BSC
E1
3.90 BSC
E2
1.90
2.50
h
0.25
0.50
L
0.40
0.60
L1
1.00 REF
N
16
R
0.07
R1
0.07
S
0.20
0.85
Tolerance of form and position
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.08
eee
0.10
fff
0.10
ggg
0.15
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Order codes
7
VND7040AJ-E
Order codes
Table 17. Device summary
Order codes
Package
PowerSSO-16
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Tube
Tape and reel
VND7040AJ-E
VND7040AJTR-E
DocID018823 Rev 9
VND7040AJ-E
8
Revision history
Revision history
Table 18. Revision history
Date
Revision
08-Jun-2011
1
Initial release.
2
Updated Features list
Updated Table 2: Suggested connections for unused and not
connected pins
Updated Figure 2: Configuration diagram (top view)
Table 3: Absolute maximum ratings:
– ISENSE, -IOUT: updated value
– VCCPK, VCCJS: added row
– -VSENSE, VCC: removed row
Table 5: Power section:
– VUSDReset, IGND(ON): added row
Updated following tables:
– Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless
otherwise specified)
– Table 7: Logic inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C)
Table 8: Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– tLATCH_RST: updated typ and max values;
– VDEMAG: updated test conditions
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– updated several values;
– VOUT_MSD, VSENSE_SAT, ISENSE_SAT, tD_OL_V: added rows
Updated Figure 6: Switching times and Pulse skew
Removed Figure 5: Pulse skew
Added Figure 9: TDSTKON
Updated Section 2.4: Waveforms
Added following chapters:
– Chapter 3: Protections
– Chapter 4: Application information
Updated Section 5.1: PowerSSO-16 thermal data
3
Table 5: Power section:
– IGND(ON): Updated max value
Updated Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless
otherwise specified)
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– VSENSE_CL: updated test conditions and min value
– KOL, KLED, dKLED/KLED, K0, dK0/K0, K1, dK1/K1, K2, dK2/K2, K3,
dK3/K3, VSENSEH: updated values
20-Sep-2012
17-Oct-2012
Changes
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Revision history
VND7040AJ-E
Table 18. Revision history (continued)
Date
18-Feb-2013
17-Jun-2013
46/48
Revision
Changes
4
Updated Table 2: Suggested connections for unused and not
connected pins and Table 4: Thermal data
Table 5: Power section:
– tD_STBY: updated max value
Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless
otherwise specified):
– WON, WOFF, tSKEW: updated values
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– dKcal/Kcal: added row
– VSENSE_TC: updated values and test conditions
– VSENSE_VCC: updated test conditions
Updated Table 11: MultiSense multiplexer addressing
Removed following tables:
Table: Electrical transient requirements (part 1/3)
Table: Electrical transient requirements (part 2/3)
Table: Electrical transient requirements (part 3/3)
Updated Section 3.1: Power limitation, Section 3.2: Thermal
shutdown, Section 3.4: Negative voltage clamp and Section 4.1.1:
Diode (DGND) in the ground line
Removed Section: Load dump protection
Added Section 4.2: Immunity against transient electrical
disturbances
Updated Section 4.4.1: Principle of Multisense signal generation
Updated Figure 41: GND voltage shift
Added Section 4.5: Maximum demagnetization energy (VCC = 16 V)
Updated Section 5.1: PowerSSO-16 thermal data
5
Table 3: Absolute maximum ratings:
– VCCPK: updated parameter
– -IOUT, ISENSE: updated value
– EMAX: updated parameter and value
Table 5: Power section:
– VF: updated test conditions
Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless
otherwise specified):
– (dVOUT/dt)on, (dVOUT/dt)off, WON, WOFF: updated values
Table 8: Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– THYST, tLATCH_RST: added note
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– KOL, KLED, K0, K1, K3: updated values
Added Figure 4: IOUT/ISENSE versus IOUT and Figure 5: Current
sense precision vs. IOUT
Added Section 2.5: Electrical characteristics curves
Updated Section 4.5: Maximum demagnetization energy
(VCC = 16 V) and Section 6.2: PowerSSO-16 package information
DocID018823 Rev 9
VND7040AJ-E
Revision history
Table 18. Revision history (continued)
Date
Revision
Changes
05-Jul-2013
6
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– K1: updated values
Updated Figure 4: IOUT/ISENSE versus IOUT
20-Sep-2013
7
Updated disclaimer.
04-Jun-2014
8
Updated Section 6.2: PowerSSO-16 package information
21-Oct-2014
9
Updated Table 16: PowerSSO-16 mechanical data
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VND7040AJ-E
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