VND7050AJ12
Double channel high-side driver with CurrentSense analog
feedback for automotive applications
Datasheet - production data
•
PowerSSO-12
GAPG040515 1112CFT
Features
Max transient supply voltage
VCC
40 V
Operating voltage range
VCC
4 V to 28 V
Minimum cranking supply
voltage (VCC decreasing)
VUSD_Cranking
2.85 V
Typ. on-state resistance
(per Ch)
RON
50 mΩ
Current limitation (typ)
ILIMH
30 A
Standby current (max)
ISTBY
0.5 µA
•
•
•
•
September 2015
Applications
•
•
Automotive qualified
Extreme low voltage operation for deep cold
cranking applications (compliant with LV124,
revision 2013)
General
−
Double channel smart high-side driver
with CurrentSense analog feedback
−
Very low standby current
−
Compatible with 3 V and 5 V CMOS
outputs
CurrentSense diagnostic functions
−
Multiplexed analog feedback of: load
current with high precision proportional
current mirror
−
Overload and short to ground (power
limitation) indication
−
Thermal shutdown indication
−
Off-state open-load detection
−
Output short to VCC detection
−
Sense enable/ disable
Protections
−
Undervoltage shutdown
−
Overvoltage clamp
−
Load current limitation
−
Self limiting of fast thermal transients
−
Loss of ground and loss of VCC
−
Reverse battery with external
components
−
Electrostatic discharge protection
All types of Automotive resistive, inductive
and capacitive loads
Specially intended for Automotive Signal
Lamps (up to P27W or SAE1156 or LED
Rear Combinations)
Description
The device is a double channel high-side driver
manufactured using ST proprietary VIPower®
technology and housed in PowerSSO-12
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and
5 V CMOS compatible interface, providing
protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown.
A current sense delivers high precision
proportional load current sense in addition to the
detection of overload and short circuit to ground,
short to VCC and off-state open-load.
A sense enable pin allows off-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
DocID027585 Rev 3
This is information on a product in full production.
1/43
www.st.com
Contents
VND7050AJ12
Contents
1
Block diagram and pin description ................................................ 5
2
Electrical specification.................................................................... 7
3
4
2.1
Absolute maximum ratings ................................................................ 7
2.2
Thermal data ..................................................................................... 8
2.3
Main electrical characteristics ........................................................... 8
2.4
Waveforms ...................................................................................... 18
2.5
Electrical characteristics curves ...................................................... 19
Protections..................................................................................... 23
3.1
Power limitation ............................................................................... 23
3.2
Thermal shutdown........................................................................... 23
3.3
Current limitation ............................................................................. 23
3.4
Negative voltage clamp ................................................................... 23
Application information ................................................................ 24
4.1
GND protection network against reverse battery............................. 24
4.1.1
Diode (DGND) in the ground line ..................................................... 25
4.2
Immunity against transient electrical disturbances .......................... 25
4.3
MCU I/Os protection........................................................................ 26
4.4
Behaviour during engine start transients ......................................... 26
4.5
CurrentSense - analog current sense ............................................. 28
4.5.1
Principle of CurrenSense signal generation ..................................... 29
4.5.2
Short to VCC and OFF-state open-load detection ........................... 31
5
Maximum demagnetization energy (VCC = 16 V) ........................ 33
6
Package and PCB thermal data .................................................... 34
6.1
7
PowerSSO-12 thermal data ............................................................ 34
Package information ..................................................................... 37
7.1
PowerSSO-12 package information ................................................ 37
7.2
PowerSSO-12 packing information ................................................. 38
7.3
PowerSSO-12 marking information ................................................. 40
8
Order codes ................................................................................... 41
9
Revision history ............................................................................ 42
2/43
DocID027585 Rev 3
VND7050AJ12
List of tables
List of tables
Table 1: Pin functions ................................................................................................................................. 5
Table 2: Suggested connections for unused and not connected pins ........................................................ 6
Table 3: Absolute maximum ratings ........................................................................................................... 7
Table 4: Thermal data ................................................................................................................................. 8
Table 5: Electrical characteristics during cranking ..................................................................................... 8
Table 6: Power section ............................................................................................................................... 9
Table 7: Switching....................................................................................................................................... 9
Table 8: Logic inputs ................................................................................................................................. 10
Table 9: Protections .................................................................................................................................. 11
Table 10: CurrentSense ............................................................................................................................ 11
Table 11: Truth table ................................................................................................................................. 17
Table 12: CurrentSense multiplexer addressing ...................................................................................... 17
Table 13: ISO 7637-2 - electrical transient conduction along supply line................................................. 26
Table 14: Test parameters, E-11 Start pulses .......................................................................................... 27
Table 15: Cranking operating mode ......................................................................................................... 28
Table 16: CurrentSense pin levels in off-state .......................................................................................... 31
Table 17: PCB properties ......................................................................................................................... 34
Table 18: Thermal parameters ................................................................................................................. 36
Table 19: PowerSSO-12 mechanical data................................................................................................ 38
Table 20: Reel dimensions ....................................................................................................................... 38
Table 21: PowerSSO-12 carrier tape dimensions .................................................................................... 39
Table 22: Device summary ....................................................................................................................... 41
Table 23: Document revision history ........................................................................................................ 42
DocID027585 Rev 3
3/43
List of figures
VND7050AJ12
List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Configuration diagram (top view)................................................................................................. 6
Figure 3: Current and voltage conventions ................................................................................................. 7
Figure 4: IOUT/ISENSE versus IOUT....................................................................................................... 14
Figure 5: Current sense accuracy versus IOUT ....................................................................................... 15
Figure 6: Switching times and Pulse skew ............................................................................................... 15
Figure 7: CurrentSense timings ................................................................................................................ 16
Figure 8: TDSTKON.................................................................................................................................. 16
Figure 9: Standby mode activation ........................................................................................................... 18
Figure 10: Standby state diagram ............................................................................................................. 18
Figure 11: OFF-state output current ......................................................................................................... 19
Figure 12: Standby current ....................................................................................................................... 19
Figure 13: IGND(ON) vs. Tcase ............................................................................................................... 19
Figure 14: Logic Input high level voltage .................................................................................................. 19
Figure 15: Logic Input low level voltage.................................................................................................... 19
Figure 16: High level logic input current ................................................................................................... 19
Figure 17: Low level logic input current .................................................................................................... 20
Figure 18: Logic Input hysteresis voltage ................................................................................................. 20
Figure 19: Undervoltage shutdown ........................................................................................................... 20
Figure 20: On-state resistance vs. Tcase ................................................................................................. 20
Figure 21: On-state resistance vs. Vcc ..................................................................................................... 20
Figure 22: Turn-on voltage slope .............................................................................................................. 20
Figure 23: Turn-off voltage slope .............................................................................................................. 21
Figure 24: Won vs Tcase .......................................................................................................................... 21
Figure 25: Woff vs Tcase .......................................................................................................................... 21
Figure 26: ILIMH vs. Tcase ....................................................................................................................... 21
Figure 27: OFF-state open-load voltage detection threshold ................................................................... 21
Figure 28: Vsense clamp vs Tcase........................................................................................................... 21
Figure 29: Vsenseh vs Tcase ................................................................................................................... 22
Figure 30: Application diagram ................................................................................................................. 24
Figure 31: Simplified internal structure - GND network protection with Schottly diode ............................ 24
Figure 32: Simplified internal structure - GND network protection with MOSFET .................................... 25
Figure 33: Cranking profile ....................................................................................................................... 27
Figure 34: CurrentSense and diagnostic – block diagram........................................................................ 28
Figure 35: CurrentSense block diagram ................................................................................................... 29
Figure 36: Analogue HSD – open-load detection in off-state ................................................................... 30
Figure 37: Open-load / short to VCC condition ......................................................................................... 31
Figure 38: Maximum turn off current versus inductance .......................................................................... 33
Figure 39: PowerSSO-12 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 34
Figure 40: PowerSSO-12 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 34
Figure 41: Rthj-amb vs PCB copper area in open box free air condition (one channel on) ..................... 35
Figure 42: PowerSSO-12 thermal impedance junction ambient single pulse (one channel on) .............. 35
Figure 43: Thermal fitting model of a double-channel HSD in PowerSSO-12.......................................... 36
Figure 44: PowerSSO-12 package dimensions ........................................................................................ 37
Figure 45: PowerSSO-12 reel 13" ............................................................................................................ 38
Figure 46: PowerSSO-12 carrier tape ...................................................................................................... 39
Figure 47: PowerSSO-12 schematic drawing of leader and trailer tape .................................................. 40
Figure 48: PowerSSO-12 marking information ......................................................................................... 40
4/43
DocID027585 Rev 3
VND7050AJ12
1
Block diagram and pin description
Block diagram and pin description
Figure 1: Block diagram
Table 1: Pin functions
Name
VCC
OUTPUT0,1
GND
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode/resistor
network.
INPUT0,1
Voltage controlled input pins with hysteresis, compatible with 3 V and 5 V CMOS
outputs. They control output switch state.
CurrentSense
Multiplexed analog sense output pin; it delivers a current proportional to the load
current.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the
CurrentSense diagnostic pin.
SEL
Active high compatible with 3 V and 5 V CMOS outputs pin; it addresses the
CurrentSense multiplexer.
DocID027585 Rev 3
5/43
Block diagram and pin description
VND7050AJ12
Figure 2: Configuration diagram (top view)
Table 2: Suggested connections for unused and not connected pins
Connection/pin
CurrentSense
Floating
Not allowed
To ground
Through 1 kΩ
resistor
N.C.
X
(1)
X
Output
Input
SEn, SEL
X
X
X
Not
allowed
Through 15 kΩ
resistor
Through 15 kΩ
resistor
Notes:
(1)X:
6/43
do not care.
DocID027585 Rev 3
VND7050AJ12
2
Electrical specification
Electrical specification
Figure 3: Current and voltage conventions
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 3: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
38
V
-VCC
Reverse DC supply voltage
0.3
V
VCCPK
Maximum transient supply voltage (ISO 16750-2:2010 Test B
clamped to 40 V; RL = 4 Ω)
40
V
VCCJS
Maximum jump start voltage for single pulse short circuit protection
28
V
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT0,1 DC output current
Internally limited
-IOUT
Reverse DC output current
IIN
INPUT0,1 DC input current
ISEn
SEn DC input current
ISEL
SEL DC input current
ISENSE
11
-1 to 10
CurrentSense pin DC output current (VGND = VCC and VSENSE < 0 V)
10
CurrentSense pin DC output current in reverse (VCC < 0V)
-20
DocID027585 Rev 3
A
mA
mA
7/43
Electrical specification
VND7050AJ12
Symbol
Parameter
Unit
30
mJ
EMAX
Maximum switching energy (single pulse)
(TDEMAG = 0.4 ms; Tjstart = 150 °C)
VESD
Electrostatic discharge (JEDEC 22A-114F)
•
INPUT0,1
•
CurrentSense
•
SEn, SEL
•
OUTPUT0,1
•
VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Tstg
2.2
Value
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
°C
Thermal data
Table 4: Thermal data
Symbol
Parameter
Typ. value
Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8)
Rthj-amb
Rthj-amb
(1)(2)
Unit
6.4
Thermal resistance junction-ambient (JEDEC JESD 51-5)
(1)(3)
59
Thermal resistance junction-ambient (JEDEC JESD 51-7)
(1)(2)
25
°C/W
Notes:
(1)One
2.3
channel ON.
(2)Device
mounted on four-layers 2s2p PCB.
(3)Device
mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace.
Main electrical characteristics
7 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5: Electrical characteristics during cranking
Symbol
Parameter
VUSD_Cranking
Minimum cranking supply voltage
(VCC decreasing)
RON
TTSD(2)
Test conditions
2.85
On-state resistance (1)
IOUT = 0.5 A; VCC = 2.85 V;
VCC decreasing
Shutdown temperature (VCC
decreasing)
VCC = 2.85 V
Notes:
(1)For
each channel.
(2)Parameter
8/43
Min. Typ. Max. Unit
guaranteed by design and characterization; not subject to production test.
DocID027585 Rev 3
V
500 mΩ
140
°C
VND7050AJ12
Electrical specification
Table 6: Power section
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
4
13
VUSD
Undervoltage shutdown
2.85
VUSDReset
Undervoltage shutdown
reset
5
VUSDhyst
Undervoltage shutdown
hysteresis
RON
Vclamp
ISTBY
On-state resistance
Clamp voltage
50
IOUT = 2 A; Tj = 150 °C
100 mΩ
IOUT = 2 A; VCC = 4 V; Tj = 25 °C
75
IS = 20 mA; Tj = -40 °C
38
IS = 20 mA; 25°C < Tj < 150°C
41
46
IS(ON)
VF
V
0.5
µA
Supply current in standby at VCC = 13 V; VIN = VOUT = VSEn = 0 V;
VSEL = 0 V; Tj = 85 °C (3)
VCC = 13 V (2)
0.5
µA
3
µA
Standby mode blanking
time
VCC = 13 V; VIN = VOUT = VSEL = 0 V;
VSEn = 5 V to 0 V
Supply current
VCC = 13 V; VSEn = VSEL = 0 V;
VIN0 = 5 V; VIN1 = 5 V; IOUT0 = 0 A;
IOUT1 = 0 A
Control stage current
IGND(ON) consumption in ON state.
All channels active.
IL(off)
52
VCC = 13 V; VIN = VOUT = VSEn = 0 V;
VSEL = 0 V; Tj = 25 °C
VCC = 13 V; VIN = VOUT = VSEn = 0 V;
VSEL = 0 V; Tj = 125 °C
tD_STBY
V
0.3
IOUT = 2 A; Tj = 25 °C
(1)
28
Off-state output current at
VCC = 13 V(1)
Output - VCC diode
voltage(1)
60
300 550
5
VCC = 13 V; VSEn = 5 V; VSEL = 0 V;
VIN0 = 5 V; VIN1 = 5 V; IOUT0 = 2 A;
IOUT1 = 2 A
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25 °C
0
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C
0
µA
8
mA
12
mA
0.01 0.5
µA
3
IOUT = -2 A; Tj = 150 °C
0.7
V
Notes:
(1)For
each channel.
(2)PowerMOS
(3)Parameter
leakage included.
specified by design; not subject to production test.
Table 7: Switching
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol
Parameter
td(on)(1)
Turn-on delay time at Tj = 25°C
td(off)(1)
Turn-off delay time at Tj = 25°C
(dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25°C
(dVOUT/dt)off(1) Turn-off voltage slope at Tj = 25°C
DocID027585 Rev 3
Test conditions Min. Typ.
RL = 6.5 Ω
RL = 6.5 Ω
Max.
10
60
120
10
40
100
0.1
0.3
0.7
0.1 0.32
0.7
Unit
µs
V/µs
9/43
Electrical specification
VND7050AJ12
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol
Parameter
Test conditions Min. Typ.
Max.
Unit
WON
Switching energy losses at turn-on (twon)
RL = 6.5 Ω
—
0.25 0.33 (2) mJ
WOFF
Switching energy losses at turn-off (twoff)
RL = 6.5 Ω
—
0.23 0.31(2)
mJ
Differential pulse skew (tPHL - tPLH)
RL = 6.5 Ω
-80
-30
20
µs
Max.
Unit
0.9
V
tSKEW
(1)
Notes:
(1)See Figure 6: "Switching times and Pulse skew"
(2)Parameter
guaranteed by design and characterization; not subject to production test.
Table 8: Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
INPUT0,1 characteristics
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
VIN = 0.9 V
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
Input clamp voltage
1
V
5.3
IIN = -1 mA
µA
7.2
-0.7
V
SEL characteristics (7 V < VCC < 18 V)
VSELL
Input low level voltage
ISELL
Low level input current
VSELH
Input high level voltage
ISELH
High level input current
VSEL(hyst)
Input hysteresis voltage
VSELCL
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
Input clamp voltage
V
V
5.3
IIN = -1 mA
µA
7.2
-0.7
V
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
VSEn(hyst)
Input hysteresis voltage
VSEnCL
10/43
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
IIN = -1 mA
DocID027585 Rev 3
V
µA
V
5.3
7.2
-0.7
V
VND7050AJ12
Electrical specification
Table 9: Protections
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
ILIMH
DC short circuit current
ILIML
Short circuit current during
thermal cycling
TTSD
Shutdown temperature
TR
Reset temperature(1)
TRS
Thermal reset of fault
diagnostic indication
THYST
4 V < VCC < 18 V
Max.
21
30
42
(1)
Unit
42
VCC = 13 V; TR < Tj < TTSD
A
10
150
175
TRS + 1
TRS + 7
VSEn = 5 V
200
°C
135
Thermal hysteresis (TTSD TR)(1)
7
Tj = -40 °C; VCC = 13 V
Turn-off output voltage
clamp
Output voltage drop
limitation
VON
Typ.
VCC = 13 V
ΔTJ_SD Dynamic temperature
VDEMAG
Min.
60
K
IOUT = 2 A; L = 6 mH;
Tj = -40 °C
VCC - 38
IOUT = 2 A; L = 6 mH;
Tj = 25 °C to +150 °C
VCC - 41 VCC - 46 VCC - 52
V
IOUT = 0.2 A
20
mV
Notes:
(1)Parameter
guaranteed by design and characterization; not subject to production test.
Table 10: CurrentSense
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
VSENSE_CL
Parameter
CurrentSense clamp voltage
Test conditions
VSEn = 0 V; ISENSE = 1 mA
Min. Typ. Max. Unit
-17
VSEn = 0 V; ISENSE = -1 mA
-12
7
V
V
CurrentSense characteristics
KOL
dKcal/Kcal(1)(2)
KLED
IOUT/ISENSE
IOUT = 0.01 A;
VSENSE = 0.5 V; VSEn = 5 V
440
Current sense ratio drift at
calibration point
IOUT = 0.01 A to 0.05 A;
Ical = 30 mA;
VSENSE = 0.5 V; VSEn = 5 V
-30
IOUT/ISENSE
IOUT = 0.05 A;
VSENSE = 0.5 V; VSEn = 5 V
530
IOUT = 0.05 A;
VSENSE = 0.5 V; VSEn = 5 V
-25
IOUT/ISENSE
IOUT = 0.2 A;
VSENSE = 0.5 V; VSEn = 5 V
830
Current sense ratio drift
IOUT = 0.2 A;
VSENSE = 0.5 V; VSEn = 5 V
-20
IOUT/ISENSE
IOUT = 0.4 A; VSENSE = 4 V;
VSEn = 5 V
915
dKLED/KLED(1)(2) Current sense ratio drift
K0
dK0/K0(1)(2)
K1
DocID027585 Rev 3
30
%
1450 2200
25
%
1400 1935
20
%
1300 1700
11/43
Electrical specification
VND7050AJ12
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
dK1/K1(1)(2)
K2
dK2/K2(1)(2)
K3
dK3/K3(1)(2)
ISENSE0
VOUT_MSD(1)
VSENSE_SAT
ISENSE_SAT
12/43
(1)
Parameter
Test conditions
Min. Typ. Max. Unit
Current sense ratio drift
IOUT = 0.4 A; VSENSE = 4 V;
VSEn = 5 V
-15
IOUT/ISENSE
IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V
980
Current sense ratio drift
IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V
-10
IOUT/ISENSE
IOUT = 4.5 A; VSENSE = 4 V;
VSEn = 5 V
Current sense ratio drift
IOUT = 4.5 A; VSENSE = 4 V;
VSEn = 5 V
-5
5
%
CurrentSense disabled:
VSEn = 0 V;
0
0.5
µA
CurrentSense disabled:
-1 V < VSENSE < 5 V(1)
-0.5
0.5
µA
CurrentSense enabled:
VSEn = 5 V;
All channel ON;
IOUTX = 0 A;
ChX diagnostic selected;
•
E.g. Ch0:
VIN0 = 5 V; VIN1 = 5 V;
CurrentSense leakage current
VSEL = 0 V;
IOUT0 = 0 A;
IOUT1 = 2 A
0
2
µA
CurrentSense enabled:
VSEn = 5 V;
ChX channel OFF;
ChX diagnostic selected;
•
E.g. Ch0:
VIN0 = 0 V; VIN1 = 5 V;
VSEL = 0 V;
IOUT1 = 2 A
0
2
µA
15
%
1230 1470
10
%
1095 1215 1335
Output Voltage for
CurrentSense shutdown
VSEn = 5 V;
RSENSE = 2.7 kΩ
•
E.g. Ch0:
VIN0 = 5 V;
VSEL = 0 V;
IOUT0 = 2 A
CurrentSense saturation
voltage
VCC = 7 V;
RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN0 = 5 V;
VSEL = 0 V; IOUT0 = 4.5 A;
Tj = 150°C
5
V
CS saturation current
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
4
mA
DocID027585 Rev 3
5
V
VND7050AJ12
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL = 0 V; Tj = 150°C
6
VOL
Off-state open-load voltage
detection threshold
VSEn = 5 V; ChX OFF;
ChX diagnostic selected
•
E.g: Ch0
VIN0 = 0 V; VSEL = 0 V
2
IL(off2)
Off-state output sink current
VIN = 0 V; VOUT = VOL
IOUT_SAT(1)
Output saturation current
A
Off-state diagnostic
3
-100
tDSTKON
VSEn = 5 V; ChX ON to OFF
transition
ChX diagnostic selected
Off-state diagnostic delay time
•
E.g: Ch0
from falling edge of INPUT
100
VIN0 = 5 V to 0 V;
(see Figure 8: "TDSTKON")
VSEL = 0 V;
IOUT0 = 0 A;
VOUT = 4 V
tD_OL_V
Settling time for valid OFFstate open load diagnostic
indication from rising edge of
SEn
tD_VOL
VSEn = 5 V; ChX OFF
ChX diagnostic selected
Off-state diagnostic delay time •
E.g: Ch0
from rising edge of VOUT
VIN0 = 0 V;
VSEL = 0 V;
VOUT = 0 V to 4 V
350
VIN0 = 0 V; VIN1 = 0 V;
VSEL = 0 V; VOUT0 = 4 V;
VSEn = 0 V to 5 V
5
4
V
-15
µA
700
µs
60
µs
30
µs
6.6
V
30
mA
Fault diagnostic feedback (see Table 11: "Truth table")
VCC = 13 V; RSENSE = 1 kΩ
•
E.g: Ch0 in open load
VIN0 = 0 V;
VSEn = 5 V;
VSEL = 0 V;
IOUT0 = 0 A;
VOUT = 4 V
VSENSEH
CurrentSense output voltage
in fault condition
ISENSEH
CurrentSense output current in
VCC = 13 V; VSENSE = 5 V
fault condition
5
7
20
CurrentSense timings (current sense mode - see Figure 7: "CurrentSense timings")(3)
tDSENSE1H
Current sense settling time
from rising edge of SEn
VIN = 5 V; VSEn = 0 V to
5 V; RSENSE = 1 kΩ;
RL = 6.5 Ω
tDSENSE1L
Current sense disable delay
time from falling edge of SEn
VIN = 5 V; VSEn = 5 V to
0 V; RSENSE = 1 kΩ;
RL = 6.5 Ω
tDSENSE2H
Current sense settling time
from rising edge of INPUT
VIN = 0 V to 5 V;
VSEn = 5 V; RSENSE = 1 kΩ;
RL = 6.5 Ω
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60
µs
5
20
µs
100
250
µs
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Electrical specification
VND7050AJ12
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
ΔtDSENSE2H
Current sense settling time
from rising edge of IOUT
(dynamic response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ;
ISENSE = 90 % of ISENSEMAX;
RL = 6.5 Ω
tDSENSE2L
Current sense turn-off delay
time from falling edge of
INPUT
VIN = 5 V to 0 V;
VSEn = 5 V; RSENSE = 1 kΩ;
RL = 6.5 Ω
Min. Typ. Max. Unit
100
µs
250
µs
VIN0 = 5 V; VIN1 = 5 V;
VSEn = 5 V;
CurrentSense transition delay
VSEL = 0 V to 5 V;
from ChX to ChY
IOUT0 = 0A; IOUT1 = 3 A;
RSENSE = 1 kΩ
20
µs
VIN0 = 5 V; VIN1 = 0 V;
CurrentSense transition delay VSEn = 5 V;
from stable current sense on VSEL = 0 V to 5 V;
ChX to VSENSEH on ChY
IOUT0 = 3 A; VOUT1 = 4 V;
RSENSE = 1 kΩ
20
µs
50
CurrentSense timings (Multiplexer transition times) (3)
tD_XtoY
tD_CStoVSENSEH
Notes:
(1)Parameter
(2)All
guaranteed by design and characterization; not subject to production test.
values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
(3)Transition
delay are measured up to +/- 10% of final conditions.
Figure 4: IOUT/ISENSE versus IOUT
14/43
DocID027585 Rev 3
VND7050AJ12
Electrical specification
Figure 5: Current sense accuracy versus IOUT
Figure 6: Switching times and Pulse skew
twoff
twon
VOUT
Vcc
80% Vcc
ON
OFF
dVOUT/dt
dVOUT/dt
20% Vcc
t
INPUT
td(off)
td(on)
tpLH
tpHL
t
GAPGCFT00797
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Electrical specification
VND7050AJ12
Figure 7: CurrentSense timings
Figure 8: TDSTKON
VINPU T
VOU T
VOU T > VOL
CurrentSense
TDSTKON
GAPG0912131101CFT
16/43
DocID027585 Rev 3
VND7050AJ12
Electrical specification
Table 11: Truth table
Mode
Standby
Conditions
INX SEn SEL OUTX CurrentSense
All logic inputs low
Nominal load
connected;
Tj < 150°C
Normal
L
Hi-Z
L
L
See (1)
H See (1)
H
See (1)
Outputs configured for
auto-restart
H
H
See (1)
Outputs configured for
latch off
L
L
See (1)
H
See (1)
Output cycles with
temperature hysteresis
L
See (1)
Output latches off
L
L
Hi-Z
Hi-Z
Re-start when
VCC > VUSD +
VUSDhyst (rising)
H
See (1)
H
See (1)
TTSD or
ΔTj > ΔTj_SD
L
Comments
See (1)
H
L
X
X
See (1)
See (1)
External pull up
Notes:
(1)Refer
to Table 12: "CurrentSense multiplexer addressing"
Table 12: CurrentSense multiplexer addressing
SEn SEL
CurrentSense output
MUX
channel
Normal mode
Overload
Off-state diag.
Negative
output
L
X
Hi-Z
H
L
Channel 0
diagnostic
ISENSE =
1/K * IOUT0
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
H
Channel 1
diagnostic
ISENSE =
1/K * IOUT1
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
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Electrical specification
2.4
VND7050AJ12
Waveforms
Figure 9: Standby mode activation
Figure 10: Standby state diagram
Normal Operation
t > tD_STBY
INx = Low
AND
SEn = Low
AND
SEL = Low
INx = High
OR
SEn = High
OR
SEL = High
Stand-by Mode
GAPG2911131147CFT
18/43
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VND7050AJ12
2.5
Electrical specification
Electrical characteristics curves
Figure 11: OFF-state output current
Figure 12: Standby current
Figure 13: IGND(ON) vs. Tcase
Figure 14: Logic Input high level voltage
Figure 15: Logic Input low level voltage
Figure 16: High level logic input current
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Electrical specification
20/43
VND7050AJ12
Figure 17: Low level logic input current
Figure 18: Logic Input hysteresis voltage
Figure 19: Undervoltage shutdown
Figure 20: On-state resistance vs. Tcase
Figure 21: On-state resistance vs. Vcc
Figure 22: Turn-on voltage slope
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VND7050AJ12
Electrical specification
Figure 23: Turn-off voltage slope
Figure 24: Won vs Tcase
Figure 25: Woff vs Tcase
Figure 26: ILIMH vs. Tcase
Figure 27: OFF-state open-load voltage
detection threshold
Figure 28: Vsense clamp vs Tcase
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Electrical specification
VND7050AJ12
Figure 29: Vsenseh vs Tcase
VSENSEH [V]
10
9
8
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
T [°C]
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100
125
150
175
GAPG2110131629CFT
VND7050AJ12
3
Protections
3.1
Power limitation
Protections
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of ΔTj_SD. The output MOSFET switches on and
cycles with a thermal hysteresis according to the maximum instantaneous power which can
be handled. The protection prevents fast thermal transient effects and, consequently,
reduces thermo-mechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered. The
device switches on again as soon as its junction temperature drops to TR.
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
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Application information
4
VND7050AJ12
Application information
Figure 30: Application diagram
4.1
GND protection network against reverse battery
Figure 31: Simplified internal structure - GND network protection with Schottly diode
24/43
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VND7050AJ12
Application information
Figure 32: Simplified internal structure - GND network protection with MOSFET
4.1.1
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (»600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
To comply with LV124, E-11 "severe" start pulse, a Schottky diode (see Figure 31:
"Simplified internal structure - GND network protection with Schottly diode") or N-channel
MOSFET (see Figure 32: "Simplified internal structure - GND network protection with
MOSFET") is recommended in order to ensure a lower ground network shift (≤ 350 mV).
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 13: "ISO 7637-2 electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
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Application information
VND7050AJ12
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 13: ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Level
US(1)
Minimum
number of
pulses or test
time
Burst cycle / pulse
repetition time
min
Pulse duration and
pulse generator
internal impedance
max
2ms, 10Ω
1
III
-112V
500 pulses
0,5 s
2a
III
+55V
500 pulses
0,2 s
5s
50µs, 2Ω
3a
IV
-220V
1h
90 ms
100 ms
0.1µs, 50Ω
3b
IV
+150V
1h
90 ms
100 ms
0.1µs, 50Ω
IV
-7V
1 pulse
4
(2)
100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test B (3)
40V
5 pulse
1 min
400ms, 2Ω
Notes:
(1)U
S
4.3
is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test
pulse from ISO 7637-2:2004(E).
(3)With
40 V external suppressor referred to ground (-40°C < Tj < 150°C).
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Behaviour during engine start transients
The battery voltage drops every time an engine start occurs as well as in start&stop
automotive systems.
The device is designed to operate during engine start pulses without external components.
In particular, the device achieves functional status A, for both E-11 start pulses, “normal”
and “severe” as defined in Table 14: "Test parameters, E-11 Start pulses".
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VND7050AJ12
Application information
Functional status A is defined as follows: the DUT (device under test) must fulfill all
functions during and after exposure to the test parameters.
Table 14: Test parameters, E-11 Start pulses
Parameter
Test pulse “normal”
Test pulse “severe”
VB
11,0 V
11,0 V
VT
4,5 V (0%, -4%)
3,2 V +0,2V
VS
4,5 V (0%, -4%)
5,0 V (0%, -4%)
VA
6,5 V (0%, -4%)
6,0 V (0%, -4%)
VR
2V
2V
tf
≤1 ms
≤1 ms
t4
0 ms
19 ms
t5
0 ms
≤1 ms
t6
19 ms
329 ms
t7
50 ms
50 ms
t8
10 s
10 s
tr
100 ms
100 ms
f
2 Hz
2 Hz
Break between two cycles
2s
2s
Test cycles
10
10
For more details see standard norm “LV124 - Electric and Electronic Components
in Motor Vehicles up to 3.5 t”.
Figure 33: Cranking profile
The extremely low VUSD_Cranking, minimum cranking supply voltage (VCC decreasing),
specification of 2.85 V, much lower than the standard requirement, allows the device
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Application information
VND7050AJ12
operating in all the applications where a ground network protection is required (see Section
4.1: "GND protection network against reverse battery").
Table 15: Cranking operating mode
Operating range
Normal mode 4 V to 28 V
Cranking mode 2.85 V to 4 V
4.5
Voltage range
Operating mode
18 V - 28 V
All functions are performed as specified. Some
deviations of the electrical characteristics.
7 V - 18 V
All functions are performed as specified. All
parameters in range.
4V-7V
All functions are performed as specified. Some
deviations of the electrical characteristics.
2.85 V - 4 V
Device is operating (VCC decreasing). Device is
protected. No diagnostic. Electrical parameters
deviations.
CurrentSense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(CurrentSense) delivering a current mirror of channel output current
Figure 34: CurrentSense and diagnostic – block diagram
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VND7050AJ12
4.5.1
Application information
Principle of CurrenSense signal generation
Figure 35: CurrentSense block diagram
Current monitor
This output is capable of providing:
•
•
Current mirror proportional to the load current in normal operation, delivering
current proportional to the load according to known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can
be done using simple equations
Current provided by CurrentSense output: ISENSE = IOUT/K
Voltage on RSENSE : VSENSE = RSENSE . ISENSE = RSENSE . IOUT/K
Where :
•
VSENSE is voltage measurable on RSENSE resistor
DocID027585 Rev 3
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Application information
•
•
•
VND7050AJ12
ISENSE is current provided from CurrentSense pin in current output mode
IOUT is current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the CurrentSense pin
which is switched to a “current limited” voltage source, VSENSEH.
In any case, the current sourced by the CurrentSense in this condition is limited to ISENSEH.
The typical behavior in case of overload or hard short circuit is shown in Waveforms
section.
Figure 36: Analogue HSD – open-load detection in off-state
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VND7050AJ12
Application information
Figure 37: Open-load / short to VCC condition
Table 16: CurrentSense pin levels in off-state
Condition
Output
CurrentSense
SEn
Hi-Z
L
VSENSEH
H
Hi-Z
L
VOUT > VOL
Open-load
VOUT < VOL
4.5.2
Short to VCC
VOUT > VOL
Nominal
VOUT < VOL
0
H
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
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Application information
VND7050AJ12
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
Equation
RPU <
32/43
VPU - 4
IL(off2)min @ 4V
DocID027585 Rev 3
VND7050AJ12
Maximum demagnetization energy (VCC = 16 V)
Figure 38: Maximum turn off current versus inductance
Maximum turn off current versus inductance
100
10
1
Single Pulse
I (A)
5
Maximum demagnetization energy (VCC = 16 V)
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
0.1
0.1
1 L (mH)
10
100
1000
GAPG0912131502CF T
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of
every pulse must not exceed the temperature specified above for curves A and B.
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Package and PCB thermal data
VND7050AJ12
6
Package and PCB thermal data
6.1
PowerSSO-12 thermal data
Figure 39: PowerSSO-12 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 40: PowerSSO-12 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 17: PCB properties
Dimension
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal via separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on via
0.025 mm
Footprint dimension (top layer)
2.2 mm x 3.9 mm
Heatsink copper area dimension (bottom layer)
34/43
Value
DocID027585 Rev 3
Footprint, 2 cm2 or 8 cm2
VND7050AJ12
Package and PCB thermal data
Figure 41: Rthj-amb vs PCB copper area in open box free air condition (one channel on)
Figure 42: PowerSSO-12 thermal impedance junction ambient single pulse (one channel on)
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
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Package and PCB thermal data
VND7050AJ12
Figure 43: Thermal fitting model of a double-channel HSD in PowerSSO-12
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
Table 18: Thermal parameters
Area/island
36/43
(cm2)
Footprint
2
8
4L
R1 = R7 (°C/W)
1.8
R2 = R8 (°C/W)
3.2
R3 (°C/W)
8
8
8
6
R4 (°C/W)
14
6
6
4
R5 (°C/W)
30
20
10
3
R6 (°C/W)
26
20
18
7
C1 = C7 (W.s/°C)
0.00035
C2 = C8 (W.s/°C)
0.005
C3 (W.s/°C)
0.05
C4 (W.s/°C)
0.2
0.3
0.3
0.4
C5 (W.s/°C)
0.4
1
1
4
C6 (W.s/°C)
3
5
7
18
DocID027585 Rev 3
VND7050AJ12
7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
PowerSSO-12 package information
Figure 44: PowerSSO-12 package dimensions
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Package information
VND7050AJ12
Table 19: PowerSSO-12 mechanical data
Millimeters
Symbol
Min.
Typ.
A
1.250
1.700
A1
0.000
0.100
A2
1.100
1.600
B
0.230
0.410
C
0.190
0.250
D
4.800
5.000
E
3.800
4.000
e
0.800
H
5.800
6.200
h
0.250
0.500
L
0.400
1.270
k
0°
8°
X
2.200
2.800
Y
2.900
3.500
ddd
7.2
0.100
PowerSSO-12 packing information
Figure 45: PowerSSO-12 reel 13"
Table 20: Reel dimensions
38/43
Max.
Description
Value(1)
Base quantity
2500
Bulk quantity
2500
A (max)
330
B (min)
1.5
DocID027585 Rev 3
VND7050AJ12
Package information
Description
Value(1)
C (+0.5, -0.2)
13
D (min)
20.2
N
100
W1 (+2 /-0)
12.4
W2 (max)
18.4
Notes:
(1)All
dimensions are in mm.
Figure 46: PowerSSO-12 carrier tape
0.30 ±0.05
P2
P0
2.0 ±0.1
4.0 ±0.1
X
1.55 ±0.05
1.75 ±0.1
B0
W
F
1.6±0.1
R 0.5
Typical
K1
Y
Y
X
K0
P1
A0
REF 4.18
REF 0.6
SECTION X - X
REF 0.5
SECTION Y - Y
GAPG2204151242CFT
Table 21: PowerSSO-12 carrier tape dimensions
Description
Value(1)
A0
6.50 ± 0.1
B0
5.25 ± 0.1
K0
2.10 ± 0.1
K1
1.80 ± 0.1
F
5.50 ± 0.1
P1
8.00 ± 0.1
W
12.00 ± 0.3
Notes:
(1)All
dimensions are in mm.
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Package information
VND7050AJ12
Figure 47: PowerSSO-12 schematic drawing of leader and trailer tape
7.3
PowerSSO-12 marking information
Figure 48: PowerSSO-12 marking information
Marking area
1
2
3
4
5
6
7
8
Special function digit
&: Engineering sample
: Commercial sample
PowerSSO-12 TOP VIEW
(not in scale)
GAPG1203151332CFT
Engineering Samples: these samples can be clearly identified by a dedicated
special symbol in the marking of each unit. These samples are intended to be
used for electrical compatibility evaluation only; usage for any other purpose may
be agreed only upon written authorization by ST. ST is not liable for any customer
usage in production and/or in reliability qualification trials.
Commercial Samples: Fully qualified parts from ST standard production with no
usage restrictions
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8
Order codes
Order codes
Table 22: Device summary
Order codes
Package
Tape and reel
PowerSSO-12
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Revision history
9
VND7050AJ12
Revision history
Table 23: Document revision history
Date
Revision
09-Jun-2015
1
Changes
Initial release.
Table 5: "Electrical characteristics during cranking":
•
18-Jun-2015
2
Updated Table 7: "Switching"
Table 10: "CurrentSense":
•
14-Sep-2015
3
KOL, KLED, K0, K1, K2: updated values
Updated Table 1: "Pin functions"
Table 5: "Electrical characteristics during cranking":
•
42/43
TTSD: updated value
RON: updated test conditions
DocID027585 Rev 3
VND7050AJ12
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
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© 2015 STMicroelectronics – All rights reserved
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