0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
VND830ASP-E

VND830ASP-E

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    POWERSO-10_7.5X9.4MM-EP

  • 描述:

    IC PWR SSR HI SIDE N-CH PWRSO10

  • 数据手册
  • 价格&库存
VND830ASP-E 数据手册
VND830ASP-E Double channel high-side solid state relay Features Type RDS(on) IOUT VCC VND830ASP-E 60 mΩ 6 A(1) 36 V(1) 10 1. Per channel 1 PowerSO-10 ■ ECOPACK®: lead free and RoHS compliant ■ Automotive Grade: compliance with AEC guidelines Description ■ Very low standby current ■ CMOS compatible input ■ Proportional load current sense ■ Current sense disable ■ Thermal shutdown protection and diagnosis ■ Undervoltage shutdown The VND830ASP-E is a monolithic device made using STMicroelectronics™ VIPower™ M0-3 technology. It is intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). ■ Overvoltage clamp ■ Load current limitation This device has two channels in high-side configuration; each channel has an analog sense output on which the sensing current is proportional (according to a known ratio) to the corresponding load current. Built-in thermal shutdown and outputs current limitation protect the chip from overtemperature and short circuit. Device turns-off in case of ground pin disconnections. Table 1. Device summary Order codes Package Power-SO-10™ September 2013 Tube Tape and reel VND830ASP-E VND830ASPTR-E Doc ID 17605 Rev 2 1/27 www.st.com 1 Contents VND830ASP-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 4 6 2/27 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 17 3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 18 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 PowerSO-10 maximum demagnetization energy (VCC = 13.5 V) . . . . . . . 19 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17 PowerSO-10 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 17605 Rev 2 VND830ASP-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching (VCC = 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic input (channel 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC - output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Truth table (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements on VCC pin (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical transient requirements on VCC pin (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical transient requirements on VCC pin (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 17605 Rev 2 3/27 List of figures VND830ASP-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. 4/27 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Switching characteristics (resistive load RL= 6.5 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Maximum turn- off current versus load inductance(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PowerSO-10 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20 PowerSO-10 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . 21 Thermal fitting model of a double channel HSD in PowerSO-10 . . . . . . . . . . . . . . . . . . . . 21 PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PowerSO-10 suggested pad layout and tube shipment (no suffix). . . . . . . . . . . . . . . . . . . 25 Tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Doc ID 17605 Rev 2 VND830ASP-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram VCC OVERVOLTAGE VCC CLAMP UNDERVOLTAGE PwCLAMP 1 DRIVER 1 Vdslim1 LOGIC IOUT1 INPUT 2 Ot1 CURRENT SENSE 1 OUTPUT 2 ILIM2 OVERTEMP. 1 OVERTEMP. 2 Ot1 K PwCLAMP 2 DRIVER 2 GND Figure 2. OUTPUT 1 ILIM1 INPUT 1 Vdslim2 IOUT2 Ot2 Ot2 CURRENT SENSE 2 K Configuration diagram (top view) GROUND INPUT 2 INPUT 1 C.SENSE1 C.SENSE2 6 7 8 9 5 4 3 10 1 2 OUTPUT 2 OUTPUT 2 N.C. OUTPUT 1 OUTPUT 1 11 VCC PowerSO-10 Doc ID 17605 Rev 2 5/27 Electrical specifications 2 VND830ASP-E Electrical specifications Figure 3. Current and voltage conventions IS VCC VCC IOUT1 IIN1 INPUT1 VIN1 OUTPUT1 CURRENT SENSE 1 IIN2 INPUT2 VIN2 VOUT1 ISENSE1 OUTPUT2 CURRENT SENSE 2 GROUND IOUT2 VSENSE1 VOUT2 ISENSE2 VSENSE2 IGND 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 2 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality document. Table 2. Absolute maximum ratings Symbol Value Unit 41 V VCC DC supply voltage -VCC Reverse supply voltage -0.3 V - IGND DC reverse ground pin current -200 mA Internally limited A -6 A +/- 10 mA -3 +15 V V IOUT Output current IR Reverse output current IIN Input current VCSENSE 6/27 Parameter Current sense maximum voltage Doc ID 17605 Rev 2 VND830ASP-E Electrical specifications Table 2. Symbol Parameter Value Unit VESD Electrostatic discharge (Human Body Model: R = 1.5 Ω; C = 100 pF) – INPUT – CURRENT SENSE – OUTPUT – VCC 4000 2000 5000 5000 V V V V EMAX Maximum switching energy (L = 1.8 mH; RL = 0 Ω; Vbat= 13.5 V; Tjstart = 150 °C; IL = 9 A) 100 mJ Ptot Power dissipation at Tc = 25 °C 74 W Tj Junction operating temperature Internally limited °C Tc Case operating temperature -40 to 150 °C Storage temperature -55 to 150 °C TSTG 2.2 Absolute maximum ratings (continued) Thermal data Table 3. Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb 1. Thermal data Thermal resistance junction-ambient Value Unit 1.3 °C/W 51.2(1) °C/W When mounted on a standard single sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick). Horizontal mounting and no artificial air flow. Doc ID 17605 Rev 2 7/27 Electrical specifications 2.3 VND830ASP-E Electrical characteristics Values specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless otherwise specified. (Per each channel). Table 4. Power Symbol Parameter VCC Min. Typ. Max. Unit Operating supply voltage 5.5 13 36 V VUSD Undervoltage shutdown 3 4 5.5 V VOV Overvoltage shutdown 36 RON On-state resistance Vclamp IS Test conditions Clamp voltage IOUT = 2 A; Tj = 25 °C 60 mΩ IOUT = 2 A; Tj = 150 °C 120 mΩ 48 55 V Off-state; VCC = 13 V; VIN = VOUT = 0 V 12 40 µA Off-state; VCC=13V; VIN = VOUT = 0 V; Tj = 25 °C 12 25 µA 7 mA 0 50 µA -75 0 µA ICC = 20 Supply current V mA(1) 41 On-state; VIN = 5 V; VCC = 13 V; IOUT = 0 A; RSENSE = 3.9 kΩ IL(off1) Off-state output current VIN = VOUT = 0 V; VCC = 36 V; Tj = 125 °C IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V IL(off3) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 125 °C 5 µA IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 25 °C 3 µA 1. Vclamp and VOV are correlated. Typical difference is 5 V. Table 5. Symbol 8/27 Switching (VCC = 13 V) Parameter Test conditions Min Typ Max Unit td(on) Turn-on delay time RL = 6.5 Ω from VIN rising edge to VOUT = 1.3 V - 30 - µs td(off) Turn-on delay time RL = 6.5 Ω from VIN falling edge to VOUT = 11.7 V - 30 - µs (dVOUT/dt)on Turn-on voltage slope RL = 6.5 Ω from VOUT = 1.3 V to VOUT = 10.4 V - See Figure 15 - V/µs (dVOUT/dt)off Turn-off voltage slope RL = 6.5 Ω from VOUT = 11.7 V to VOUT = 1.3 V - See Figure 16 - V/µs Doc ID 17605 Rev 2 VND830ASP-E Electrical specifications Table 6. Symbol Logic input (channel 1, 2) Parameter Test conditions VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL Table 7. Forward on voltage TTSD TR 1.25 V µA 3.25 V 10 0.5 Test conditions µA V 6 6.8 8 -0.7 V V Min Typ Max Unit - - 0.6 V -IOUT = 2 A; Tj = 150 °C Protection Parameter Test conditions DC short circuit current VCC = 13 V Min. Typ. Max. Unit 6 9 15 A 15 A 200 °C 5.5 V < VCC 8 V, IOUT1,2 = 2.5 A; RSENSE = 10 kΩ 4 V dK1/K1 K2 dK2/K2 K3 dK3/K3 ISENSE VSENSE VSENSEH Analog sense leakage current Max analog sense output voltage Sense voltage in VCC = 13 V; RSENSE = 3.9 kΩ overtemperature condition Analog sense output VCC = 13 V; Tj > TTSD; RVSENSEH impedance in All channels open overtemperature condition tDSENSE Current sense delay response to 90% ISENSE (2) 1. 9 V ≤ VCC ≤ 16 V (see Figure 4) 2. Current sense signal delay after positive input slope. Sense pin doesn’t have to be left floating. 10/27 Doc ID 17605 Rev 2 1280 1300 +10 1500 1500 -6 1280 1340 1800 1780 +6 1500 1500 % % 1680 1600 5.5 V 400 Ω 500 µs VND830ASP-E Electrical specifications Figure 4. Switching characteristics (resistive load RL= 6.5 Ω) VOUT 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% tr tf t ISENSE 90% INPUT t tDSENSE td(on) td(off) t Figure 5. IOUT/ISENSE versus IOUT Iout/Isense 2250 2000 A 1750 B 1500 C D 1250 E 1000 750 500 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Iout [A] A: Max, Tj = -40 °C to 150 °C B: Max, Tj = 25 °C to 150 °C C: Typical, Tj = -40 °C to 150 °C Doc ID 17605 Rev 2 D: Min, Tj = 25 °C to 150 °C E: Min, Tj = -40 °C to 150 °C 11/27 Electrical specifications Table 10. Truth table (per each channel) Conditions 12/27 VND830ASP-E Input Output Sense Normal operation L H L H 0 Nominal Overtemperature L H L L 0 VSENSEH Undervoltage L H L L 0 0 Overvoltage L H L L 0 0 Short circuit to GND L H H L L L Short circuit to VCC L H H H 0 < Nominal Negative output voltage clamp L L 0 Doc ID 17605 Rev 2 (TjTTSD) 0 0 VSENSEH VND830ASP-E Electrical specifications Table 11. Electrical transient requirements on VCC pin (part 1) Test levels ISO T/R 7637/1 test pulse I II III IV Delays and impedance 1 -25 V -50 V -75 V -100 V 2 ms, 10 Ω 2 +25 V +50 V +75 V +100 V 0.2 ms, 10 Ω 3a -25 V -50 V -100 V -150 V 0.1 µs, 50 Ω 3b +25 V +50 V +75 V +100 V 0.1 µs, 50 Ω 4 -4 V -5 V -6 V -7 V 100 ms, 0.01 Ω 5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2 Ω Table 12. Electrical transient requirements on VCC pin (part 2) Test levels results ISO T/R 7637/1 Test pulse I II III IV 1 C C C C 2 C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E Table 13. Electrical transient requirements on VCC pin (part 3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Doc ID 17605 Rev 2 13/27 Electrical specifications Figure 6. VND830ASP-E Waveforms NORMAL OPERATION INPUTn LOAD CURRENTn SENSEn UNDERVOLTAGE VCC VUSDhyst VUSD INPUTn LOAD CURRENTn SENSEn OVERVOLTAGE VOV VCC INPUTn LOAD CURRENTn SENSEn VCC < VOV VCC > VOV SHORT TO GROUND INPUTn LOAD CURRENTn LOAD VOLTAGEn SENSEn SHORT TO VCC INPUTn LOAD VOLTAGEn LOAD CURRENTn SENSEn Tj TTSD TR
VND830ASP-E 价格&库存

很抱歉,暂时无法提供与“VND830ASP-E”相匹配的价格&库存,您可以联系我们找货

免费人工找货