VND830MSP
Double channel high-side driver
Features
Type
RDS(on)
IOUT
VCC
VND830MSP
60 mΩ(1)
6 A(1)
36 V
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10
1. Per each channel.
1
CMOS compatible inputs
■
Open drain status outputs
■
On-state open-load detection
■
Off-state open-load detection
■
Shorted load protection
■
Undervoltage and overvoltage shutdown
■
Loss of ground protection
■
Very low standby current
■
Reverse battery protection
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Description
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PowerSO-10
■
The VND830MSP is a monolithic device designed
in| STMicroelectronics™ VIPower™ M0-3
Technology. The VND830MSP is intended for
driving any type of multiple load with one side
connected to ground.
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The Active VCC pin voltage clamp protects the
device against low energy spikes (see ISO7637
transient compatibility table). Active current
limitation combined with thermal shutdown and
automatic restart protects the device against
overload.
The current limitation threshold is aimed at
detecting the 21 W / 12 V standard bulb as an
overload fault.
The device detects the open-load condition in
both the on and off-state. In the off-state the
device detects if the output is shorted to VCC. The
device automatically turns off in the case where
the ground pin becomes disconnected.
Device summary
Order codes
Package
PowerSO-10
September 2013
Tube
Tape and reel
VND830MSP
VND830MSP13TR
Doc ID 7379 Rev 5
1/27
www.st.com
1
Contents
VND830MSP
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
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3.1.1
Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16
3.1.2
Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 17
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3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3
MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5
Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 19
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Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
5
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PowerSO-10 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
6
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5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3
PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 7379 Rev 5
VND830MSP
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Doc ID 7379 Rev 5
3/27
List of figures
VND830MSP
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PowerSO-10 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20
Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Thermal fitting model of a double channel HSD in PowerSO-10 . . . . . . . . . . . . . . . . . . . . 21
PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSO-10 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PowerSO-10 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PowerSO-10 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Doc ID 7379 Rev 5
VND830MSP
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
Vcc
Vcc
CLAMP
OVERVOLTAGE
UNDERVOLTAGE
CLAMP 1
GND
OUTPUT1
INPUT1
DRIVER 1
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CLAMP 2
STATUS1
CURRENT LIMITER 1
DRIVER 2
LOGIC
OUTPUT2
OVERTEMP. 1
OPEN LOAD ON 1
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CURRENT LIMITER 2
INPUT2
OPEN LOAD OFF 1
OPEN LOAD ON 2
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STATUS2
OPEN LOAD OFF 2
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OVERTEMP. 2
Figure 2.
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GROUND
INPUT 1
STATUS 1
STATUS 2
INPUT 2
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OUTPUT 1
OUTPUT 1
N.C.
OUTPUT 2
OUTPUT 2
5
4
3
6
7
8
9
10
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Configuration diagram (top view)
2
1
11
VCC
Table 2.
Suggested connections for unused and not connected pins
Connection / pin
Status
N.C.
Output
Input
Floating
X
X
X
X
To ground
X
Doc ID 7379 Rev 5
Through 10 KΩ
resistor
5/27
Electrical specifications
VND830MSP
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
Table 3.
Absolute maximum ratings
Symbol
Parameter
VCC
DC supply voltage
- VCC
Reverse DC supply voltage
- IGND
DC reverse ground pin current
IOUT
- IOUT
IIN
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Pr
Internally limited
A
-6
A
+/-10
mA
+/-10
mA
4000
4000
5000
5000
V
V
V
V
Maximum switching energy
(L = 1.8 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C;
IL = 9 A)
100
mJ
Power dissipation (per island) at Tlead = 25 °C
73.5
W
Internally limited
°C
DC output current
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Reverse DC output current
DC input current
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VESD
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Tj
Junction operating temperature
Tc
Case operating temperature
-40 to 150
Storage temperature
-55 to 150
Tstg
V
mA
P
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V
-200
Electrostatic discharge (human body model: R = 1.5 KΩ;
C = 100 pF)
– INPUT
– STATUS
– OUTPUT
– VCC
Ptot
41
-0.3
DC Status current
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Unit
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ISTAT
EMAX
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Value
Doc ID 7379 Rev 5
°C
VND830MSP
2.2
Electrical specifications
Thermal data
Table 4.
Thermal data (per island)
Symbol
Parameter
Rthj-lead
Thermal resistance junction-lead
Rthj-amb
Thermal resistance junction-ambient
Value
Unit
1.7
°C/W
51.7(1)
37(2)
°C/W
2
1. When mounted on a standard single-sided FR-4 board with 0.5 cm of Cu (at least 35 µm thick) connected
to all VCC pins. Horizontal mounting and no artificial air flow.
2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 µm thick) connected to
all VCC pins. Horizontal mounting and no artificial air flow.
2.3
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Electrical characteristics
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Values specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless
otherwise stated.
Figure 3.
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IIN1
INPUT 1
ISTAT1
VIN1
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VSTAT1
IIN2
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INPUT 2
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Pr
VSTAT2
VCC
IOUT1
IOUT2
OUTPUT 2
STATUS 2
VF1 (*)
VCC
VOUT1
VIN2 ISTAT2
od
IS
OUTPUT 1
STATUS 1
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Current and voltage conventions
VOUT2
GND
IGND
Note:
VFn = VCCn - VOUTn during reverse battery condition.
Doc ID 7379 Rev 5
7/27
Electrical specifications
Table 5.
VND830MSP
Power output
Symbol
Parameter
VCC
Operating supply
voltage
VUSD
Test conditions
Min.
5.5
13
36
V
Undervoltage shutdown
3
4
5.5
V
VOV
Overvoltage shutdown
36
RON
On-state resistance
IS
Supply current
Off-state; VCC = 13 V;
VIN = VOUT = 0 V
12
Off-state; VCC = 13 V;
VIN = VOUT = 0 V; Tj = 25 °C
12
µA
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µA
7
mA
0
50
µA
-75
0
µA
5
IL(off2)
Off-state output current VIN = 0 V; VOUT = 3.5 V
IL(off3)
Off-state output current
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C
5
µA
IL(off4)
Off-state output current
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25 °C
3
µA
TTSD
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Parameter
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Test conditions
Shutdown temperature
P
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Min.
Typ.
Max.
Unit
150
175
200
°C
TR
Reset temperature
135
Thyst
Thermal hysteresis
7
tSDL
Status delay in overload
conditions
Ilim
Current limitation
let
Vdemag
8/27
40
Off-state output current VIN = VOUT = 0 V
Symbol
Note:
mΩ
mΩ
25
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Pr
60
120
IL(off1)
Table 6.
O
V
IOUT = 0.5 A; Tj = 25 °C
IOUT = 0.5 A; VCC > 8 V
On-state; VCC = 13 V; VIN = 5 V;
IOUT = 0 A
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Typ. Max. Unit
15
Tj > TTSD
VCC = 13 V
5.5 V < VCC < 36 V
Turn-off output clamp voltage
°C
IOUT = 2 A; L = 6 mH
6
9
°C
20
µs
15
A
15
A
VCC - VCC - VCC 41
48
55
V
To ensure long term reliability under heavy overload or short circuit conditions, protection
and related diagnostic signals must be used together with a proper software strategy. If the
device is subjected to abnormal conditions, this software must limit the duration and number
of activation cycles.
Doc ID 7379 Rev 5
VND830MSP
Electrical specifications
Table 7.
VCC - output diode
Symbol
Parameter
VF
Forward on voltage
Table 8.
Test conditions
Typ.
Max.
Unit
—
—
0.6
V
- IOUT = 1.3 A; Tj = 150 °C
Switching (VCC = 13 V; Tj = 25 °C)
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
td(on)
Turn-on delay time
RL = 6.5 Ω from VIN rising
edge to VOUT = 1.3 V
(see Figure 5)
5
30
td(off)
Turn-off delay time
RL = 6.5 Ω from VIN falling
edge to VOUT = 11.7 V
(see Figure 5)
10
30
0.15
See
Figure 10
0.1
See
Figure 12
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Min.
Typ.
VIN = 1.25 V
1
µA
3.25
V
RL = 6.5 Ω from VOUT = 1.3 V
dVOUT/dt(on) Turn-on voltage slope to VOUT = 10.4 V
(see Figure 5)
RL = 6.5 Ω from VOUT = 11.7 V
dVOUT/dt(off) Turn-off voltage slope to VOUT = 1.3 V
(see Figure 5)
Table 9.
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Logic inputs
Symbol
Parameter
)-
VIL
Input low level
IIL
Low level input current
VIH
Input high level
IIH
High level input current
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VICL
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VI(hyst)
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Min.
Table 10.
Symbol
Test conditions
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70
µs
1.5
V/µs
0.75
V/µs
Max.
Unit
1.25
V
10
0.5
IIN = 1 mA
Input clamp voltage
µs
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VIN = 3.25 V
Input hysteresis voltage
60
µA
V
6
6.8
IIN = -1 mA
8
-0.7
V
V
Status pin
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VSTAT
Status low output voltage
ISTAT = 1.6 mA
0.5
V
ILSTAT
Status leakage current
Normal operation; VSTAT = 5 V
10
µA
CSTAT
Status pin Input capacitance Normal operation; VSTAT = 5 V
100
pF
8
V
VSCL
Status clamp voltage
ISTAT = 1 mA
ISTAT = - 1 mA
Doc ID 7379 Rev 5
6
6.8
-0.7
V
9/27
Electrical specifications
Table 11.
VND830MSP
Open-load detection
Symbol
Parameter
IOL
Open-load on-state detection threshold
VIN = 5 V
Open-load on-state detection delay
IOUT = 0 A
VOL
Open-load off-state voltage detection
threshold
VIN = 0 V
tDOL(off)
Open-load detection delay at turn-off
tDOL(on)
Figure 4.
Test conditions
0.6
1.5
0.9
2.5
Unit
1.2
A
200
µs
3.5
V
1000
µs
Tj > TTSD
u
d
o
VINn
VSTATn
r
P
e
VSTATn
tDOL(off)
let
o
s
b
tDOL(on)
O
)
Switching time waveforms
s
(
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Doc ID 7379 Rev 5
)
s
(
ct
OVER TEMP STATUS TIMING
VINn
10/27
Typ. Max.
Status timings
OPEN LOAD STATUS TIMING (with external pull-up)
IOUT < IOL
VOUT > VOL
Figure 5.
Min.
tSDL
tSDL
VND830MSP
Electrical specifications
Table 12.
Truth table
Conditions
Input
Output
Status
Normal operation
L
H
L
H
H
H
Current limitation
L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
Overtemperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Overvoltage
L
H
L
L
Output voltage > VOL
L
H
H
H
Output current < IOL
L
H
L
H
Table 13.
Test pulse
I
1
- 25V(1)
)
(s
O
ct
du
+ 25V
ro
3a
o
s
b
II
(1)
2
P
e
let
t
e
l
o
s
b
O
L
H
H
L
Test level
7637/1
3b
u
d
o
r
P
e
Electrical transient requirements
ISO T/R
)
s
(
ct
H
H
-
25V(1)
+
25V(1)
III
IV
Delays and impedance
- 50V(1)
- 75V(1)
- 100V(1)
2ms, 10Ω
+
50V(1)
75V(1)
+
100V(1)
0.2ms, 10Ω
-
50V(1)
-
150V(1)
0.1µs, 50Ω
+
50V(1)
+
100V(1)
0.1µs, 50Ω
+
-
100V(1)
+
75V(1)
4
- 4V(1)
- 5V(1)
- 6V(1)
- 7V(1)
5
26.5V(1)
46.5V(2)
66.5V(2)
86.5V(2)
+
+
+
+
100ms, 0.01Ω
400ms, 2Ω
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
proper operation without replacing the device.
Doc ID 7379 Rev 5
11/27
Electrical specifications
Figure 6.
VND830MSP
Waveforms
NORMAL OPERATION
INPUTn
LOAD VOLTAGEn
STATUSn
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
)
s
(
ct
INPUTn
LOAD VOLTAGEn
STATUS
r
P
e
OVERVOLTAGE
VCC VOV
t
e
l
o
VCC
INPUTn
LOAD VOLTAGEn
STATUSn
)
(s
t
c
u
INPUTn
od
LOAD VOLTAGEn
r
P
e
STATUSn
t
e
l
o
bs
O
s
b
O
OPEN LOAD with external pull-up
VOUT > VOL
VOL
OPEN LOAD without external pull-up
INPUTn
LOAD VOLTAGEn
STATUSn
Tj
TTSD
TR
OVERTEMPERATURE
INPUTn
LOAD CURRENTn
STATUSn
12/27
u
d
o
undefined
Doc ID 7379 Rev 5
VND830MSP
Electrical specifications
2.4
Electrical characteristics curves
Figure 7.
Off-state output current
Figure 8.
High level input current
Iih (uA)
IL(off1) (uA)
2.5
5
2.25
4.5
Off state
Vcc=36V
Vin=Vout=0V
2
1.75
Vin=3.25V
4
3.5
1.5
3
1.25
2.5
1
2
0.75
1.5
0.5
1
0.25
0.5
)
s
(
ct
u
d
o
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
Input clamp voltage
r
P
e
7.8
s
b
O
700
Iin=1mA
7.6
600
)-
7.4
7.2
s
(
t
c
7
6.8
u
d
o
6.2
6
ete
-50
ol
Figure 11.
s
b
O
-25
0
Pr
25
50
100
125
150
175
150
175
150
175
t
e
l
o
dVout/dt(on) (V/ms)
800
8
6.4
75
Figure 10. Turn-on voltage slope
Vicl (V)
6.6
50
Tc (°C)
Tc (°C)
Figure 9.
25
Vcc=13V
Rl=6.5Ohm
500
400
300
200
100
0
75
100
125
150
-50
175
-25
0
25
50
75
100
125
Tc (ºC)
Tc (°C)
Overvoltage shutdown
Figure 12. Turn-off voltage slope
Vov (V)
dVout/dt(off) (V/ms)
50
600
48
550
Vcc=13V
Rl=6.5Ohm
46
500
44
450
42
40
400
38
350
36
300
34
250
32
200
30
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (ºC)
Tc (°C)
Doc ID 7379 Rev 5
13/27
Electrical specifications
VND830MSP
Figure 13. ILIM vs Tcase
Figure 14. On-state resistance vs VCC
Ilim (A)
Ron (mOhm)
20
120
Tc=150°C
110
18
Vcc=13V
100
16
90
14
80
12
70
10
60
8
50
Tc=25°C
40
6
Tc= - 40°C
30
4
10
0
0
-50
-25
0
25
50
75
100
125
150
Iout=5A
175
5
10
15
20
Tc (°C)
30
u
d
o
35
40
Figure 16. Input hysteresis voltage
Vih (V)
Vhyst (V)
3.6
1.5
1.3
3.2
s
b
O
1.2
3
r
P
e
t
e
l
o
1.4
3.4
1.1
)-
2.8
s
(
t
c
2.6
2.4
u
d
o
2.2
2
-50
-25
0
Pr
25
50
75
100
1
0.9
0.8
0.7
0.6
0.5
125
150
175
-50
-25
0
25
Tc (°C)
e
t
e
l
50
75
100
125
150
175
Tc (°C)
Figure 17. On-state resistance vs Tcase
so
Figure 18. Input low level
Ron (mOhm)
Vil (V)
160
2.6
2.4
140
Iout=2A
Vcc=8V; 13V & 36V
120
2.2
100
2
80
1.8
60
1.6
40
1.4
20
1.2
1
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
Tc (°C)
14/27
25
Vcc (V)
Figure 15. Input high level
b
O
)
s
(
ct
20
2
Doc ID 7379 Rev 5
100
125
150
175
VND830MSP
Electrical specifications
Figure 19. Status leakage current
Figure 20. Status low output voltage
Ilstat (uA)
Vstat (V)
0.05
0.8
0.7
Istat=1.6mA
0.04
0.6
Vstat=5V
0.5
0.03
0.4
0.02
0.3
0.2
0.01
)
s
(
ct
0.1
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
150
175
u
d
o
Tc (°C)
Tc (°C)
Figure 21. Status clamp voltage
125
Figure 22. Open-load on-state detection
threshold
Vscl (V)
r
P
e
Iol (mA)
8
1250
7.8
t
e
l
o
1200
Istat=1mA
7.6
1150
7.4
s
b
O
1100
7.2
Vcc=13V
Vin=5V
1050
)-
7
6.8
s
(
t
c
6.6
6.4
du
6.2
6
-50
-25
0
o
r
P
25
50
75
100
1000
950
900
850
800
750
125
150
175
Tc (°C)
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Figure 23. Open-load off-state voltage
detection threshold
e
t
e
ol
Vol (V)
O
bs
5
4.5
Vin=0V
4
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Doc ID 7379 Rev 5
15/27
Application information
3
VND830MSP
Application information
Figure 24. Application schematic
+5V +5V
+5V
VCC
Rprot
STATUS1
Dld
μC
Rprot
)
s
(
ct
INPUT1
OUTPUT1
Rprot
STATUS2
Rprot
INPUT2
u
d
o
r
P
e
t
e
l
o
GND
)
(s
s
b
O
RGND
VGND
OUTPUT2
DGND
t
c
u
d
o
r
3.1
GND protection network against reverse battery
P
e
This section provides two solutions for implementing a ground protection network against
reverse battery.
bs
t
e
l
o
3.1.1
O
Solution 1: a resistor in the ground line (RGND only)
This can be used with any type of load.
The following show how to dimension the RGND resistor:
1.
RGND ≤ 600 mV / 2 (IS(on)max)
2.
RGND ≥ ( -VCC) / ( -IGND)
where - IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC < 0 during reverse battery situations) is:
PD = ( -VCC)2/ RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
16/27
Doc ID 7379 Rev 5
VND830MSP
Application information
Please note that, if the microprocessor ground is not shared by the device ground, then the
RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift varies depending on how many devices are ON in the case of several highside drivers sharing the same RGND .
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.
3.1.2
Solution 2: a diode (DGND) in the ground line
A resistor (RGND = 1 kΩ) should be inserted in parallel to DGND if the device is driving an
inductive load. This small signal diode can be safely shared amongst several different HSD.
Also in this case, the presence of the ground network produces a shift (≈600 mV) in the
input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift not varies if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the Absolute Maximum
Rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.
)
s
(
ct
u
d
o
3.2
r
P
e
t
e
l
o
Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCC maximum DC rating. The same applies if the device is subject to transients on the VCC
line that are greater than those shown in the ISO T/R 7637/1 table.
)
(s
3.3
s
b
O
MCU I/O protection
t
c
u
If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent
the microcontroller I/O pins from latching up.
d
o
r
P
e
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:
s
b
O
t
e
l
o
- VCCpeak / Ilatchup ≤ Rprot ≤ (VOHμC - VIH - VGND) / IIHmax
Example
For the following conditions:
VCCpeak = -100 V
Ilatchup ≥ 20 mA
VOHμC ≥ 4.5 V
5 kΩ ≤ Rprot ≤ 65 kΩ.
Recommended values are:
Rprot = 10 kΩ
Doc ID 7379 Rev 5
17/27
Application information
3.4
VND830MSP
Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5 V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1.
no false open-load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT = (VPU / (RL + RPU))RL < VOlmin.
2.
no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2).
)
s
(
ct
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
u
d
o
Figure 25. Open-load detection in off-state
r
P
e
V batt.
t
e
l
o
VCC
DRIVER
+
LOGIC
INPUT
)-
s
(
t
c
STATUS
du
e
t
e
ol
o
r
P
s
b
O
RPU
IL(off2)
OUT
+
R
VOL
GROUND
s
b
O
18/27
VPU
Doc ID 7379 Rev 5
RL
VND830MSP
3.5
Application information
Maximum demagnetization energy (VCC = 13.5 V)
Figure 26. Maximum turn-off current versus load inductance
I LM AX (A)
100
)
s
(
ct
10
u
d
o
A
B
r
P
e
C
t
e
l
o
1
0,1
1
s
b
O
10
100
L(mH)
)
(s
t
c
u
A = single pulse at TJstart = 150 °C
B= repetitive pulse at TJstart = 100 °C
d
o
r
C= repetitive pulse at TJstart = 125 °C
P
e
t
e
l
o
bs
VIN, IL
Demagnetization
Demagnetization
Demagnetization
O
t
Note:
Values are generated with RL = 0Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature
specified above for curves B and C.
Doc ID 7379 Rev 5
19/27
Package and PCB thermal data
VND830MSP
4
Package and PCB thermal data
4.1
PowerSO-10 thermal data
Figure 27. PowerSO-10 PC board
)
s
(
ct
u
d
o
r
P
e
Note:
Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness =
35 µm, Copper areas: from minimum pad lay-out to 8 cm2).
t
e
l
o
Figure 28. Rthj-amb vs PCB copper area in open box free air condition
)
(s
RTHj_amb (°C/W)
55
s
b
O
ct
u
d
o
50
Tj-Tamb=50°C
r
P
e
45
t
e
l
o
s
b
O
40
35
30
0
2
4
6
PCB Cu heatsink area (cm^2)
20/27
Doc ID 7379 Rev 5
8
10
VND830MSP
Package and PCB thermal data
Figure 29. Thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
100
0.5 cm2
6 cm2
10
)
s
(
ct
u
d
o
1
r
P
e
t
e
l
o
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
)
(s
10
s
b
O
100
1000
Equation 1: pulse calculation formula
t
c
u
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where
d
o
r
δ = tp ⁄ T
P
e
Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10
s
b
O
t
e
l
o
Tj_1
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
Pd1
Tj_2
C1
C2
R1
R2
Pd2
T_amb
Doc ID 7379 Rev 5
21/27
Package and PCB thermal data
Table 14.
VND830MSP
Thermal parameters
Area / island (cm2)
Footprint
R1 (°C/W)
0.15
R2 (°C/W)
0.8
R3 (°C/W)
0.7
R4 (°C/W)
0.8
R5 (°C/W)
12
R6 (°C/W)
37
C1 (W.s/°C)
0.0006
C2 (W.s/°C)
2.1E-03
C3 (W.s/°C)
0.013
C4 (W.s/°C)
0.3
C5 (W.s/°C)
0.75
22
3
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Doc ID 7379 Rev 5
)
s
(
ct
u
d
o
r
P
e
C6 (W.s/°C)
22/27
6
5
VND830MSP
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSO-10 mechanical data
)
s
(
ct
Figure 31. PowerSO-10 package dimensions
u
d
o
B
r
P
e
0.10 A B
10
H
E
1
)
(s
e
t
c
u
0.25
d
o
r
h
O
E
B
s
b
O
DETAIL "A"
A
E4
SEATING
PLANE
A
C
D
= D1 =
=
=
SEATING
PLANE
P
e
let
o
s
b
t
e
l
o
E2
F
A1
A1
L
DETAIL "A"
α
Doc ID 7379 Rev 5
23/27
Package and packing information
Table 15.
VND830MSP
PowerSO-10 mechanical data
mm
Dim.
Min.
3.35
3.65
A(1)
3.4
3.6
A1
0
0.10
B
0.40
0.60
B(1)
0.37
0.53
C
0.35
C(1)
0.23
D
9.40
D1
7.40
E
9.30
E2
7.20
E2(1)
7.30
E4
5.90
(s)
ct
du
F
u
d
o
ol
bs
9.60
7.60
9.50
7.60
7.50
-O
6.10
6.30
1.27
1.35
1.20
1.40
H
13.80
14.40
H(1)
13.85
14.35
o
r
P
h
0.50
L
1.20
1.80
L(1)
0.80
1.10
α
0°
8°
α(1)
2°
8°
1. Muar only POA P013P.
24/27
ete
Pr
0.32
1.25
F(1)
b
O
)
s
(
ct
0.55
5.90
e
so
Max.
A
E4(1)
e
t
e
l
Typ.
Doc ID 7379 Rev 5
VND830MSP
5.3
Package and packing information
PowerSO-10 packing information
Figure 32. PowerSO-10 suggested Figure 33. PowerSO-10 tube shipment
pad layout
(no suffix)
14.6 - 14.9
CASABLANCA
B
10.8 - 11
MUAR
C
6.30
C
A
A
0.67 - 0.73
10
9
8
1
9.5
2
3
7
4
5
B
0.54 - 0.6
All dimensions are in mm.
1.27
Casablanca
Muar
6
)
s
(
ct
Base Q.ty Bulk Q.ty Tube length (± 0.5) A
B C (± 0.1)
50
1000
532
10.4 16.4
0.8
50
1000
532
4.9 17.2
0.8
r
P
e
Figure 34. PowerSO-10 tape and reel shipment (suffix “TR”)
let
o
s
b
u
d
o
Reel dimensions
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
O
)
s
(
t
c
600
600
330
1.5
13
20.2
24.4
60
30.4
u
d
o
r
P
e
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
s
b
O
t
e
l
o
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
All dimensions are in mm.
24
4
24
1.5
1.5
11.5
6.5
2
End
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
Doc ID 7379 Rev 5
25/27
Revision history
6
VND830MSP
Revision history
Table 16.
Document revision history
Date
Revision
09-Sep-2004
1
Initial release.
2
Current and voltage convention update (page 2).
Configuration diagram (top view) & suggested connections for unused
and n.c. pins insertion (page 2).
4 cm2 Cu condition insertion in thermal data table (page 3).
VCC - output diode section update (page 4).
Protections note insertion (page 4).
Revision history table insertion (page 18).
Disclaimers update (page 19).
05-Dec-2008
3
Document reformatted and restructured.
Added contents, list of tables and figures.
Added ECOPACK® packages information.
08-Oct-2010
4
Updated Figure 5: Switching time waveforms
20-Sep-2013
5
Updated Disclaimer.
03-Mar-2008
Changes
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