VND830PEP-E

VND830PEP-E Double channel high side driver Features Type RDS(on) IOUT VCC VND830PEP-E 60mΩ(1) 6A(1) 36V ) s ( ct 1. Per each channel. u d o PowerSSO-24 ■ CMOS compatible inputs ■ Open drain status outputs ■ On-state open load detection ■ Off-state open load detection ■ Shorted load protection ■ Undervoltage and overvoltage shutdown ■ Protection against loss of ground ■ Very low standby current ■ Reverse battery protection (see Application schematic on page 16) ■ In compliance with the 2002/95/EC european directive r P e Description P e t e l o t e l o ) (s t c u d o r The VND830PEP-E is a monolithic device designed in STMicroelectronics VIPower™ M0-3 Technology, intended for driving any kind of load with one side connected to ground. s b O Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both in on and off-state. Output shorted to VCC is detected in the off-state. Device automatically turns off in case of ground pin disconnection. s b O Table 1. Device summary Order codes Package PowerSSO-24 September 2013 Tube Tape and reel VND830PEP-E VND830PEPTR-E Doc ID 10826 Rev 6 1/25 www.st.com 1 Contents VND830PEP-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ) s ( ct u d o Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 4 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16 r P e 3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16 3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 17 t e l o 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ) (s s b O Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 5 t c u PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 d o r Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 P e 5.1 t e l o 5.2 s b O 6 2/25 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Doc ID 10826 Rev 6 VND830PEP-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Switching (VCC = 13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical transient requirements on VCC pin (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical transient requirements on VCC pin (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical transient requirements on VCC pin (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 10826 Rev 6 3/25 List of figures VND830PEP-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Open-load status timing (with external pull-up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Over temperature status timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Rthj-amb vs PCB copper area in open box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PowerSSO-24 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 20 Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 20 PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 4/25 Doc ID 10826 Rev 6 VND830PEP-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram ) s ( ct u d o r P e t e l o Figure 2. ) (s s b O Configuration diagram (top view) ct VCC GND NC INPUT2 NC INPUT1 NC C.SENSE1 NC C.SENSE2 NC VCC u d o r P e t e l o s b O OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 TAB = VCC Table 2. Suggested connections for unused and not connected pins Connection / pin Current sense Floating To ground Through 1KΩ resistor N.C. Output Input X X X X Doc ID 10826 Rev 6 Through 10KΩ resistor 5/25 Electrical specifications VND830PEP-E 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Absolute maximum ratings Symbol V - 0.3 V - 200 mA Internally limited A -6 A +/- 10 mA +/- 10 mA 4000 4000 5000 5000 V V V V 54 W Internally limited °C Case operating temperature - 40 to 150 °C Storage temperature - 55 to 150 °C - IGND DC reverse ground pin current IOUT DC output current -IOUT Reverse DC output current IIN DC input current Istat DC status current ete Tc s b O 41 Reverse DC supply voltage Tj 2.2 Unit - VCC u d o e t e ol Pr s b O Electrostatic discharge (human body model:R=1.5KΩ; C=100pF) – Input – Status – Output – VCC )- s ( t c VESD ol Value DC supply voltage VCC Ptot ) s ( ct Parameter u d o Power dissipation TC = 25°C Pr Tstg Junction operating temperature Thermal data Table 4. Symbol Rthj-case Rthj-amb Thermal data (per island) Parameter Value Unit 2.3 °C/W Thermal resistance junction-case (max) Thermal resistance junction-ambient (one chip ON) (max) 1. When mounted on a standard single-sided FR-4 board with to all VCC pins. 0.5cm2 57(1) 42(2) °C/W of Cu (at least 35µm thick) connected 2. When mounted on a standard single-sided FR-4 board with 8cm2 of Cu (at least 35µm thick) connected to all VCC pins. 6/25 Doc ID 10826 Rev 6 VND830PEP-E 2.3 Electrical specifications Electrical characteristics Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless otherwise stated. Figure 3. Current and voltage conventions ) s ( ct u d o r P e t e l o Note: VFn = VCCn - VOUTn during reverse battery condition. Table 5. Symbol Parameter VCC VUSD VOV RON ete ol O bs Power output IS )- s b O Test conditions Min. Typ. Max. Unit Operating supply voltage 5.5 13 36 V Undervoltage shutdown c u d 3 4 5.5 V Overvoltage shutdown 36 t(s o r P V IOUT = 2A; Tj = 25°C IOUT = 2A; Tj = 125°C On-state resistance Supply current 60 120 mΩ mΩ Off-state; VCC = 13V; VIN = VOUT = 0V 12 40 µA Off-state; VCC = 13V; VIN = VOUT = 0V; Tj = 25°C 12 25 µA On-state; VCC = 13V; VIN = 5V; IOUT = 0A 5 7 mA 0 50 µA -75 0 µA IL(off1) Off-state output current VIN = VOUT = 0V IL(off2) Off-state output current VIN = 0V; VOUT = 3.5V IL(off3) Off-state output current VIN = VOUT = 0V; VCC = 13V; Tj = 125°C 5 µA IL(off4) Off-state output current VIN = VOUT = 0V; VCC = 13V; Tj = 25°C 3 µA Doc ID 10826 Rev 6 7/25 Electrical specifications Table 6. VND830PEP-E Switching (VCC = 13V) Symbol Parameter Max. Unit RL = 6.5Ω from VIN rising edge to VOUT = 1.3V - 30 - µs td(off) Turn-off delay time RL = 6.5Ω from VIN falling edge to VOUT = 11.7V - 30 - µs dVOUT/dt(on) Turn-on voltage slope RL = 6.5Ω from VOUT = 1.3V to VOUT = 10.4V - See Figure 14 - V/µs dVOUT/dt(off) Turn-off voltage slope RL = 6.5Ω from VOUT = 11.7V to VOUT = 1.3V - See Figure 13 - V/µs Symbol Parameter VF Forward on voltage Status leakage current CSTAT Status pin input capacitance VSCL Status clamp voltage (s) ct u d o Parameter - 0.6 V - Min. Typ. Max. Unit 0.5 V Normal operation; VSTAT= 5V 10 µA Normal Operation; VSTAT= 5V 100 pF 8 V V u d o r P e t e l o bs ISTAT= 1.6 mA -O ISTAT= 1mA ISTAT= - 1mA Test conditions Input low level IIL Low level input current VIH Input high level IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage Table 10. Protections(1) TR Typ. 6 6.8 -0.7 Logic inputs VIL TTSD Min. - IOUT = 1.3A; Tj = 150°C Test conditions ILSTAT Symbol Unit Parameter Status low output voltage Symbol Max. Status pin r P e t e l o Test conditions VSTAT Table 9. ) s ( ct VCC - output diode Symbol 8/25 Typ. Turn-on delay time Table 8. O Min. td(on) Table 7. bs Test conditions VIN = 1.25V Typ. Max. Unit 1.25 V 1 µA 3.25 V VIN = 3.25V 10 0.5 IIN = 1mA IIN = -1mA Parameter Min. Test conditions 6 µA V 6.8 - 0.7 8 V V Min. Typ. Max. Unit Shutdown temperature 150 175 200 °C Reset temperature 135 Doc ID 10826 Rev 6 °C VND830PEP-E Electrical specifications Protections(1) (continued) Table 10. Symbol Parameter Test conditions Thyst Thermal hysteresis tSDL Status delay in overload conditions Ilim Current limitation Vdemag Min. Typ. 7 15 Max. °C Tj > TTSD 6 9 5.5V < VCC < 36V 20 µs 15 15 A A VCC - VCC - VCC 41 48 55 Turn-off output clamp voltage IOUT = 2A; L = 6mH Unit V 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 11. ) s ( ct u d o Open-load detection Symbol Parameter Test conditions IOL Open-load on-state detection threshold VIN = 5V tDOL(on) Open-load on-state detection delay IOUT = 0A VOL Open-load off-state voltage detection threshold VIN = 0V tDOL(off) Open-load detection delay at turn-off Figure 4. ) (s Min. Typ. Max. Unit 50 100 200 mA 200 µs 3.5 V 1000 µs r P e t e l o s b O 1.5 2.5 t c u Open-load status timing (with external pull-up) d o r P e t e l o s b O Doc ID 10826 Rev 6 9/25 Electrical specifications Figure 5. VND830PEP-E Over temperature status timing Figure 6. ) s ( ct u d o Switching time waveforms r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 10/25 Table 12. Truth table Conditions Inputn Outputn Statusn Normal Operation L H L H H H Current Limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Over temperature L H L L H L Undervoltage L H L L X X Doc ID 10826 Rev 6 VND830PEP-E Electrical specifications Table 12. Truth table (continued) Conditions Inputn Outputn Statusn Overvoltage L H L L H H Output voltage > VOLn L H H H L H Output current < IOLn L H L H H L Table 13. Electrical transient requirements on VCC pin (part 1/3) ISO T/R ) s ( ct Test level 7637/1 Test pulse I II III IV 1 - 25V - 50V - 75V - 100V 2 + 25V + 50V + 75V 3a - 25V - 50V - 100V 3b + 25V + 50V + 75V 4 - 4V - 5V 5 + 26.5V + 46.5V Table 14. s ( t c u d o 7637/1 - 150V 0.1µs, 50Ω + 100V 0.1µs, 50Ω - 7V 100ms, 0.01Ω + 86.5V 400ms, 2Ω Test level II III IV C C C C 2 C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E r P e 1 O + 66.5V 0.2ms, 10Ω I Test pulse bs let 2ms, 10Ω Electrical transient requirements on VCC pin (part 2/3) ISO T/R t e l o O ) - 6V r P e + 100V o s b u d o Delays and impedance Table 15. Electrical transient requirements on VCC pin (part 3/3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. Doc ID 10826 Rev 6 11/25 Electrical specifications Figure 7. VND830PEP-E Waveforms ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 12/25 Doc ID 10826 Rev 6 VND830PEP-E Electrical specifications 2.4 Electrical characteristics curves Figure 8. Off-state output current Figure 9. IL(off1) (µA) High level input current Iih (µA) 2.5 5 2.25 4.5 Vcc=36V Vin=3.25V 2 4 1.75 3.5 1.5 3 1.25 2.5 1 2 0.75 1.5 0.5 1 0.25 0.5 0 u d o 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 50 ) s ( ct 75 100 125 150 175 Tc (°C) Figure 10. Input clamp voltage r P e Figure 11. Status leakage current t e l o Ilstat (µA) Vicl (V) 0.1 8 bs 0.09 7.8 Iin=1mA 7.6 7.4 ) s ( t 7.2 7 c u d 6.8 6.6 6.4 6.2 -50 -25 0 e t e ol o r P 25 50 75 100 125 0.07 0.06 0.05 0.04 0.03 0.02 0.01 150 175 0 -50 Tc (°C) -25 0 25 50 75 100 125 150 175 Tc (°C) Figure 12. Status low output voltage s b O -O Vstat=5V 0.08 Figure 13. Status clamp voltage Vstat (V) Vscl (V) 8 0.8 7.8 0.7 Istat=1mA Istat=1.6mA 7.6 0.6 7.4 0.5 7.2 0.4 7 6.8 0.3 6.6 0.2 6.4 0.1 6.2 0 6 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Doc ID 10826 Rev 6 13/25 Electrical specifications VND830PEP-E Figure 14. Turn-on voltage slope Figure 15. Turn-off voltage slope dVout/dt(on) (V/ms) dVout/dt(off) (V/ms) 1000 500 900 450 Vcc=13V Rl=6.5Ohm 800 Vcc=13V Rl=6.5Ohm 400 700 350 600 300 500 250 400 200 300 ) s ( ct 150 200 100 100 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 Figure 16. On-state resistance vs Tcase Ron (mOhm) Ron (mOhm) 120 100 90 70 O ) 80 60 t(s c u d 0 -50 -25 0 25 50 75 o r P Tc (°C) e t e ol 100 125 150 175 Tc=150°C Tc=25°C 60 50 Tc=-40°C 40 30 20 Iout=2A 10 0 175 5 10 15 20 25 30 35 40 Vcc (V) Figure 18. ILIM vs Tcase Figure 19. Input high level Ilim (A) Vih (V) 20 s b O 150 r P e bs 80 100 20 125 u d o t e l o 110 Iout=2A Vcc=8V; 13V & 36V 40 100 Figure 17. On-state resistance vs VCC 160 120 75 Tc (°C) Tc (°C) 140 50 3.6 18 Vcc=13V 3.4 16 14 3.2 12 3 10 2.8 8 6 2.6 4 2.4 2 0 2.2 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) 14/25 -50 -25 0 25 50 75 Tc (°C) Doc ID 10826 Rev 6 100 125 150 175 VND830PEP-E Electrical specifications Figure 20. Open-load on-state detection threshold Figure 21. Open-load off-state detection threshold Iol (mA) Vol (V) 140 5 135 4.5 Vin=0V Vcc=13V Vin=5V 130 4 125 3.5 120 3 115 2.5 110 2 105 1.5 100 1 95 0.5 90 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 50 u d o 75 Tc (°C) Figure 22. Input hysteresis voltage ) s ( ct 100 125 100 125 150 175 150 175 r P e Figure 23. Input low level Vhyst (V) Vil (V) 1.5 2.6 1.4 t e l o 2.4 1.3 bs 2.2 1.2 1.1 1 (s) 0.9 0.8 t c u 0.7 0.6 od 0.5 -50 -25 0 25 50 r P e 75 100 125 150 -O 2 1.8 1.6 1.4 1.2 1 175 -50 -25 0 25 Tc (°C) 50 75 Tc (°C) Figure 24. Overvoltage shutdown Figure 25. Undervoltage shutdown t e l o Vusd (V) Vov (V) s b O 8 50 48 7 46 6 44 5 42 4 40 3 38 2 36 1 34 32 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (°C) -25 0 25 50 75 100 125 150 175 Tc (°C) Doc ID 10826 Rev 6 15/25 Application information 3 VND830PEP-E Application information Figure 26. Application schematic ) s ( ct u d o r P e t e l o ) (s 3.1 s b O GND protection network against reverse battery t c u This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 d o r P e Solution 1: a resistor in the ground line (RGND only) t e l o This can be used with any type of load. bs O The following show how to dimension the RGND resistor: 1. RGND ≤ 600mV / (IS(on)max) 2. RGND ≥ ( - VCC) / (- IGND) where - IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC < 0 during reverse battery situations) is: PD = (- VCC)2/ RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that, if the microprocessor ground is not shared by the device ground, then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. 16/25 Doc ID 10826 Rev 6 VND830PEP-E Application information If the calculated power dissipation leads to a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below. 3.1.2 Solution 2: a diode (DGND) in the ground line A resistor (RGND = 1kΩ) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift ( ≈600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. 3.2 ) s ( ct u d o Load dump protection r P e Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than those shown in the ISO T/R 7637/1 table. 3.3 t e l o MCU I/O protection s b O If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/O pins from latching up. ) (s t c u The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os: d o r - VCCpeak / Ilatchup ≤ Rprot ≤ (VOHμC - VIH - VGND) / IIHmax P e Example t e l o For the following conditions: s b O VCCpeak = - 100V Ilatchup ≥ 20mA VOHμC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended values are: Rprot = 10kΩ 3.4 Open-load detection in off-state Off-state open-load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: Doc ID 10826 Rev 6 17/25 Application information VND830PEP-E 1. no false open-load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT = (VPU / (RL+RPU)) RL < VOlmin. 2. no misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU < (VPU – VOLmax) / IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched off when the module is in standby. The values of VOLmin, VOLmax and IL(off2) are available in the electrical characteristics section. Figure 27. Open-load detection in off-state ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 18/25 Doc ID 10826 Rev 6 VND830PEP-E Package and PC board thermal data 4 Package and PC board thermal data 4.1 PowerSSO-24 thermal data Figure 28. PowerSSO-24 PC board ) s ( ct Note: u d o r P e Layout condition of Rth and Zth measurements (PCB FR4 area= 78mm x 78mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm2). t e l o Figure 29. Rthj-amb vs PCB copper area in open box RTHj_amb(°C/W) 60 ) (s s b O t c u 55 d o r P e 50 s b O t e l o 45 40 0 1 2 3 4 5 6 7 8 9 PCB Cu heatsink area (cm^2) Doc ID 10826 Rev 6 19/25 Package and PC board thermal data VND830PEP-E Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse ZTH (°C/W) 100 Footprint 8 cm2 10 ) s ( ct 1 u d o 0.1 0.0001 0.001 0.01 0.1 t e l o 1 Time (s) r P e s b O 10 100 1000 Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24 ) (s t c u d o r P e t e l o s b O Equation 1: pulse calculation formula Z THδ = R TH ⋅δ+Z THtp (1 – δ) where δ = tP/T 20/25 Doc ID 10826 Rev 6 VND830PEP-E Package and PC board thermal data Table 16. Thermal parameters Area/island (cm2) Footprint R1 = R7 (°C/W) 0.1 R2 = R8 (°C/W) 0.9 R3 (°C/W) 1 R4 (°C/W) 4 R5 (°C/W) 13.5 R6 (°C/W) 37 C1 = C7 (W.s/°C) 0.0006 C2 = C8 (W.s/°C) 0.0025 C3 (W.s/°C) 0.025 22 ) s ( ct u d o C4 (W.s/°C) Pr 0.08 ete C5 (W.s/°C) ol C6 (W.s/°C) ) (s 8 s b O 0.7 3 5 t c u d o r P e t e l o s b O Doc ID 10826 Rev 6 21/25 Package information VND830PEP-E 5 Package information 5.1 ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 PowerSSO-24 mechanical data ) s ( ct Figure 32. PowerSSO-24 package dimensions u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 22/25 Doc ID 10826 Rev 6 VND830PEP-E Package information Table 17. PowerSSO-24 mechanical data Millimeters Symbol Min. Typ. Max. A 2.45 A2 2.15 2.35 a1 0 0.10 b 0.33 0.51 c 0.23 0.32 D 10.10 10.50 E 7.40 e 0.8 e3 8.8 F 2.3 let G1 o s b 10.1 h -O k 0° L 0.55 ) s ( ct N X u d o Y u d o r P e G H ) s ( ct 7.60 0.1 0.06 10.5 0.4 8° 0.85 10º 4.1 4.7 6.5 7.1 r P e t e l o s b O Doc ID 10826 Rev 6 23/25 Revision history 6 VND830PEP-E Revision history Table 18. Document revision history Date Revision Changes 04-Oct-2004 1 Initial release. 15-Nov-2004 2 Mechanical data updating. PowerSSO-24 thermal characteristics insertion 27-Nov-2004 3 PC board copper area correction. 12-Dec-2005 4 Electrical characteristics insertion. Absolute maximum ratings modification. 01-Jul-2009 5 Updated Figure 17: PowerSSO-24 mechanical data: – Deleted A (min) value – Changed A (max) value from 2.47 to 2.45 – Changed A2 (max) value from 2.40 to 2.35 – Changed a1 (max) value from 0.075 to 0.1 – Inserted F and k rows 20-Sep-2013 6 Updated Disclaimer. u d o ) (s r P e t e l o s b O t c u d o r P e t e l o s b O 24/25 ) s ( ct Doc ID 10826 Rev 6 VND830PEP-E ) s ( ct Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. u d o r P e All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 10826 Rev 6 25/25