VNH3SP30

® VNH3SP30 FULLY INTEGRATED H-BRIDGE MOTOR DRIVER TYPE VNH3SP30 RDS(on) (*) 34mΩ IOUT 30 A VCCmax 40 V (*) Typical per leg at 25°C s s s OUTPUT CURRENT:30 A 5V LOGIC LEVEL COMPATIBLE INPUTS UNDERVOLTAGE AND OVERVOLTAGE SHUT-DOWN s OVERVOLTAGE CLAMP s THERMAL SHUT DOWN s CROSS-CONDUCTION PROTECTION s LINEAR CURRENT LIMITER s V ERY LOW STAND-BY POWER CONSUMPTION s P WM OPERATION UP TO 10 KHz s P ROTECTION AGAINST: LOSS OF GROUND AND LOSS OF VCC MultiPowerSO-30 DESCRIPTION The VNH3SP30 is a full bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic HSD and two Low-Side switches. The HSD switch is designed using STMicroelectronics VIPower M0-3 technology that allows to efficiently integrate on the same die a true Power MOSFET with an intelligent signal/protection circuitry. The Low-Side switches are vertical MOSFETs manufactured using STMicroelectronics proprietary EHD (“STripFET™”) process. BLOCK DIAGRAM VCC OVERTEMPERATURE A OV + UV OVERTEMPERATURE B CLAMP A CLAMP B HSA DRIVER HSA LOGIC DRIVER HSB HSB CURRENT LIMITATION A OUTA CURRENT LIMITATION B OUTB LSA DRIVER LSA DRIVER LSB LSB GNDA DIAGA/ENA INA PWM INB DIAGB/ENB GNDB April 2004 1/26 VNH3SP30 The three dice are assembled in MultiPowerSO-30 package on electrically isolated leadframes. This package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. The input signals INA and INB can directly interface to the microcontroller to select the motor direction and the brake condition. The DIAG A/ENA or DIAGB/EN B, when connected to an external pull CONNECTION DIAGRAM (TOP VIEW) up resistor, enable one leg of the bridge. They also provide a feedback digital diagnostic signal. The normal condition operation is explained in the truth table on page 7. The PWM, up to 10KHz, lets us to control the speed of the motor in all possible conditions. In all cases, a low level state on the PWM pin will turn off both the LSA and LSB switches. When PWM rises to a high level, LSA or LSB turn on again depending on the input pin state. OUTA Nc Vcc Nc INA ENA/DIAGA Nc PWM Nc ENB/DIAGB INB Nc Vcc Nc OUTB 1 30 OUTA Heat Slug3 OUTA Nc GNDA GNDA GNDA OUTA Nc Vcc Nc OUTB VCC Heat Slug1 OUTB Heat Slug2 GNDB GNDB GNDB 16 15 Nc OUTB PIN DEFINITIONS AND FUNCTIONS PIN No 1, 25, 30 SYMBOL OUTA, Heat Slug2 FUNCTION Source of High-Side Switch A / Drain of Low-Side Switch A Not connected Drain of High-Side Switches and Power Supply Voltage Clockwise Input Status of High-Side and Low-Side Switches A; Open Drain Output PWM Input Not connected Status of High-Side and Low-Side Switches B; Open Drain Output Counter Clockwise Input Source of High-Side Switch B / Drain of Low-Side Switch B Source of Low-Side Switch A (*) Source of Low-Side Switch B (*) 2, 4,7,9,12,14,17, 22, NC 24,29 VCC, Heat 3, 13, 23 Slug1 5 INA 6 ENA/DIAGA 8 PWM 9 NC ENB/DIAGB 10 11 15, 16, 21 26, 27, 28 18, 19, 20 INB OUTB, Heat Slug3 GNDA GNDB (*) Note: GND A and GNDB must be externally connected together 2/26 VNH3SP30 PIN FUNCTIONS DESCRIPTION NAME VCC GNDA GNDB OUTA OUTB INA INB PWM ENA/DIAGA ENB/DIAGB DESCRIPTION Battery connection. Power grounds, must always be externally connected together. Power connections to the motor. Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of the bridge in normal operation according to the truth table (brake to VCC, Brake to GND, clockwise and counterclockwise). Voltage controlled input pin with hysteresis, CMOS compatible. Gates of Low-Side FETS get modulated by the PWM signal during their ON phase allowing speed control of the motor Open drain bidirectional logic pins. These pins must be connected to an external pull up resistor.When externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a High-Side FET or excessive ON state voltage drop across a Low-Side FET), these pins are pulled low by the device (see truth table in fault condition). BLOCK DESCRIPTIONS (see Electrical Block Diagram page 4) NAME LOGIC CONTROL OVERVOLTAGE + UNDERVOLTAGE HIGH SIDE CLAMP VOLTAGE HIGH SIDE AND LOW SIDE DRIVER LINEAR CURRENT LIMITER OVERTEMPERATURE PROTECTION FAULT DETECTION DESCRIPTION Allows the turn-on and the turn-off of the High Side and the Low Side switches according to the truth table. Shut-down the device outside the range [5.5V..36V] for the battery voltage. Protect the High-Side switches from the high voltage on the battery line in all configuration for the motor. Drive the gate of the concerned switch to allow a good RDS(on) for the leg of the bridge. In case of short circuit for the High-Side switch, limits the motor current by reducing its electrical characteristics. In case of short-circuit with the increase of the junction’s temperature, shuts-down the concerned High-Side to prevent its degradation and to protect the die. Signalize an abnormal behavior of the switches in the half-bridge A or B by pulling low the concerned ENx/DIAGx pin. 3/26 VNH3SP30 ABSOLUTE MAXIMUM RATING Symbol VCC Imax1 IR IIN IEN Ipw VESD Tj Tc TSTG Parameter Supply voltage Maximum output current (continuous) Reverse output current (continuous) Input current (INA and INB pins) Enable input current (DIAGA/ENA and DIAGB/ENB pins) PWM input current Electrostatic discharge (R=1.5kΩ, C=100pF) - Logic pins - Output pins: OUTA, OUTB, VCC Junction operating temperature Case operating temperature Storage temperature Value -0.3.. 40 30 -30 +/- 10 +/- 10 +/- 10 4 5 Internally Limited -40 to 150 -55 to 150 Unit V A A mA mA mA KV kV °C °C °C CURRENT AND VOLTAGE CONVENTIONS ICC IINA IINB IENA IENB IN A INB DIAGA/ENA DIAGB/ENB PWM Ipw GND VINA VINB VENA VENB Vpw IGND GNDA GNDB VCC VCC OUTA OUTB IOUTA IOUTB VOUTA VOUTB 4/26 VNH3SP30 THERMAL DATA See MultiPowerSO-30 Thermal Data section. ELECTRICAL CHARACTERISTICS (VCC=9V up to 18V; -40°C Low-Side Power MOSFET saturation detection. (1) When a fault condition is detected, the user can know which power element is in fault by monitoring the IN A, INB, DIAGA/EN A and DIAGB/ENB pins. In any case, when a fault is detected, the faulty half bridge is latched off. To turn-on the respective output (OUTX) again, the input signal must rise from low to high level. (1) An internal operational amplifier compares the Drain-Source MOSFET voltage with the internal reference (2.7V Typ.). The relevant Lowside PowerMOS is switched off when its Drain-Source voltage exceeds the reference voltage. TRUTH TABLE IN FAULT CONDITIONS (detected on OUTA) INA 1 1 0 0 X X X INB 1 0 1 0 X 1 0 DIAGA/ENA 0 0 0 0 0 0 0 DIAGB/ENB 1 1 1 1 0 1 1 OUTA OPEN OPEN OPEN OPEN OPEN OPEN OPEN OUTB H L H L OPEN H OPEN Fault Information Protection Action 8/26 VNH3SP30 TEST MODE The PWM pin allows to test the load connection between two half-bridges. In the test mode (Vpwm =-2V) the internal Power Mos gate drivers are disabled. The INA or INB inputs allow to turn-on the High Side A or B, respectively, in order to connect one side of the load at VCC voltage. The check of the voltage on the other side of the load allow to verify the continuity of the load connection. In case of load disconnection the DIADX/ENX pin corresponding to the faulty output is pulled down. ELECTRICAL TRANSIENT REQUIREMENTS ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 Class C E Test Level I -25V +25V -25V +25V -4V +26.5V Test Level II -50V +50V -50V +50V -5V +46.5V Test Level III -75V +75V -100V +75V -6V +66.5V Test Level IV -100V +100V -150V +100V -7V +86.5V Test Levels Result III C C C C C E Test Levels Delays and Impedance 2ms, 10Ω 0.2ms, 10Ω 0.1µs, 50Ω 0.1µs, 50Ω 100ms, 0.01Ω 400ms, 2Ω Test Levels Result IV C C C C C E Test Levels Result I C C C C C C Test Levels Result II C C C C C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 9/26 1 VNH3SP30 HALF-BRIDGE CONFIGURATION The VNH3SP30 can be used as a high power half-bridge driver achieving an on resistance per leg of 22.5mΩ. Suggested configuration is the following: VCC INA INB DIAGA/ENA DIAGB/ENB PWM OUTB IN A INB DIAGA/ENA DIAGB/ENB PWM OUTA M OUTA OUTB GNDA GNDB GNDA GNDB MULTI-MOTORS CONFIGURATION The VNH3SP30 can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow to put unused half-bridges in high impedance. Suggested configuration is the following: VCC INA INB DIAGA/ENA DIAGB/ENB PWM OUTB INA IN B DIAGA/ENA DIAGB/ENB PWM OUTA M2 OUTA OUTB GNDA GNDB GND A GNDB M1 M3 10/26 VNH3SP30 Figure 1: Definition of the delay times measurement (example of clockwise operation) VINA, t VINB t PWM t ILOAD tDEL tDEL t Figure 2: Definition of the Low Side Switching times PWM t VOUTA, B 90% 80% tf 20% 10% tr t 11/26 VNH3SP30 Figure 3: Definition of the High side Switching times VINA, tD(on) tD(off) t VOUTA 90% 10% t 12/26 VNH3SP30 Waveforms NORMAL OPERATION (DIAGA/EN A=1, DIAGB/EN B=1) DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUT B (int. pin) GATEA (int. pin) GATEB NORMAL OPERATION (DIAG A/EN A=1, DIAGB/ENB=0 and DIAGA/EN A=0, DIAGB/ENB=1) DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUT B (int. pin) GATEA (int. pin) GATEB CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND INA INB ILIM IOUTA TTSD Tj DIAGA/ENA DIAGB/ENB (int. pin) GATEA (int. pin) GATEB normal operation OUTA shorted to ground normal operation 13/26 VNH3SP30 Waveforms (Continued) OUTA shorted to VCC and undervoltage shutdown INA INB OUTA OUTB (int. pin) GATEA (int. pin) GATEB DIAGB/ENB DIAGA/ENA VCC normal operation OUTA shorted to VCC normal operation undervoltage shutdown Load disconnection test (INA=1, PWM=-2V) INA INB PWM (test mode) OUTA OUTB (int. pin)GATEA (int. pin) GATEB DIAGA/ENA DIAGB/ENB load connected load disconnected load connected back 14/26 VNH3SP30 On State Supply Current Is (mA) 8 7 6 5 4 3 2 Off State Supply Current Is (uA) 50 45 Vcc=18V INA or INB=5V Vcc=18V 40 35 30 25 20 15 10 1 0 -50 -25 0 25 50 75 100 125 150 175 5 0 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) High Level Input Current Iinh (µA) 8 7 Input Clamp Voltage Vicl (V) 8 7.75 Vin=3.25V 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175 7.5 7.25 7 6.75 6.5 6.25 6 -50 -25 Iin=1mA 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) Input High Level Voltage Vih (V) 3.6 3.4 3.2 3 Input Low Level Voltage Vil (V) 2.8 2.6 2.4 2.2 2 2.8 1.8 2.6 1.6 2.4 2.2 2 -50 -25 0 25 50 75 100 125 150 175 1.4 1.2 1 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) 15/26 VNH3SP30 Input Hysteresis Voltage Vihyst (V) 2 1.8 High Level Enable Pin Current Ienh (µA) 8 7 Vcc=13V 1.6 1.4 1.2 1 0.8 0.6 Ven=3.25V 6 5 4 3 2 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175 1 0 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) High Level Enable Voltage Venh (V) 4 3.8 3.6 3.4 3.2 Low Level Enable Voltage Venl (V) 2.8 2.6 Vcc=9V 2.4 2.2 2 Vcc=9V 3 1.8 2.8 1.6 2.6 2.4 2.2 2 -50 -25 0 25 50 75 100 125 150 175 1.4 1.2 1 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) Enable Output Low Level Voltage Vdiag (V) 0.6 0.525 Enable Clamp Voltage Vencl (V) 8 7.75 Ien=1mA 0.45 0.375 0.3 0.225 0.15 0.075 0 -50 -25 0 25 50 75 100 125 150 175 7.5 7.25 7 6.75 6.5 6.25 6 -50 -25 Ien=1mA 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) 16/26 VNH3SP30 PWM High Level Voltage Vpwh (V) 5 4.5 PWM Low Level Voltage Vpwl (V) 2.8 2.6 Vcc=9V 4 3.5 3 2 2.5 1.8 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 1.6 1.4 1.2 1 -50 -25 2.4 2.2 Vcc=9V 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) PWM High Level Current Ipwh (µA) 8 7 6 5 4 3 2 Overvoltage Shutdown Vov (V) 54 52 Vcc=9V Vpw=3.25V 50 48 46 44 42 40 38 1 0 -50 -25 0 25 50 75 100 125 150 175 36 34 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) Undervoltage Shutdown Vusd (V) 7 6.5 6 Current Limitation Ilim (A) 80 75 70 65 5.5 5 4.5 4 60 55 50 45 40 3.5 3 -50 -25 0 25 50 75 100 125 150 175 35 30 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) 17/26 VNH3SP30 On State High Side Resistance Vs. Tcase Ronhs (mOhm) 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175 On State High Side Resistance Vs. VCC Ronhs (mOhm) 80 70 Iload=12A Vcc=9V; 13V; 18V Iload=12A 60 50 40 30 Tc= 150ºC Tc= 25ºC 20 10 0 8 9 10 11 12 13 14 15 16 17 18 19 20 Tc= -40ºC Tc (ºC) Vcc (V) On State Low Side Resistance Vs. Tcase Ronls (mOhm) 40 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 150 175 On State Low Side Resistance Vs. VCC Ronls (mOhm) 40 35 Iload=12A Vcc=9V; 13V; 18V Iload=12A 30 25 20 15 10 Tc= 150ºC Tc= 25ºC Tc= -40ºC 5 0 8 9 10 11 12 13 14 15 16 17 18 19 20 Tc (ºC) Vcc (V) On State Leg Resistance Ron (mOhm) 90 80 70 60 Delay Time during change of operation mode tdel (µs) 1000 900 800 700 600 50 500 40 400 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) 18/26 VNH3SP30 Turn-on Delay Time td(on) (µs) 100 90 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175 Turn-off Delay Time td(off) (µs) 150 140 130 120 110 100 90 80 70 60 50 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) Output Voltage Rise Time tr (µs) 1 0.9 0.8 Output Voltage Fall Time tf (µs) 5 4.5 4 3.5 0.7 0.6 0.5 0.4 3 2.5 2 1.5 1 0.3 0.2 -50 -25 0 25 50 75 100 125 150 175 0.5 0 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) 19/26 VNH3SP30 MultiPowerSO-30 THERMAL DATA MultiPowerSO-30 PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 16cm2). CHIPSET CONFIGURATION HIGH SIDE CHIP HSAB LOW SIDE CHIP A LSA LOW SIDE CHIP B LSB Auto and mutual Rthj-amb Vs PCB copper area in open box free air condition (according to page 20 definitions) °C/W 45 40 35 30 25 20 15 10 5 0 0 52 10 15 cm of Cu Area (refer to PCB layout) RthA RthB = RthC RthAB = RthAC RthBC 20 20/26 VNH3SP30 THERMAL CALCULATION IN CLOCKWISE AND ANTI-CLOCKWISE OPERATION IN STEADYSTATE MODE HSA ON OFF HSB OFF ON LSA OFF ON LSB ON OFF TjHSAB PdHSA x RthHS + PdLSB x RthHSLS + Tamb PdHSB x RthHS + PdLSA x RthHSLS + Tamb TjLSA PdHSA x RthHSLS + PdLSB x RthLSLS + Tamb PdHSB x RthHSLS + PdLSA x RthLS + Tamb TjLSB PdHSA x RthHSLS + PdLSB x RthLS + Tamb PdHSB x RthHSLS + PdLSA x RthLSLS + Tamb Thermal resistances definition (values according to the PCB heatsink area) RthHS = RthHSA = R thHSB = High Side Chip Thermal Resistance Junction to Ambient (HSA or HSB in ON state) RthLS = R thLSA = R thLSB = Low Side Chip Thermal Resistance Junction to Ambient RthHSLS = R thHSALSB = RthHSBLSA = Mutual Thermal Resistance Junction to Ambient between High Side and Low Side Chips RthLSLS = RthLSALSB = Mutual Thermal Resistance Junction to Ambient between Low Side Chips THERMAL CALCULATION IN TRANSIENT MODE (*) TjHSAB = ZthHS x PdHSAB + ZthHSLS x (PdLSA + PdLSB) + Tamb TjLSA = ZthHSLS x PdHSAB + ZthLS x PdLSA + ZthLSLS x PdLSB + Tamb TjLSB = ZthHSLS x PdHSAB + ZthLSLS x PdLSA + Z thLS x PdLSB + Tamb Single pulse thermal impedance definition (values according to the PCB heatsink area) ZthHS = High Side Chip Thermal Impedance Junction to Ambient ZthLS = ZthLSA = ZthLSB = Low Side Chip Thermal Impedance Junction to Ambient ZthHSLS = ZthHSABLSA = ZthHSABLSB = Mutual Thermal Impedance Junction to Ambient between High Side and Low Side Chips ZthLSLS = ZthLSALSB = Mutual Thermal Impedance Junction to Ambient between Low Side Chips Pulse calculation formula Z TH δ = R TH ⋅ δ + Z THtp ( 1 – δ ) δ = tp ⁄ T where (*) Calculation is valid in any dynamic operating condition. Pd values set by user. 21/26 VNH3SP30 MultiPowerSO-30 HSD Thermal Impedance Junction Ambient Single Pulse 10 0 ZthHS 10 Footprint 4 cm2 8 cm2 16 cm2 Footprint 4 cm2 8 cm2 16 cm2 °C/W ZthHSLS 1 0 .1 0 .0 0 1 0 .0 1 0 .1 t i m e ( se c ) 1 10 100 10 0 0 MultiPowerSO-30 LSD Thermal Impedance Junction Ambient Single Pulse 100 Z thLS Footprint 4 cm2 8 cm2 16 cm2 Footprint 4 cm2 8 cm2 16 cm2 10 ZthLSLS °C/W 1 0 .1 0 .0 0 1 0 .0 1 0 .1 t i m e ( se c ) 1 10 100 1000 22/26 VNH3SP30 Thermal fitting model of an H-Bridge in MultiPowerSO-30 Thermal Parameter (*) Area/island (cm2) R1=R7 (°C/W) R2=R8 (°C/W) R3 (°C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) R9=R10=R15=R16 (°C/W) R11=R17 (°C/W) R12=R18 (°C/W) R13=R19 (°C/W) R14=R20 (°C/W) R21=R22=R23 (°C/W) C1=C7 (W.s/°C) C2=C8 (W.s/°C) C3 (W.s/°C) C4=C13=C19 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) C9=C15 (W.s/°C) C10=C11=C16=C17 (W.s/°C) C12=C18 (W.s/°C) C14=C20 (W.s/°C) Footprint 0.05 0.3 0.5 1.3 1.4 44.7 0.6 0.8 1.5 20 46.9 115 0.001 0.005 0.02 0.3 0.6 5 0.001 0.003 0.075 2.5 4 8 16 39.1 31.6 23.7 36.1 30.4 20.8 7 9 11 3.5 4.5 5.5 (*) The blank space means that the value is the same as the previous one. 23/26 VNH3SP30 MultiPowerSO-30 MECHANICAL DATA mm. MIN. 1.85 0 0.42 0.23 17.1 18.85 15.9 5.55 4.6 9.6 0.8 0deg 16 1 6.05 5.1 10.1 1.15 10deg 7deg 17.2 TYP MAX. 2.35 2.25 0.1 0.58 0.32 17.3 19.15 16.1 DIM. A A2 A3 B C D E E1 e F1 F2 F3 L N S 24/26 2 VNH3SP30 MultiPowerSO-30 SUGGESTED PAD LAY-OUT 25/26 VNH3SP30 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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