VNH7070AY
Automotive fully integrated H-bridge motor driver
Datasheet - production data
Output protected against short to ground and
short to VCC
Standby mode
Half bridge operation
Package: ECOPACK®
PowerSSO-36 TP
Description
Features
Type
RDS(on)
Iout
Vccmax
VNH7070AY
72 mtyp
per leg)
20 A
38 V
AEC-Q100 qualified
Output current: 20 A
3 V CMOS compatible inputs
Undervoltage shutdown
Overvoltage clamp
Thermal shutdown
Cross-conduction protection
Current and power limitation
Very low standby power consumption
Protection against loss of ground and loss of
VCC
PWM operation up to 20 KHz
Multisense monitoring functions
– Analog motor current feedback
– Chip temperature monitoring
– Battery voltage monitoring
Multisense diagnostic functions
– Output short to ground detection
– Thermal shutdown indication
– OFF-state open-load detection
– High-side power limitation indication
– Low-side overcurrent shutdown indication
– Output short to VCC detection
March 2019
This is information on a product in full production.
The device is a full bridge motor driver intended
for a wide range of automotive applications. The
device incorporates a dual monolithic high-side
driver and two low-side switches. All switches are
designed using STMicroelectronics® well known
and proven proprietary VIPower® M0 technology
that allows to efficiently integrate on the same die
a true Power MOSFET with an intelligent
signal/protection circuitry. The three dice are
assembled in a PowerSSO-36 package equipped
with three exposed islands for optimized
dissipation performances. This package is
specifically designed for the harsh automotive
environment and offers improved thermal
performance thanks to exposed die pads. A
Multisense_EN pin is available to enable the
MultiSense diagnostic. The input signals INA and
INB can directly interface the microcontroller to
select the motor direction and the brake condition.
Two selection pins (SEL0 and SEL1) are
available to address to the microcontroller the
information available on the Multisense. The
Multisense pin allows to monitor the motor current
by delivering a current proportional to the motor
current value and provides also the diagnostic
feedback according to the implemeted truth table.
When MultiSense_EN pin is driven low,
MultiSense pin is in high impedance condition.
The PWM, up to 20 KHz, allows to control the
speed of the motor in all possible conditions. In all
cases, a low level state on the PWM pin turns off
both the LSA and LSB switches.
DS12207 Rev 5
1/48
www.st.com
Contents
VNH7070AY
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1
Power limitation (high-side driver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2
Thermal shutdown (high-side and low-side) . . . . . . . . . . . . . . . . . . . . . . . 28
3.3
Current limitation and over current detector . . . . . . . . . . . . . . . . . . . . . . . 28
4
Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5
MultiSense operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1
MultiSense analog monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2
Multisense diagnostics flag in fault conditions . . . . . . . . . . . . . . . . . . . . . 31
6
Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7
Open Load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8
Immunity against transient electrical disturbances . . . . . . . . . . . . . . . 35
9
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1.1
9.2
10
2/48
Thermal resistances definition (values according to the PCB heatsink
area) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Thermal Characterization during transients . . . . . . . . . . . . . . . . . . . . . . . 38
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.1
PowerSSO-36 TP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.2
PowerSSO-36 TP packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DS12207 Rev 5
VNH7070AY
10.3
Contents
PowerSSO-36 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DS12207 Rev 5
3/48
3
List of tables
VNH7070AY
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
4/48
Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Logic inputs (Vcc=7 V up to 28 V;-40 °C< TjϬ
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MultiSense_EN = 1
DS12207 Rev 5
27/48
47
Protections
VNH7070AY
3
Protections
3.1
Power limitation (high-side driver)
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ∆Tj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as soon
as ∆Tj exceeds the safety level of ∆Tj_SD. The protection prevents fast thermal transient
effects and, consequently, reduces thermo-mechanical fatigue. When Power Limitation is
reached, The device enters in latch mode and generates the Fault Flag on
Multisense=VsenseH when the faulty leg diagnostic is selected (please refer to Table 13).
3.2
Thermal shutdown (high-side and low-side)
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175 °C), the device enters in latch mode and generates the Fault Flag on
Multisense = VsenseH (please refer to Table 13). The concerned high side can be switched
ON again as soon as Tj drops below TTR_HSD, INX is set low for a duration >
TLATCH_RST_HS and set high again.
3.3
Current limitation and over current detector
The device is equipped with an output current limiter in order to protect the silicon as well as
the other components of the system (e.g. bonding wires, wiring harness, connectors, loads,
etc.) from excessive current flow. High-side current limitation: in case of short-circuit,
overload or during load power-up, the output current is clamped to a safety level, ILIM_HSD,
by operating the output power MOSFET in the active region.
Low-side overcurrent detector: this protection senses the current flowing in the low-side. If
the current exceeds a safety level ISD_LS, the device will switch off after a filtering time
tsd_ld.
In case of fault conditions caused by Power Limitation or overtemperature or open
load/short to VCC in OFF state, the fault is indicated by the MultiSense pin being internally
switched to a “current limited” voltage source pulled to level VSENSEH (please refer to
Table 13).
28/48
DS12207 Rev 5
VNH7070AY
4
Typical application schematic
Typical application schematic
Figure 16. Typical application schematic
'
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Note:
To protect the device against Battery disconnection with energized inductive load when the
bridge driver goes into 3-state, suggested C(Vcc) is:
Emotor
C Vcc = ---------------------------------------------2
0.5 DVcc, max
where:
Emotor = 19.4 mJ;
DVcc,max = Vcc_AMR - Vcc_max;
Vcc_AMR = 38 V;
Vcc_max = 26 V (Vcc at jump start);
C(Vcc) = 270 µF.
DS12207 Rev 5
29/48
47
MultiSense operation
VNH7070AY
5
MultiSense operation
5.1
MultiSense analog monitoring
Diagnostic information on device and load status are provided by an analog output pin
(MultiSense) delivering the following signals:
Current monitor: current mirror of channel output current
VCC monitor: voltage proportional to VCC
TCASE: voltage proportional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in MultiSense multiplexer
addressing table.
Figure 17. MultiSense analog monitoring
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DS12207 Rev 5
*1'%
VNH7070AY
5.2
MultiSense operation
Multisense diagnostics flag in fault conditions
Multisense pin delivers fixed voltage (VSENSEH) with a certain current capability in case of:
Fault condition on activated high-side (in ON state) triggered by Power Limitation,
overtemperature protection, where MultiSense output is selected by SEL0 to high-side
in fault state.
Fault condition on activated low-side (in ON state) triggered by overcurrent shutdown,
overtemperature protection, where MultiSense output is selected by SEL0 to the same
leg (of high-side) where low-side is in fault state.
Short-circuit to VCC on OUT in OFF state (INA = INB = PWM = 0) selected by SEL0;
Special care must be taken for the OUTB (SEL0 = 0) because the fixed voltage is
available only before the device enters its stand-by mode after TD_STDBY (because
all control signals are set to 0).
In the configuration of half bridge (load connected between OUT and ground), when
open-load appears on OUT in OFF state (selected by SEL0) with activated external
pull-up resistor. Such condition causes an effect similar to the short circuit to VCC on
leg in OFF state (as mentioned in the above case, output voltage exceeds open-load
threshold VOL).
DS12207 Rev 5
31/48
47
Reverse battery protection
6
VNH7070AY
Reverse battery protection
The picture below shows a P-Channel MOSFET connected to the VCC pin.
Figure 18. P-channel MOSFET connected to the VCC pin
In normal operation the Zener diode plus the resistor generate a gate-source voltage
enough to switch on the P-MOSFET. In case of reverse battery polarity: the P-Ch is
switched off since its gate voltage is low. No current can flow in this state.
32/48
DS12207 Rev 5
VNH7070AY
7
Open Load detection in off-state
Open Load detection in off-state
The Open Load (OL) detection in off-state operates when output is deactivated (it means
INA = INB = PWM = 0). Open load detection is performed by reading the MultiSense output.
External (switched) pull-up resistor has to be used and dimensioned to pull output voltage
above the maximum open load detection voltage (VOL MAX) when load is not connected.
Possible conditions are specified in Table 14.
If pull up resistor is applied over switched circuitry, it allows to detect short to VCC from
Open load.
Depending on the application setup, two cases can be applied:
Half-bridge, with separate loads on OUTA and OUTB, open-load pull-up resistor RPU is
applied for each side; see an example in the figure below.
Figure 19. Open load detection in off-state - configuration two half-bridges
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if the device is used in half bridge configuration, the RPU value has to be:
V BATTmin – V OLmax
R pull_up ------------------------------------------------------I L off2 min @VOLmax
Full bridge (load connected between OUTA and OUTB), only one pull-up resistor RPU
is sufficient; see an example in the figure below.
DS12207 Rev 5
33/48
47
Open Load detection in off-state
VNH7070AY
Figure 20. Open load detection in off-state - configuration full-bridge
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if the device is used in H-bridge configuration, the equation is:
V BATTmin – V OLmax
R pull_up -------------------------------------------------------------2xI L off2 min @VOLmax
34/48
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DS12207 Rev 5
1026
VNH7070AY
8
Immunity against transient electrical disturbances
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 15: ISO 7637-2
electrical transient conduction along supply line.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), Section 4. The DUT is intended as the present device
only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns automatically
to normal operation after the test”.
Table 15. ISO 7637-2 electrical transient conduction along supply line
Test pulse
2011(E)
Test pulse severity level
with status II functional
performance status
Minimum
number of
pulses or
test time
Burst cycle/pulse
repetition time
Pulse duration
and pulse
generator
internal
impedance
Level
US(1)
1
III
-112 V
500 pulses
0.5 s
2a
III
+55
500 pulses
0.2 s
5s
50 µs, 2 Ω
3a
IV
-220 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
IV
+150 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
(2)
IV
-7 V
1 pulse
4
min.
max.
2 ms, 10 Ω
100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B(3)
40 V
5 pulse
1 min
400 ms, 2 Ω
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E)
2. Test pulse from ISO 7637-2:2004(E)
3. With 40 V external suppressor referred to ground (-40 °C < TJ < 150 °C)
DS12207 Rev 5
35/48
47
Package and PCB thermal data
VNH7070AY
9
Package and PCB thermal data
9.1
PowerSSO-36 thermal data
Figure 21. PowerSSO-36™ PC board
Note:
36/48
Board finish thickness 1.6 mm +/- 10%, board double layers and four layers, board
dimension 129x60, board material FR4, Cu thickness 0.070 mm (front and back side),
thermal vias spaced on a 1.2 mm x 1.2 mm grid, Vias pad clearance thickness 0.2 mm,
thermal via diameter 0.3 mm ± 0.08 mm, Cu thickness on vias 0.025 mm, footprint
dimension 4.1 mm x 6.5 mm.
DS12207 Rev 5
VNH7070AY
Package and PCB thermal data
Figure 22. Chipset configuration
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Figure 23. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition
Table 16. Thermal resistance junction-ambient
Footprint
Cu 2 cm2
Cu 8 cm2
4Layer
°C/W
RthA
64.4
47.1
37.8
24.1
RthB=RthC
72.4
51.7
43.2
30.2
RthAB=RthAC
43.3
26.8
19.3
10.8
RthBC
46.3
28.2
21.6
13.8
DS12207 Rev 5
37/48
47
Package and PCB thermal data
9.1.1
VNH7070AY
Thermal resistances definition (values according to the PCB heatsink
area)
RthHS = RthHSA = RthHSB = high-side chip thermal resistance junction to ambient
(HSA or HSB in ON state)
RthLS = RthLSA = RthLSB = low-side chip thermal resistance junction to ambient
RthHSLS = RthHSALSB = RthHSBLSA = mutual thermal resistance junction to
ambient between high-side and low-side chips
RthLSLS = RthLSALSB = mutual thermal resistance junction to ambient between lowside chip.
Table 17. Thermal model for junction temperature calculation in steady-state conditions
Chip 1
Chip 2
Chip 3
Tjchip1
Tjchip2
Tjchip3
ON
OFF
ON
Pdchip1.RthA + Pdchip3 .
RthAC + Tamb
Pdchip1.RthAB + Pdchip3 Pdchip1.RthAC + Pdchip3
. RthBC + Tamb
. RthC + Tamb
ON
ON
OFF
Pdchip1.RthA + Pdchip2 .
RthAB + Tamb
Pdchip1.RthAB + Pdchip2 Pdchip1.RthAC + Pdchip2
. RthB + Tamb
. RthBC + Tamb
ON
OFF
OFF
Pdchip1.RthA + Tamb
Pdchip1.RthAB + Tamb
OFF
ON
ON
(Pdchip2 + Pdchip3) .
RthAB + Tamb
Pdchip2 .
Pdchip2.RthB + Pdchip3 .
RthBC + Pdchip3 .
RthBC + Tamb
RthC + Tamb
9.2
Pdchip1.RthAC + Tamb
Thermal Characterization during transients
T hs = PD hs Z hs + Z hsls Pd IsA + Pd ISB + T amb
T IsA = Pd IsA Z Is + Pd hs Z hsls + Pd IsB Z IsIs + T amb
T IsB = Pd IsB Z Is + Pd hs Z hsls + Pd IsA Z IsIs + T amb
38/48
DS12207 Rev 5
VNH7070AY
Package and PCB thermal data
Figure 24. HSD thermal impedance junction ambient single pulse
Figure 25. LSD thermal impedance junction ambient single pulse
DS12207 Rev 5
39/48
47
Package and PCB thermal data
VNH7070AY
Table 18. Thermal parameters
2
Area/island (cm )
FP
2
8
4L
R1 (°C/W)
0.8
R2 (°C/W)
3.7
R3 (°C/W)
13
12
8.8
5.5
R4 (°C/W)
28
14
13
5
R5 (°C/W)
37
21
14
7
R6 (°C/W)
36
36
22
13
R7 (°C/W)
0.8
R8 (°C/W)
3.7
R9 (°C/W)
2.2
R10 (°C/W)
3.2
R11 (°C/W)
24
15.5
15.5
8.8
R12 (°C/W)
49
32
20
13
R13 (°C/W)
54
33
25
16
R14 (°C/W)
56
30
27
20
R15 (°C/W)
2.2
R16 (°C/W)
3.2
R17 (°C/W)
24
15.5
15.5
8.8
R18 (°C/W)
49
32
20
13
R19 (°C/W)
54
33
25
16
R20 (°C/W)
56
30
27
20
R21 (°C/W)
70
64
70
55
R22 (°C/W)
70
64
70
55
R23 (°C/W)
70
66
55
40
C1 (W·s/°C)
0.00028
C2 (W·s/°C)
0.0018
C3 (W·s/°C)
0.15
0.13
0.12
0.14
C4 (W·s/°C)
0.7
1.45
1.4
0.4
C5 (W·s/°C)
0.8
1.8
1.5
14
C6 (W·s/°C)
5
6
7.5
18
C7 (W·s/°C)
0.00028
C8 (W·s/°C)
0.0018
C9 (W·s/°C)
0.00007
C10 (W·s/°C)
0.015
C11 (W·s/°C)
0.08
0.07
0.07
0.06
C12 (W·s/°C)
0.35
0.3
0.37
0.26
40/48
DS12207 Rev 5
VNH7070AY
Package and PCB thermal data
Table 18. Thermal parameters (continued)
Area/island (cm2)
FP
2
8
4L
C13 (W·s/°C)
0.55
1.4
1.2
1.4
C14 (W·s/°C)
2.8
5.4
3.2
20
C15 (W·s/°C)
0.00007
C16 (W·s/°C)
0.015
C17 (W·s/°C)
0.08
0.07
0.07
0.06
C18 (W·s/°C)
0.35
0.3
0.37
0.26
C19 (W·s/°C)
0.55
1.4
1.2
1.4
C20 (W·s/°C)
2.8
5.4
3.2
20
C21 (W·s/°C)
0.011
0.009
0.009
0.005
C22 (W·s/°C)
0.011
0.009
0.009
0.005
C23 (W·s/°C)
0.017
0.016
0.016
0.011
Figure 26. Electrical equivalent model
DS12207 Rev 5
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47
Package and packing information
10
VNH7070AY
Package and packing information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
10.1
PowerSSO-36 TP package information
Figure 27. PowerSSO-36 TP package dimensions
("1($'5
42/48
DS12207 Rev 5
VNH7070AY
Package and packing information
Table 19. PowerSSO-36 TP mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
A
2.15
2.47
A2
2.15
2.40
a1
0
0.1
b
0.18
0.36
c
0.23
0.32
D
10.10
10.50
E
7.4
7.6
e
0.5
e3
8.5
F
2.3
G
H
0.1
10.1
10.5
h
0.4
k
0 deg
8 deg
L
0.6
1
M
4.3
N
10 deg
O
1.2
Q
0.8
S
2.9
T
3.65
U
1.0
X1
1.85
2.35
Y1
3
3.5
X2
1.85
2.35
Y2
3
3.5
X3
4.7
5.2
Y3
3
3.5
Z1
0.4
Z2
0.4
DS12207 Rev 5
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47
Package and packing information
10.2
VNH7070AY
PowerSSO-36 TP packing information
Figure 28. PowerSSO-36 TP tube shipment (no suffix)
C
Base Qty
Bulk Qty
Tube length (±0.5)
A
B
C (±0.1)
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 29. PowerSSO-36 TP tape and reel shipment (suffix “TR”)
Reel dimensions
Base Qty
Bulk Qty
A (max)
B (min)
C (±0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (±0.1)
P
D (±0.05)
D1 (min)
F (±0.1)
K (max)
P1 (±0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
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DS12207 Rev 5
No components
VNH7070AY
10.3
Package and packing information
PowerSSO-36 marking information
Figure 30. PowerSSO-36 marking information
.BSLJOHBSFB
4QFDJBMGVODUJPOEJHJU
&OHJOFFSJOHTBNQMF
CMBOL $PNNFSDJBMTBNQMF
1PXFS4405017*&8
OPUJOTDBMF
("1($'5
Parts marked as ‘&’ are not yet qualified and therefore not approved for use in production.
ST is not responsible for any consequences resulting from such use. In no event will ST be
liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to run
a qualification activity.
DS12207 Rev 5
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47
Order codes
11
VNH7070AY
Order codes
Table 20. Device summary
Order codes
Package
PowerSSO-36 TP
46/48
Tube
Tape and reel
VNH7070AY
VNH7070AYTR
DS12207 Rev 5
VNH7070AY
12
Revision history
Revision history
Table 21. Document revision history
Date
Revision
Description of changes
13-Jul-2017
1
Initial release.
17-May-2018
2
Updated Table 7: Power section; Table 10: Protections and diagnostics
(7 V < VCC < 18 V; -40 °C < Tj < 150 °C); Table 11: MultiSense
(7 V < VCC < 18 V; -40 °C < Tj < 150 °C).
Updated Section 3.1: Power limitation (high-side driver) and Section 3.2: Thermal
shutdown (high-side and low-side).
25-Jan-2019
3
Updated in cover page the first feature with “AEC-Q100 qualified”.
Updated Table 6, Table 11, Table 17 and Figure 16.
Added Figure 23, Table 16, Figure 24, Figure 25 and Table 18.
11-Feb-2019
4
In Table 7 updated Typ. value for RONHS parameter.
In Table 11 updated Min. value for IOUT_SAT parameter.
14-Mar-2019
5
Updated Figure 23, Figure 24 and Figure 25.
Updated Table 16 and Table 18.
DS12207 Rev 5
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47
VNH7070AY
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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No license, express or implied, to any intellectual property right is granted by ST herein.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
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DS12207 Rev 5
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