VNH7100BAS
Automotive fully integrated H-bridge motor driver
Datasheet - production data
Description
SO-16N
GAPGCFT00648
Features
Type
RDS(on)
Iout
VCCmax
VNH7100BAS
100 mtyp
per leg)
12 A
38 V
The device is a full bridge motor driver intended
for a wide range of automotive applications. The
device incorporates a dual monolithic high-side
driver and two low-side switches.
Both switches are designed using
STMicroelectronics’ well known and proven
proprietary VIPower® M0 technology that allows
to efficiently integrate on the same die a true
Power MOSFET with an intelligent
signal/protection circuitry. The three dies are
assembled in SO-16N package on electrically
isolated leadframes.
Moreover, its fully symmetrical mechanical design
allows superior manufacturability at board level.
The input signals INA and INB can directly
interface the microcontroller to select the motor
direction and the brake condition. A SEL0 pin is
available to address the information available on
the MultiSense to the microcontroller. The
MultiSense pin allows to monitor the motor
current by delivering a current proportional to the
motor current value.
AEC-Q100 qualified
Output current: 15 A
3 V CMOS-compatible inputs
Undervoltage shutdown
Overvoltage clamp
Thermal shutdown
Cross-conduction protection
Current and power limitation
Very low standby power consumption
Protection against loss of ground and loss of
VCC
PWM operation up to 20 kHz
The PWM, up to 20 kHz, allows to control the
speed of the motor in all possible conditions. In all
cases, a low level state on the PWM pin turns off
both the LSA and LSB switches.
Table 1. Device summary
MultiSense diagnostic functions
– Analog motor current feedback
– Output short to ground detection
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
Order codes
Package
SO-16N
Tube
Tape and reel
—
VNH7100BASTR
Output protected against short to ground and
short to VCC
Standby Mode
Half Bridge Operation
Package: ECOPACK®
March 2017
This is information on a product in full production.
DocID029596 Rev 2
1/39
www.st.com
Contents
VNH7100BAS
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
5
6
2/39
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2
OFF-state open-load detection – External circuitry dimensioning . . . . . . 23
3.3
Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 24
3.4
Device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1
SO16-N thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2
Package thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.1
Thermal characterization in steady state conditions . . . . . . . . . . . . . . . 28
4.2.2
Thermal characterization during transients . . . . . . . . . . . . . . . . . . . . . . 29
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1
SO-16N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2
SO-16N packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3
SO-16N marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DocID029596 Rev 2
VNH7100BAS
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic inputs (INA, INB, PWM) (VCC = 7 V up to 28 V; -40°C < Tj < 150°C) . . . . . . . . . . . . 10
Switching (VCC = 13 V; RLOAD = 5.2 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections and diagnostics (VCC = 7 V up to 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . 11
CS (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operative condition - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
On-state fault conditions - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Off-state - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . . 24
Thermal model for junction temperature calculation in steady-state conditions . . . . . . . . . 29
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SO-16N carrier tape dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DocID029596 Rev 2
3/39
3
List of figures
VNH7100BAS
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
4/39
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Low-side turn-on delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Time to shutdown for the low-side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input reset time for HSD - fault unlatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input reset time for LSD - fault unlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL) . . . . . . . . . . . . . . . . . . 17
Normal operative conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OUT shorted to ground and short clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OUT shorted to Vcc and short clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application schematic with reverse battery protection connected to Vbatt . . . . . . . . . . . . . 22
Application schematic with reverse battery protection connected to GND . . . . . . . . . . . . . 22
Suggested PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Half-bridge configuration (case a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Half-bridge configuration (case b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Multi-motors configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PCB layout (top and bottom): footprint, 2+2+2 cm2, 8+8+8 cm2 . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PCB 4 layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chipset configuration in steady state conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Auto and mutual Rthj-amb vs. PCB heat-sink area in open box free air condition . . . . . . . . 29
HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electrical equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SO-16N package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SO-16N reel 13” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SO-16N carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SO-16N schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SO-16N marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DocID029596 Rev 2
VNH7100BAS
1
Block diagram and pin description
Block diagram and pin description
Figure 1. Block diagram
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Table 2. Block description
Name
Description
Logic control
Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the truth table.
Undervoltage
Shuts down the device for battery voltage lower than 4 V.
High-side and low-side clamp voltage
Protect the high-side and the low-side switches from the
high voltage on the battery line.
High-side and low-side driver
Drive the gate of the concerned switch to allow a proper
Ron for the leg of the bridge.
Current limitation
Limits the motor current in case of short circuit.
In case of short-circuit with the increase of the junction
High-side and low-side overtemperature
temperature, it shuts down the concerned driver to prevent
protection
degradation and to protect the die.
Low-side overload detector
Detects when low side current exceeds shutdown current
and latches off the concerned Low side.
DocID029596 Rev 2
5/39
38
Block diagram and pin description
VNH7100BAS
Table 2. Block description (continued)
Name
Description
Fault detection
Signalizes the abnormal behavior of the switch through
MultiSense pin.
Power limitation
Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
Figure 2. Configuration diagram (top view)
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Table 3. Pin definitions and functions
6/39
Pin N°
Symbol
Function
1, 16
GNDA
Source of low-side switch A
2, 15
OUTA
Source of high-side switch A / drain of low-side switch A
3
INA
Clockwise input
4, 5, 12
VCC
Power supply voltage
6
INB
Counter clockwise input
7, 10
OUTB
Source of high-side switch B / drain of low-side switch B
8, 9
GNDB
Source of low-side switch B
11
PWM
Voltage controlled input pin with hysteresis, CMOS compatible. Gates
of low-side FETS get modulated by the PWM signal during their on
phase allowing speed control of the motor. Active high.
13
CS
Multiplexed analog sense output pin; it delivers a current proportional
to the motor current.
14
SEL0
Active high compatible with 3 V and 5 V CMOS outputs pin; in
combination with INA, INB, it addresses the CurrentSense information
delivered to the micro according to the operative truth table.
DocID029596 Rev 2
VNH7100BAS
2
Electrical specifications
Electrical specifications
Figure 3. Current and voltage conventions
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2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
Supply voltage
38
V
-VCC
Reverse DC Supply Voltage
0.3
V
Imax
Maximum output current (continuous)
Internally limited
A
Reverse output current (continuous)
-15
A
VCCPK
Maximum transient supply voltage (ISO 16750-2:2010
Test B clamped to 40 V; RL = 4 )
40
V
VCCJS
Maximum jump start voltage for single pulse short circuit
protection
28
V
Input current (INA and INB pins)
-1 to 10
mA
ISEL0
SEL0 DC input current
-1 to 10
mA
IPWM
PWM input current
-1 to 10
mA
IR
IIN
ISENSE
CS pin DC output current (VGND = VCC and VSENSE < 0 V)
10
CS pin DC output current in reverse (VCC < 0 V)
-20
DocID029596 Rev 2
mA
7/39
38
Electrical specifications
VNH7100BAS
Table 4. Absolute maximum ratings (continued)
Symbol
Value
Unit
VESD
Electrostatic discharge
(Human body model: R = 1.5 k; C = 100 pF)
– INA,INB, PWM
– SEL0
– CS
– VCC
– Output
2
2
2
4
4
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Tc
TSTG
2.2
Parameter
kV
Thermal data
Table 5. Thermal data
Symbol
Rthj-pin
Parameter
Thermal resistance junction-pin
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD
2. Device mounted on four-layers 2s2p PCB.
8/39
DocID029596 Rev 2
Unit
HSD
32
°C/W
LSD
45
°C/W
51-2)(1)
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2)(2)
1. Device mounted on two-layers 2s0p PCB.
Max. value
See Figure 24 °C/W
HSD
40.7
°C/W
LSD
55.4
°C/W
VNH7100BAS
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for VCC = 7 V up to 28 V; -40°C < Tj < 150°C, unless
otherwise specified.
Table 6. Power section
Symbol
VCC
IS
Parameter
Test conditions
Operating supply
voltage
Min.
4
Supply current
V
Off-state (standby)
INA = INB = 0; SEL0 = 0;
PWM = 0; Tj = 25 °C; VCC = 13 V;
1
μA
Off-state (standby)
INA = INB = 0; SEL0 = 0;
PWM = 0; VCC = 13 V; Tj = 85°C
1
μA
Off-state (standby)
INA = INB = 0; SEL0 = 0;
PWM = 0; VCC = 13 V; Tj = 125 °C
3
μA
2
4
mA
3.5
6
mA
1
1.8
ms
On-state: INA or INB = 5 V;
PWM = 0 or PWM = 5; SEL0 = X
Standby mode blanking
time
RONHS
Static high-side
resistance
RONLS
Static low-side
resistance
Vf
IL(off)
IL(off_h)
VCC = 13 V;
INA = INB = PMW = 0 V;
VSEL0 from 5 V to 0 V
0.2
IOUT = 2.5 A; Tj = 25°C
60
IOUT = 2.5 A; Tj = -40 to 150°C
40
IOUT = 2.5 A; Tj = -40°C to 150°C
IOUT = -2.5 A; Tj = 150°C
Off-state output current
of one leg
Off-state output current
of one leg with other
HSD on
m
120
IOUT = 2.5 A; Tj = 25°C
Free-wheeling diode
forward voltage
Max. Unit
28
Off-state (no standby)
INA = INB = 0; SEL0 = 5 V;
PWM= 0
tD_STBY(1)
Typ.
0.7
m
m
80
m
0.9
V
INA = INB = 0; PWM = 0;
VCC = 13 V; Tj = 25 °C
0
0.5
μA
INA = INB = 0; PWM = 0;
VCC = 13 V; Tj = 125 °C
0
3
μA
INA = 0; INB = 5 V; PWM = 0;
VCC = 13 V
20
60
μA
1. To power on the device from the standby, it is recommended to:
— toggle INA or INB or SEL0 from 0 to 1 first to come out from STBY mode
— toggle PWM from 0 to 1 with a delay of 20 μs
this avoids any over-stress on the device in case of existing short-to-battery.
DocID029596 Rev 2
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38
Electrical specifications
VNH7100BAS
Table 7. Logic inputs (INA, INB, PWM) (VCC = 7 V up to 28 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0.9
V
VIL
Input low level voltage
VIH
Input high level voltage
2.1
V
VIHYST
Input hysteresis voltage
0.2
V
IIN = 1 mA
VICL
Input clamp voltage
IINL
Input current
VIN = 0.9 V
IINH
Input current
VIN = 2.1 V
5.3
7.2
IIN = -1 mA
-0.7
V
V
1
μA
10
μA
0.9
V
SEL0 (VCC = 7 V up to 18 V; -40°C < Tj < 150°C)
VSELL
Input low level voltage
ISELL
Low level input current
VSELH
Input high level voltage
ISELH
High level input current
VSEL(hyst)
Input hysteresis voltage
VSELCL
VSEL = 0.9 V
μA
2.1
V
VSEL = 2.1 V
10
0.2
ISEL = 1 mA
Input clamp voltage
1
μA
V
5.3
7.5
ISEL = -1 mA
-0.8
V
V
PWM (VCC= 7 V up to 28 V; -40°C < Tj < 150°C)
VPWM
Input low level voltage
IPWM
Low level input current
VPWM
Input high level voltage
IPWMH
High level input current
0.9
VPWM = 0.9 V
VPMWCL
Input clamp voltage
1
μA
2.1
V
VPWM = 2.1 V
VPWM(hyst) Input hysteresis voltage
10
0.2
IPWM = 1 mA
V
μA
V
5.3
7.2
IPWM = -1 mA
-0.7
V
V
Table 8. Switching (VCC = 13 V; RLOAD = 5.2 Ω)
Symbol
f(1)
Parameter
Test conditions
PWM frequency
Min. Typ. Max.
0
kHz
td(on)
Turn-on delay time
Input rise time < 1μs (see Figure 6)
20
μs
td(off)
Turn-off delay time
Input rise time < 1μs (see Figure 6)
13
μs
tr
Rise time
See Figure 5
0.7
1.5
μs
tf
Fall time
See Figure 5
0.2
0.5
μs
Low-side turn-on delay
time
Input rise time < 1 μs (see Figure 7)
150
350
μs
tcross
40
1. Parameter guaranteed by design and characterization; not subjected to production test.
10/39
20
Unit
DocID029596 Rev 2
VNH7100BAS
Electrical specifications
Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VUSD
Undervoltage shutdown
4
V
VUSDreset
Undervoltage shutdown
reset
5
V
VUSDHyst
Undervolatge shutdown
Hysteresis
0.4
V
ILIM_H
High-side current
limitation
12
18
24
A
ISD_LS
Shutdown LS current
14
22
30
A
tSD_LS
Time to shutdown for the VINA = VINB = 0 V;
low-side
PWM = 5 V (see Figure 8)
5
μs
VCL_HSD
High-side clamp voltage
(VCC to OUTA = 0 or
OUTB = 0)
IOUT = 100 mA;
tCLAMP = 1 ms
38
46
V
VCL_LSD
Low-side clamp voltage
(OUTA = VCC or
OUTB = VCC to GND)
IOUT = 100 mA;
tCLAMP = 1 ms
38
46
V
TTSD_HS
High-side thermal
shutdown temperature
INx = 2.1 V
150
175
TTR_HS
High-side thermal reset
temperature
THYST_HS
200
135
High-side thermal
hysteresis (TSD_HS TR_HS)
°C
°C
7
°C
Low-side thermal
shutdown temperature
INx = 0 V
150
175
200
°C
VCL
Total clamp voltage
(VCC to GND)
IOUT = 100 mA;
tCLAMP = 1 ms
38
46
52
V
VOL
OFF-state open-load
voltage detection
threshold
INA = INB = 0; PWM = 0;
VSEL0 = 5 V for CHA;
VSEL0 = 0 V and within
tD_STBY for CHB
2
3
4
V
IL(off2)
OFF-state output sink
current
INA = INB = 0; VOUTx = VOL;
PWM = 0 V; VSEL0 = 5 V for
-100
CHA; VSEL0 = 0 V and within
tD_STBY for CHB
-15
μA
tDSTKON
OFF-state diagnostic
delay time from falling
edge of INPUT (see
Figure 4)
INA = 5 V to 0 V; INB = 0 V;
VSEL0 = 5 V; IOUT = 0 A;
VOUTA = 4 V; PWM = 0 V
150
350
μs
tD_VOL(1)
OFF-state diagnostic
delay time from rising
edge of VOUT (see
Figure 11)
INA = INB = 0 V; PWM = 0 V;
VOUTx = 0 V to 4 V;
VSEL0 = 5 V for CHA;
VSEL0 = 0 V and within
tD_STBY for CHB
5
30
μs
TTSD_LS
DocID029596 Rev 2
40
11/39
38
Electrical specifications
VNH7100BAS
Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Input reset time for highVINx = 5 V to 0 V; HSDx
tLatch_RST_HD(1) side fault unlatch (see
faulting
Figure 9)
3
10
20
μs
Input reset time for lowtLatch_RST_LS(1) side fault unlatch (see
Figure 10)
3
10
20
μs
VINx = 0 V to 5 V; LSDx
faulting
1. Parameter guaranteed by design and characterization; not subjected to production test.
Table 10. CS (7 V < VCC < 18 V; -40 °C < Tj < 150 °C)
Symbol
VSENSE_CL
Test conditions
MultiSense clamp
voltage
Min.
VCC = 18 V; ISENSE = -5 mA
Typ. Max. Unit
11
VCC = 18 V; ISENSE = 5 mA
-13
V
-9
K0
IOUT/ISENSE
IOUT = 0.05 A; VSENSE = 0.5 V;
Tj = -40°C to 150°C
536
K1
IOUT/ISENSE
IOUT = 0.2 A; VSENSE = 0.5 V;
Tj = -40°C to 150°C
710
K2
IOUT/ISENSE
IOUT = 2.5 A; VSENSE = 4 V;
Tj = -40°C to 150°C
1015 1120 1229
K3
IOUT/ISENSE
IOUT = 4 A; VSENSE = 4 V;
Tj = -40°C to 150°C
1040 1120 1200
V
1190 1670
dK0/K0(1)(2)
Analog sense current IOUT = 0.05 A; VSENSE = 0.5 V;
drift
Tj = -40°C to 150°C
-25
25
%
dK1/K1(1)(2)
Analog sense current IOUT = 0.2 A; VSENSE = 0.5 V;
drift
Tj = -40°C to 150°C
-21
21
%
dK2/K2(1)(2)
Analog sense current IOUT = 2.5 A; VSENSE = 4 V;
drift
Tj = -40°C to 150°C
-5
5
%
dK3/K3(1)(2)
Analog sense current IOUT = 4 A; VSENSE = 4 V;
drift
Tj = -40°C to 150°C
-4
4
%
VSENSE_SAT
Max analog sense
output voltage
ISENSE0
12/39
Parameter
MultiSense leakage
current
VCC = 7 V; RSENSE = 10 kΩ;
VSEL0 = 5 V; IOUTA = 4 A;
VINA = 5 V; PWM = 0; Tj = 150 °C
5
IOUT = 0 A; VSENSE = 0 V;
INx = 0 V; SEL0 = 0;
Tj = -40°C to 150°C (standby)
0
0.5
μA
IOUT = 0 A; VSENSE = 0 V;
INx = 0 V; SEL0 = 5 V;
Tj = -40°C to 150°C (no standby)
0
0.5
μA
INx = 5 V; PWM = 5 V:
Tj = -40°C to 150°C; IOUT = 0 A
0
5
μA
DocID029596 Rev 2
V
VNH7100BAS
Electrical specifications
Table 10. CS (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol
VSENSEH
Parameter
Test conditions
MultiSense output
voltage in fault
condition
VCC = 13 V; RSENSE = 1 kΩ
– E.g: OUTA in open-load
INA = 0 V; IOUTA = 0 A;
VOUTA = 4 V; VSEL0 = 5 V
VOUT_MSD(2)
VINA = 5 V; VINB = 0 V;
Output Voltage for
V
= 5 V; RSENSE = 2.7 k
MultiSense shutdown SEL0
IOUT = 2.5 A
ISENSE_SAT(2)
MultiSense
saturation current
VCC = 13 V; VSENSE = 4 V;
VINA = 5 V; VINB = 0 V;
VSEL0 = 5 V; Tj = 150 °C
IOUT_SAT(2)
Output saturation
current
ISENSEH
MultiSense output
voltage in fault
condition
Min.
Typ. Max. Unit
5
7
5
V
V
5.8
mA
VCC = 13 V; VSENSE = 4 V;
VINA = 5 V; VINB = 0 V;
VSEL0 = 5 V; IOUT = 7 A; Tj = 150°C
7
A
9 V < VCC < 18 V;
VSENSE = VSENSEH
10
20
30
mA
1. Analog sense current drift is deviation of factor K for a given device over (-40 °C to 150 °C and
9 V < VCC < 18 V) with respect to its value measured at Tj = 25 °C, VCC = 13 V.
2. Parameter guaranteed by design and characterization; not subjected to production test.
Figure 4. TDSTKON
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DocID029596 Rev 2
13/39
38
Electrical specifications
VNH7100BAS
Figure 5. Definition of the low-side switching times
PWM
t
VOUTA, B
90%
tf
80%
20%
10%
tr
t
Figure 6. Definition of the high-side switching times
VINA
tD(off)
tD(on)
t
VOUTA
90%
10%
t
14/39
DocID029596 Rev 2
VNH7100BAS
Electrical specifications
Figure 7. Low-side turn-on delay time
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DocID029596 Rev 2
15/39
38
Electrical specifications
VNH7100BAS
Figure 9. Input reset time for HSD - fault unlatch
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DocID029596 Rev 2
VNH7100BAS
Electrical specifications
Figure 11. OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL)
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DocID029596 Rev 2
17/39
38
Electrical specifications
VNH7100BAS
Table 11. Operative condition - truth table
Pin status
INA
INB
1
1
1
0
1
1
0
0
0
1
1
0
1
0
0
0
0
0
SEL0 PWM
1
x
0
1
0
Current Monitoring HSDB
Current Monitoring HSDA
Hi-Z
1
Hi-Z
0
0
0
1
(2)
HSDA
Current Monitoring HSDA
0
1
0
CS
1
1
HSDs and LDSs Status
Current Monitoring HSDB
1
Hi-Z
0
x(1)
LSDA HSDB LSDB
On
Off
On
Off
On
Off
Off
On
On
Off
Off
Off
On
Off
Off
On
On
Off
Off
Off
Off
On
On
Off
Off
Off
On
Off
Off
On
On
Off
Off
Off
On
Off
Off
On
Off
On
Off
Off
Off
Off
Off
Off
Off
Off
1. Refer to Table 13: Off-state - truth table
2. For INA =INB=SEL0 = PWM = 0, the device enters in standby after tD_STBY
Table 12. On-state fault conditions - truth table
Digital Input pins
CS
Note:
18/39
Comment
INA
INB
PWM SEL0
0
0
1
0
VsenseH
LSB protection triggered; LSB latched off
0
0
1
1
VsenseH
LSA protection triggered; LSA latched off
0
1
X
0
VsenseH
HSB protection triggered; HSB latched off
0
1
1
1
VsenseH
LSA protection triggered; LSA latched off
1
0
1
0
VsenseH
LSB protection triggered; LSB latched off
1
0
X
1
VsenseH
HSA protection triggered; HSA latched off
1
1
X
0
VsenseH
HSB protection triggered; HSB latched off
1
1
X
1
VsenseH
HSA protection triggered; HSA latched off
Other logic combinations on digital input pins not reported on the above table don’t allow to detect a
latched off channel.
DocID029596 Rev 2
VNH7100BAS
Electrical specifications
Table 13. Off-state - truth table
INA
INB
SEL0
PWM
OutA
OutB
CS
Description
VSENSEH
Case 1. OutA shorted to VCC if no
pull-up is applied
Case 2. No open-load in full bridge
configuration with an external pullup on OutB
Case 3. open-load in half bridge
configuration with an external pullup on OutA(motor connected
between OutA and Ground)
Hi-Z
Case 1. Open-load in full Bridge
configuration with an external pullup on OutB
Case 2. No open-load in half Bridge
configuration with external pull-up
on OutA (motor connected between
OutA and Ground)
Off-state diagnostic
VoutA>VOL
x
1
VoutAVOL
VSENSEH
Case 2. No open-load in full
bridge configuration with
external pull-up on OutA
Case 3. Open-load in half bridge
configuration with external pull-up
on OutB (motor connected between
OutB and Ground)
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DocID029596 Rev 2
21/39
38
Application information
3
VNH7100BAS
Application information
Here following there is the typical application schematic suggested for a proper operation of
the device in DC or PWM conditions.
Figure 15. Application schematic with reverse battery protection connected to Vbatt
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22/39
DocID029596 Rev 2
VNH7100BAS
Application information
Figure 17. Suggested PCB layout
Note:
PCB layout recommendation:
Optimized connection (short) between Drain LSD and Source HSD
Optimized GNDa and GNDb connection (symmetric connection)
3.1
Reverse battery protection
Three possible solutions can be considered:
A Schottky diode D connected to VCC pin
An N-channel MOSFET connected to the GND pin
A P-channel MOSFET connected to the VCC pin
In case the reverse battery protection is not present, the device sustains no more than -15 A
because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery
condition the I/Os of the device is pulled down to the VCC line (approximately -1.5 V).
Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If
IRmax is the maximum target reverse current through microcontroller I/Os, series resistor is:
V IOs – V CC
R = -----------------------------I Rmax
3.2
OFF-state open-load detection – External circuitry
dimensioning
The detection of an open-load in off state requires an external circuitry to be connected
between Output and VBATT.
For the detection it is necessary to put one network on each leg in case of Half Bridge
operation or one network on one of the output in case of full bridge (see Table 13: Off-state truth table).
The external circuitry is made up by an external pull-up resistor Rpull_up connecting the
output to a positive supply voltage VPU (VBatt).
DocID029596 Rev 2
23/39
38
Application information
VNH7100BAS
It is preferable to switch-off VPU by using an external pull_up switch to reduce the overall
standby current during he module standby mode.
Rpull_up must be dimensioned to ensure that in normal operative conditions VOUT > VOLmax.
To satisfy this condition the Rpull_up must be selected according to:
if the device is used in half bridge configuration, the equation is:
V BATTmin – V OLmax
R pull_up ------------------------------------------------------I L(off2)min[@VOLmax]
if the device is used in H-bridge configuration, the equation is:
V BATTmin – V OLmax
R pull_up ------------------------------------------------------------2 I L(off2)min[@VOLmax]
3.3
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 14.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns automatically
to normal operation after the test”.
Table 14. ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle / pulse
repetition time
Pulse duration and
pulse generator
internal impedance
Level
US(1)
1
III
-112 V
500 pulses
0,5 s
2a
III
+55 V
500 pulses
0,2 s
5s
50μs, 2
3a
IV
-220 V
1h
90 ms
100 ms
0.1μs, 50
3b
IV
+150 V
1h
90 ms
100 ms
0.1μs, 50
(2)
IV
-7 V
1 pulse
4
min
max
2ms, 10
100ms, 0.0 1
Load dump according to ISO 16750-2:2010
Test B(3)
40 V
5 pulse
1 min
400 ms, 2
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
24/39
DocID029596 Rev 2
VNH7100BAS
Application information
2. Test pulse from ISO 7637-2:2004(E).
3. With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).
3.4
Device configurations
Figure 18. Half-bridge configuration (case a)
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Note:
The VNH7100BAS can be used in half bridge configuration as the two legs can be
independently driven. The SEL0 pin can be used to address the diagnostic on the CS
according to the operative truth table.
Figure 19. Half-bridge configuration (case b)
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Note:
The VNH7100BAS can be used in applications where an half-bridge with a resistance of
50 mΩ per leg is needed.
DocID029596 Rev 2
25/39
38
Application information
VNH7100BAS
Figure 20. Multi-motors configuration
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26/39
The VNH7100BAS can easily be designed in multi motor driving configuration in the
applications where only one motor at a time must be activated. The SEL0 pin can be used to
read the diagnostic on the CS according to the operative truth table.
DocID029596 Rev 2
VNH7100BAS
Package and PCB thermal data
4
Package and PCB thermal data
4.1
SO16-N thermal data
Figure 21. PCB layout (top and bottom): footprint, 2+2+2 cm2, 8+8+8 cm2
DocID029596 Rev 2
27/39
38
Package and PCB thermal data
VNH7100BAS
Figure 22. PCB 4 layer
Note:
Board finish thickness 1.6 mm +/- 10%; Board double layer and four layers; Board
dimension 77x86 mm; Board Material FR4; Cu thickness 0.070mm (outer layers); Cu
thickness 0.035mm (inner layers); Thermal vias separation 1.2 mm; Thermal via diameter
0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm.
4.2
Package thermal data
4.2.1
Thermal characterization in steady state conditions
Figure 23. Chipset configuration in steady state conditions
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28/39
DocID029596 Rev 2
VNH7100BAS
Package and PCB thermal data
Figure 24. Auto and mutual Rthj-amb vs. PCB heat-sink area in open box free air
condition
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Table 15. Thermal model for junction temperature calculation in steady-state
conditions
Chip 1 Chip 2 Chip 3
4.2.2
Tjchip1
Tjchip2
Tjchip3
ON
OFF
ON
Pdchip1 • RthA + Pdchip3
• RthAC + Tamb
Pdchip1 • RthAB + Pdchip3
• RthBC + Tamb
Pdchip1 • RthAC + Pdchip3
• RthC + Tamb
ON
ON
OFF
Pdchip1 • RthA + Pdchip2
• RthAB + Tamb
Pdchip1 • RthAB + Pdchip2
• RthB + Tamb
Pdchip1 • RthAC + Pdchip2
• RthBC + Tamb
ON
OFF
OFF
Pdchip1 • RthA+ Tamb
Pdchip1 • RthAB + Tamb
Pdchip1 • RthAC + Tamb
ON
ON
ON
Pdchip1 • RthA + (Pdchip2 Pdchip2 • RthB + Pdchip1 • Pdchip1 • RthAB + Pdchip2
+ Pdchip3) • RthAB +
RthAB + Pdchip3 • RthBC • RthBC + Pdchip3 • RthC
Tamb
+ Tamb
+ Tamb
Thermal characterization during transients
Ths= Pdhs • Zhs + Zhsls • (PdlsA + PdlsB) + Tamb
TlsA= PdlsA • Zls + Pdhs • Zhsls + PdlsB • Zlsls + Tamb
TlsB= PdlsB • Zls + Pdhs • Zhsls + PdlsA • Zlsls + Tamb
DocID029596 Rev 2
29/39
38
Package and PCB thermal data
VNH7100BAS
Figure 25. HSD thermal impedance junction ambient single pulse
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Figure 26. LSD thermal impedance junction ambient single pulse
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30/39
DocID029596 Rev 2
VNH7100BAS
Package and PCB thermal data
Figure 27. Electrical equivalent model
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Table 16. Thermal parameters
2Layer PCB
Area/island (cm2)
4Layer
PCB
FP
2
8
R1 (°C/W)
5.3
5.3
5.3
5.3
R2 (°C/W)
12
12
12
12
R3 (°C/W)
30
25
25
30
R4 (°C/W)
42
12
12
2
R5 (°C/W)
85
45
30
17
R6 (°C/W)
5.3
5.3
5.3
5.3
R7 (°C/W)
6.3
6.3
6.3
6.3
R8 (°C/W)
12
12
12
12
R9 (°C/W)
30
30
30
42
R10 (°C/W)
68
52
48
10
R11 (°C/W)
75
80
60
26
R12 (°C/W)
6.3
6.3
6.3
6.3
R13 (°C/W)
12
12
12
12
R14 (°C/W)
30
30
30
42
R15 (°C/W)
68
52
48
10
R16 (°C/W)
75
80
60
26
R17 (°C/W)
120
100
100
100
R18 (°C/W)
120
100
100
100
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Package and PCB thermal data
VNH7100BAS
Table 16. Thermal parameters (continued)
2Layer PCB
Area/island (cm2)
32/39
4Layer
PCB
FP
2
8
R19 (°C/W)
180
170
170
170
R20 (°C/W)
180
170
170
170
C1 (W·s/°C)
0.00065
0.00065
0.00065
0.00065
C2 (W·s/°C)
0.018
0.018
0.018
0.018
C3 (W·s/°C)
0.08
0.1
0.1
0.1
C4 (W·s/°C)
0.2
0.5
1
2
C5 (W·s/°C)
1.5
2
6
12
C6 (W·s/°C)
0.00065
0.00065
0.00065
0.00065
C7 (W·s/°C)
0.0005
0.0005
0.0005
0.0005
C8 (W·s/°C)
0.018
0.018
0.018
0.018
C9 (W·s/°C)
0.06
0.06
0.06
0.06
C10 (W·s/°C)
0.08
0.1
0.2
0.5
C11 (W·s/°C)
1
2.5
3
6
C12 (W·s/°C)
0.0005
0.0005
0.0005
0.0005
C13 (W·s/°C)
0.018
0.018
0.018
0.018
C14 (W·s/°C)
0.06
0.06
0.06
0.06
C15 (W·s/°C)
0.08
0.1
0.2
0.5
C16 (W·s/°C)
1
2.5
3
6
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VNH7100BAS
5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.1
SO-16N package information
Figure 28. SO-16N package dimensions
("1($'5
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38
Package information
VNH7100BAS
Table 17. SO-16N mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
A
1.75
A1
0.10
0.25
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
9.80
9.90
10.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
1.27
h
0.25
0.50
L
0.40
1.27
k
0
8
ccc
5.2
0.10
SO-16N packing information
Figure 29. SO-16N reel 13”
"DDFTT)PMFBU
4MPU-PDBUJPO
NNNJO
8
"
/
%
$
8
#
34/39
*GQSFTFOU
UBQFTMPUJODPSF
GPSUBQFTUBSU
NNNJOXJEUIY
NNNJOEFQUI
5"1($'5
DocID029596 Rev 2
VNH7100BAS
Package information
Table 18. Reel dimensions
Description
Value(1)
Base quantity
2500
Bulk quantity
2500
A (max)
330
B (min)
1.5
C (+0.5, -0.2)
13
D (min)
20.2
N
100
W1 (+2 /-0)
16.4
W2 (max)
22.4
1. All dimensions are in mm.
Figure 30. SO-16N carrier tape
("1($'5
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Package information
VNH7100BAS
Table 19. SO-16N carrier tape dimensions
Description
Value
A0
6.55 ± 0.1
B0
10.38 ± 0.1
K0
2.10 ± 0.1
K1
1.80 ± 0.1
F
7.50 ± 0.1
P1
8.00 ± 0.1
W
16.00 ± 0.3
Figure 31. SO-16N schematic drawing of leader and trailer tape
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DocID029596 Rev 2
VNH7100BAS
5.3
Package information
SO-16N marking information
Figure 32. SO-16N marking information
.BSLJOHBSFB
4QFDJBMGVODUJPOEJHJU
&4&OHJOFFSJOHTBNQMF
CMBOL $PNNFSDJBMTBNQMF
40/5017*&8
OPUJOTDBMF
("1($'5
Note:
Parts marked as -ES are not yet qualified and therefore not approved for use in production.
ST is not responsible for any consequences resulting from such use. In no event will ST be
liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to run
a qualification activity.
Commercial Samples: fully qualified parts from ST standard production with no usage
restrictions.
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Revision history
6
VNH7100BAS
Revision history
Table 20. Document revision history
Date
Revision
23-Aug-2016
1
Initial release.
2
Document status promoted from target specification to production data.
Added ‘AEC-Q100 qualified’ as first feature in cover page.
Modified in cover page the value of VCCmax parameter from 41 V to
38 V.
Update on Table 10 the values of K0, K2 and K3 parameters, and for
ISENSEH parameter updated ‘Test conditions’ and Min. value.
Updated Table 12.
Updated Figure 25, Figure 26 and Figure 27.
Updated Table 16: Thermal parameters.
02-Mar-2017
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Changes
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VNH7100BAS
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
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