VNI8200XP-32
Octal high-side smart power solid-state relay with serial/parallel
selectable interface on-chip
Datasheet - production data
PowerSSO-36 package
with exposed pad down (EPD)
Features
Type
VNI8200XP-32
Vdemag
(1)
VCC-45 V
RDS(on)
(1)
0.11 Ω
IOUT
(1)
1A
VCC
45 V
Notes:
(1)
Per channel
Applications
Output current: 1 A per channel
Serial/parallel selectable interface
Short-circuit protection
8-bit and 16-bit SPI interface for IC
command and control diagnostic
Channel overtemperature detection and
protection
Thermal independence of separate channels
All type of loads (resistive, capacitive,
inductive load) are driven
Loss of GND protection
Power Good diagnostic
Undervoltage shutdown with hysteresis
August 2015
Overvoltage protection (VCC clamping)
Very low supply current
Common fault open drain output
IC warning temperature detection
Channel output enable
100 mA high efficiency step-down switching
regulator with integrated boot diode
Adjustable regulator output
Switching regulator disable
5 V and 3.3 V compatible I/Os
Channel output status LED driving 4x2
multiplexed array
Fast demagnetization of inductive loads
ESD protection
Designed to meet IEC61131-2,
IEC61000-4-4 and IEC61000-4-5
Programmable logic control
Industrial PC peripheral input/output
Numerical control machines
Table 1: Device summary
Order code
VNI8200XP-32
VNI8200XPTR-32
DocID027849 Rev 3
This is information on a product in full production.
Package
Packing
Tube
PowerSSO-36
Tape and
reel
1/43
www.st.com
Contents
VNI8200XP-32
Contents
1
Description....................................................................................... 6
2
Block diagram.................................................................................. 7
3
Pin connection................................................................................. 8
4
5
Maximum ratings ........................................................................... 10
Electrical characteristics .............................................................. 12
5.1
Power section.................................................................................. 12
5.2
SPI characteristics .......................................................................... 13
5.3
Switching ......................................................................................... 13
5.4
Logic inputs ..................................................................................... 14
5.5
Protection and diagnostic ................................................................ 14
5.6
Step-down switching regulator ........................................................ 16
5.7
LED driving array ............................................................................ 16
6
Reverse polarity protection .......................................................... 17
7
8
Demagnetization energy ............................................................... 18
Truth table ...................................................................................... 19
9
Pin function description................................................................ 20
10
11
2/43
9.1
SPI/parallel selection mode (SEL2)................................................. 20
9.2
Serial data in (SDI) .......................................................................... 20
9.3
Serial data out (SDO) ...................................................................... 20
9.4
Serial data clock (CLK) ................................................................... 20
9.5
Slave select ..................................................................................... 21
9.6
8/16-bit selection (SEL1) ................................................................. 21
9.7
Output enable (OUT_EN) ................................................................ 21
9.8
IC warning case temperature detection ........................................... 22
9.9
Fault indication ................................................................................ 22
9.10
Power Good ( PG ) ........................................................................ 23
9.11
Programmable watchdog counter reset (WD) ................................. 23
SPI operation (SEL2 = H) .............................................................. 25
10.1
8-bit SPI mode (SEL1 = L) .............................................................. 25
10.2
16-bit SPI mode (SEL1 = H) ............................................................ 25
LED driving array .......................................................................... 27
DocID027849 Rev 3
VNI8200XP-32
Contents
12
Step-down switching regulator .................................................... 28
13
Typical circuits and conventions ................................................. 29
14
Thermal management ................................................................... 32
14.1
Thermal behavior ............................................................................ 33
15
Interface timing diagram ............................................................... 34
16
Switching parameter test conditions ........................................... 35
17
Package information ..................................................................... 36
18
17.1
PowerSSO-36 package information ................................................ 36
17.2
Packing information ......................................................................... 39
Revision history ............................................................................ 42
DocID027849 Rev 3
3/43
List of tables
VNI8200XP-32
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pin description .............................................................................................................................. 8
Table 3: Absolute maximum ratings ......................................................................................................... 10
Table 4: Thermal data ............................................................................................................................... 11
Table 5: Power section ............................................................................................................................. 12
Table 6: SPI characteristics ...................................................................................................................... 13
Table 7: Switching..................................................................................................................................... 13
Table 8: Logic inputs ................................................................................................................................. 14
Table 9: Protection and diagnostic ........................................................................................................... 14
Table 10: Step-down switching regulator.................................................................................................. 16
Table 11: LED driving array ...................................................................................................................... 16
Table 12: Truth table ................................................................................................................................. 19
Table 13: Pin function description ............................................................................................................. 20
Table 14: Programmable watchdog time .................................................................................................. 23
Table 15: Command 8-bit frame (master-to-slave) ................................................................................... 25
Table 16: Fault 8-bit frame (slave-to-master) ........................................................................................... 25
Table 17: Command 16-bit frame (master-to-slave) ................................................................................. 25
Table 18: Fault 16-bit frame (slave-to-master) ......................................................................................... 26
Table 19: PowerSSO-36 mechanical data................................................................................................ 38
Table 20: PowerSSO-36 tube shipment mechanical data ........................................................................ 39
Table 21: PowerSSO-36 tape dimension mechanical data ...................................................................... 40
Table 22: PowerSSO-36 reel dimension mechanical data ....................................................................... 41
Table 23: Document revision history ........................................................................................................ 42
4/43
DocID027849 Rev 3
VNI8200XP-32
List of figures
List of figures
Figure 1: Block diagram .............................................................................................................................. 7
Figure 2: Pin connection (top view) ............................................................................................................ 8
Figure 3: Reverse polarity protection ........................................................................................................ 17
Figure 4: Maximum demagnetization energy vs. load current, typical values .......................................... 18
Figure 5: SPI mode diagram ..................................................................................................................... 21
Figure 6: Output channel enable/disable behavior ................................................................................... 22
Figure 7: Power Good diagnostic ............................................................................................................. 23
Figure 8: Watchdog reset ......................................................................................................................... 24
Figure 9: LED driving array ....................................................................................................................... 27
Figure 10: Typical circuit for switching regulation VDC-out = 3.3 V ............................................................. 29
Figure 11: Typical circuit for switching regulation VDC-out = 5 V ................................................................ 30
Figure 12: SPI directional logic convention............................................................................................... 31
Figure 13: PowerSSO-36 thermal impedance vs. time ............................................................................ 32
Figure 14: Thermal behavior ..................................................................................................................... 33
Figure 15: Serial timing ............................................................................................................................. 34
Figure 16: dV/dt(ON) and dV/dt(OFF) time diagram test conditions ........................................................ 35
Figure 17: td(ON) and td(OFF) time diagram test conditions ........................................................................... 35
Figure 18: PowerSSO-36 package outline ............................................................................................... 36
Figure 19: PowerSSO-36 package outline details .................................................................................... 37
Figure 20: PowerSSO-36 package outline details (section B-B) .............................................................. 37
Figure 21: PowerSSO-36 tube shipment outline ...................................................................................... 39
Figure 22: PowerSSO-36 tape dimension outline .................................................................................... 40
Figure 23: PowerSSO-36 reel shipment outline ....................................................................................... 41
DocID027849 Rev 3
5/43
Description
1
VNI8200XP-32
Description
The VNI8200XP-32 is a monolithic 8-channel driver featuring a very low supply current,
with integrated SPI interface and high efficiency 100 mA micropower step-down switching
regulator peak current control loop mode. The IC, realized in STMicroelectronics
VIPower™ technology, is intended to drive any kind of load with one side connected to
ground.
Active channel current limitation combined with thermal shutdown, independent for each
channel, and automatic restart, protect the device against overload.
Additional embedded functions are: loss of GND protection that automatically turns off the
device outputs in case of ground disconnection, undervoltage shutdown with hysteresis,
Power Good diagnostic for valid supply voltage range recognition, output enable function
for immediate power outputs ON/OFF, and programmable watchdog function for
microcontroller safe operation; case overtemperature protection to control the IC case
temperature.
The device embeds a four-wire SPI serial peripheral with selectable 8 or 16-bit operations;
through a select pin the device can also operate with a parallel interface.
Both the 8-bit and 16-bit SPI operations are compatible with daisy chain connection.
The SPI interface allows command of the output driver by enabling or disabling each
channel featuring, in 16-bit format, a parity check control for communication robustness. It
also allows the monitoring of the status of the IC signaling Power Good, overtemperature
condition for each channel, IC pre-warning temperature detection.
Built-in thermal shutdown protects the chip from overtemperature and short-circuit. In
overload condition, the channel turns OFF and ON again automatically after the IC
temperature decreases below a threshold fixed by a temperature hysteresis so that junction
temperature is controlled. If this condition makes case temperature reaching case
temperature limit, TCSD, overloaded channels are turned OFF and restart, nonsimultaneously, when case and junction temperature decrease below their own reset
threshold. If the case of thermal reset, the channels loaded are not switched on until the
junction temperature reset event. Non-overloaded channels continue to operate normally.
Case temperature above TCSD is reported through the TWARN open drain pin.
An internal circuit provides a not latched common FAULT indicator reporting if one of the
following events occurs: channel OVT (overtemperature), parity check fail. The Power
Good diagnostic warns the controller that the supply voltage is below a fixed threshold.
The watchdog function is used to detect the occurrence of a software fault of the host
controller. The watchdog circuitry generates an internal reset on expiry of the internal
watchdog timer. The watchdog timer reset can be achieved by applying a negative pulse
on the WD pin. The watchdog function can be disabled by the WD_EN dedicated pin. This
pin also allows the programming of a wide range of watchdog timings.
An internal LED matrix driver circuitry (4 rows, 2 columns) allows the detection of the status
of the single outputs. An integrated step-down voltage regulator provides supply voltage to
the internal LED matrix driver and logic output buffers and can be used to supply the
external optocouplers if the application requires isolation. The regulator is protected against
short-circuit or overload conditions thanks to pulse-by-pulse current limit with a peak
current control loop.
6/43
DocID027849 Rev 3
VNI8200XP-32
Block diagram
DC-DC
converter
VCC
PG
DCVDD
V REF
P HAS E
FB
BOO T
Figure 1: Block diagram
Undervoltage and
Power Good
SEL1/IN1
WD_EN/IN2
OUT_EN/IN3
WD/IN4
SDI/IN5
SPI
Logic
CLK/IN6
SS/IN7
SDO/IN8
SEL2
Current limiter
Junction temp.
detection
VREG
ROW0
ROW1
ROW2
Vcc
clamp
Clamp power
Case temp.
detection
LED
drivng
Pull- down
resistor
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
DocID027849 Rev 3
TWARN
GND
FAU LT
CO L1
ROW3
CO L0
2
Block diagram
GIPG020420151244LM
7/43
Pin connection
3
VNI8200XP-32
Pin connection
Figure 2: Pin connection (top view)
1
2
SEL2
NC
SEL1/IN1
NC
3
WD_EN/IN2
OUT1
4
OUT_EN/IN3
OUT2
WD/IN4
OUT3
SDI/IN5
OUT4
CLK/IN6
OUT5
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SS/IN7
TAB=Vcc
OUT6
SDO/IN8
OUT7
VREG
OUT8
COL0
NC
COL1
BOOT
DCVDD
PHASE
GND
VREF
ROW0
FB
ROW1
TWARN
ROW2
FAULT
ROW3
PG
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GIPG020420151249LM
Table 2: Pin description
8/43
Pin
Name
Type
Description
1
SEL2
Logic input
SPI/parallel selection mode
2
SEL1/IN1
Logic input
8/16-bit SPI selection mode/channel 1 input
3
WD_EN/ IN2
Logic/analog
input
4
OUT_EN /IN3
Logic input
Output enable/channel 3 input
5
WD/IN4
Logic input
Watchdog input. The internal watchdog counter is
cleared on the falling edges/channel 4 input
6
SDI/IN5
Logic input
Serial data input/channel 5 input
7
CLK/IN6
Logic input
Serial clock/channel 6 input
8
SS /IN7
Logic input
Slave select/channel 7 input
9
SDO/IN8
Logic
input/output
Serial data output/channel 8 input
10
VREG
Power supply
SPI/inputs/LED supply voltage
11
COL0
Open source
output
LED source output
12
COL1
Open source
output
LED source output
13
DCVDD
Analog output
Internally generated DC-DC low voltage supply (to
be connected to external 10 nF capacitor)
Watchdog enable_setting/channel 2 input
DocID027849 Rev 3
VNI8200XP-32
Pin connection
Pin
Name
Type
Description
14
VREF
Analog output
Internally generated DC-DC voltage reference (to be
connected to external 10 nF capacitor)
15
ROW0
Open drain
output
Status channel 1-2
16
ROW1
Open drain
output
Status channel 3-4
17
ROW2
Open drain
output
Status channel 5-6
18
ROW3
Open drain
output
Status channel 7-8
19
PG
Open drain
output
Power Good diagnostic, active low
20
FAULT
Open drain
output
Fault indication, active low
21
TWARN
Open drain
output
IC case warning temperature detection, active low
Analog input
Step-down feedback input. The output voltage,
directly connected to this pin, results in an output
voltage of 3.3 V. An external resistor divider is
required for higher output voltages
22
FB
23
GND
24
PHASE
Power output
Step-down output
25
BOOT
Power output
Step-down bootstrap voltage. Used to provide a
drive voltage, higher than the supply voltage, to
power the switch of the step-down regulator
26
NC
27
OUT8
Power output
Channel 8 power output
28
OUT7
Power output
Channel 7 power output
29
OUT6
Power output
Channel 6 power output
30
OUT5
Power output
Channel 5 power output
31
OUT4
Power output
Channel 4 power output
32
OUT3
Power output
Channel 3 power output
33
OUT2
Power output
Channel 2 power output
34
OUT1
Power output
Channel 1 power output
35
NC
Not connected
36
NC
Not connected
TAB
TAB
Ground
Not connected
Power supply
Exposed tab internally connected to VCC
DocID027849 Rev 3
9/43
Maximum ratings
4
VNI8200XP-32
Maximum ratings
Table 3: Absolute maximum ratings
Symbol
Parameter
VCC
Power supply voltage
-VCC
Reverse supply voltage
VREG
Value
Unit
45
V
-0.3
V
Logic supply voltage
-0.3 to +6
V
VFAULT
VTWARN
VPG
Voltage range on pins TWARN , FAULT , PG
-0.3 to +6
V
VBOOT
Bootstrap peak voltage VPHASE = VCC
VCC+6
V
VROW
Voltage range on ROW pins
-0.3 to +6
V
VCOL
Voltage range on COL pins
-0.3 to +6
V
Voltage level range on logic input pins
-0.3 to +6
VIN
IOUT
IR
Output current (continuous)
Reverse output current (per channel)
Internally limited
V
(1)
A
-5
A
IGND
DC ground reverse current
-250
mA
IREG
VREG input current
-1/10
mA
Current range on pins TWARN , FAULT , PG
-1 to +10
mA
Input current range
-1 to +10
mA
Current range on ROW pins (ROW in ON-state)
+20
mA
Current range on ROW pins (ROW in OFF-state)
-1 to +10
mA
Current range on COL pins (COL in ON-state)
-10
mA
Current range on COL pins (COL in OFF-state)
-1 to +10
mA
VESD
Electrostatic discharge (R = 1.5 kΩ; C = 100 pF)
2000
V
EAS
Single pulse avalanche energy per channel not
simultaneously @Tamb = 125 °, IOUT = 0.5 A
3
J
PTOT
Power dissipation at TC = 25 °C
TJ
Junction operating temperature
IFAULT
ITWARN,
IPG
IIN
IROW
ICOL
TSTG
Storage temperature
Internally limited
(1)
W
Internally limited
°C
-55 to 150
°C
Notes:
(1)
Protection functions are intended to avoid IC damage in fault conditions and are not intended for continuous
operation. Continuous and repetitive operation of protection functions may reduce the IC lifetime.
10/43
DocID027849 Rev 3
VNI8200XP-32
Maximum ratings
Table 4: Thermal data
Symbol
Rth(JC)
Rth(JA)
Parameter
Thermal resistance junction-case
(1)
Thermal resistance junction-ambient
(2)
Value
Unit
Max.
2
°C/W
Max.
15
°C/W
Notes:
(1)
(2)
Per channel.
2
PowerSSO-36 mounted on a four-layer FR4, with 8 cm for each layer, Cu thickness = 35 µm
DocID027849 Rev 3
11/43
Electrical characteristics
VNI8200XP-32
5
Electrical characteristics
5.1
Power section
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified
Table 5: Power section
Symbol
Parameter
VCC
Supply voltage
VCC
clamp
Clamp on VCC
RDS(on)
On-state
resistance
Test conditions
Min.
Typ.
10.5
Current 20 mA
45
IOUT = 0.5 A at TJ = 25 °C
50
IS
VCC supply
current
IDS
VREG supply
current
V
52
V
Ω
0.65
1
1.1
5.3
3.5
mA
mA
5.2
mA
DC-DC OFF VREG = 5 V SPI
OFF WD_EN = 0
200
µA
DC/DC OFF VREG = 5 V SPI
ON WD_EN = VREG
250
µA
ILGND
Output current at
GND
disconnection
All pins at 0 V except
VOUT = 24 V
0.5
mA
VOUT(OFF)
OFF-state output
voltage
VIN = 0 V, IOUT = 0 A
1
V
IOUT(OFF)
OFF-state output
current
VIN = VOUT = 0 V
2
µA
Charge pump
frequency
Channel in ON-state
FCP
0
(4)
Notes:
(1)
SS signal high, no communication.
(2)
SS signal low, communication ON.
(3)
SS signal low, communication ON.
(4)
12/43
36
0.2
All channels in ON-state,
DC-DC in ON-state VREG = 5
(2)
V, SPI ON
All channels in ON-state,
DC-DC in OFF-state
(3)
VREG = 5 V, SPI ON
Unit
0.11
IOUT = 0.5 A at TJ = 125 °C
All channels in OFF-state,
DC-DC in OFF-state,
(1)
VREG=5 V, SPI OFF
Max.
To cover EN55022 class A and class B normative.
DocID027849 Rev 3
1.45
MHz
VNI8200XP-32
5.2
Electrical characteristics
SPI characteristics
10.5 V < VCC < 36 V; 2.7 V < VREG < 5 V; -40 TCSD) and is released
when this condition is removed (T C < TCR).
9.9
Fault indication
The FAULT pin is an open drain active low fault indication pin. This pin is activated by
one or more of the following conditions:
Channel overtemperature (OVT)
This pin is activated when at least one of the channels is in junction overtemperature.
Unlike the SPI fault detection bits, this signal is not latched: the FAULT pin is low only
when the fault condition is active and is released if the input driving signal is OFF or after
the OVT protection condition has been removed. This last event occurs if the channel
temperature decreases below the threshold level and the case temperature has not
exceeded TCSD or is below TCR. This means that the FAULT pin is low only while the
junction overtemperature is active (T J > TTSD) and is released after this condition has
been removed (TJ < TR and TC < TCR).
Parity check fail
When SPI mode is used (SEL2 = H), if a parity check fault of the incoming SPI frame is
detected or counted, CLK rising edges are different by a multiple of 8, the FAULT pin is
22/43
DocID027849 Rev 3
VNI8200XP-32
Pin function description
kept low. When counted CLK rising edges are a multiple of 8 and parity check is valid, the
FAULT pin is kept high.
9.10
Power Good ( PG )
The PG terminal is an open drain, which indicates the status of the supply voltage. When
VCC supply voltage reaches the Vsth1 threshold, PG goes into a high impedance state. It
goes into a low impedance state when VCC falls below the Vsth2 threshold.
In 16-bit SPI mode, a PG bit is also available. This bit is set high when the Power Good
diagnostic is active, it is otherwise cleared.
Figure 7: Power Good diagnostic
PG
VPGH2
Vcc
VPGH1
GIPG030420151221LM
9.11
Programmable watchdog counter reset (WD)
If SEL2 = H, the VNI8200XP-32 embeds a watchdog counter that must be erased, with a
negative pulse on the WD pin, before it expires. If the WD counter elapses, the
VNI8200XP-32 goes into an internal reset state where all the outputs are disabled; to
restart normal operation a negative pulse must be applied to the WD pin.
The watchdog enable/disable pin should be connected through an external divider to V REG.
The watchdog time is fixed in the following table:
Table 14: Programmable watchdog time
VWD_EN
tWM
0.25 VREG > VWD_EN
Disable
0.25 VREG ≤ VWD_EN < 0.5 VREG
40 ± 25% ms
0.25 VREG ≤ VWD_EN < 0.75 VREG
80 ± 25% ms
0.75 VREG ≤ VWD_EN = VREG
160 ± 25% ms
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Pin function description
VNI8200XP-32
Figure 8: Watchdog reset
24/43
DocID027849 Rev 3
VNI8200XP-32
SPI operation (SEL2 = H)
10
SPI operation (SEL2 = H)
10.1
8-bit SPI mode (SEL1 = L)
If SEL2 = H, the 8-bit SPI mode is based on an 8-bit command frame sent from the
microcontroller to the IC; each bit directly drives the corresponding output where LSB
drives output 0 and MSB drives output 7. Each bit, set to ‘1’, activates (closes) the
corresponding output.
At the same time, the IC transfers the channel fault conditions (OVT) to the microcontroller.
These fault conditions are latched at the occurrence and cleared after each communication
(each time the SS signal has a positive transition). Each bit, set to ‘1’, indicates an OVT
condition for the corresponding channel.
Table 15: Command 8-bit frame (master-to-slave)
MSB
IN7
LSB
IN6
IN5
IN4
IN3
IN2
IN1
IN0
Table 16: Fault 8-bit frame (slave-to-master)
MSB
F7
10.2
LSB
F6
F5
F4
F3
F2
F1
F0
16-bit SPI mode (SEL1 = H)
The 16-bit SPI mode is based on a 16-bit command frame sent from the microcontroller to
the IC; the first 8 bits directly drive the output channels (each bit, set to ‘1’, activates the
corresponding output), the other 8 bits contain a 4-bit parity check code where the last bit
(the inversion of the previous one) is used to detect a communication error condition
(providing at least a transition in each frame):
P0 = IN0 +IN1+ IN2 +IN3 +IN4+ IN5+ IN6 +IN7
P1 = IN1 + IN3 + IN5 + IN7
P2 = IN0 + IN2 + IN4 + IN6
nP0 = not P0
Table 17: Command 16-bit frame (master-to-slave)
MSB
IN7
LSB
IN6
IN5
IN4
IN3
IN2
IN1
IN0
P2
P1
P0
At the same time, the IC transfers to the microcontroller a 16-bit fault frame where the first
8 bits indicate a channel fault (OVT) condition (each bit, set to ‘1’, indicates an OVT event),
the following 4 bits provide general fault condition information. FB_OK: this bit is related to
the DC-DC regulation: at the DC-DC turn-on, this bit is low and becomes high after FB
rises above 90% of the nominal VFB voltage and a correct SPI communication occurred. If
the FB voltage falls below 80% of the nominal VFB voltage, this bit is zero; TWARN (IC
warning case temperature), PC (parity check fail, the bit, set to ‘1’, indicates a PC fail or the
length is not a multiple of 8) and PG (Power Good, see Section 9.10: "Power Good
DocID027849 Rev 3
25/43
nP0
SPI operation (SEL2 = H)
VNI8200XP-32
(PG)"). The last 4 bits are used as parity check bits and communication error condition (see
command 16-bit frame):
P0 = F0+ F1+ F2 + F3 + F4 + F5 + F6 + F7
P1 = PC+ FB_OK + F1 + F3 + F5 + F7
P2 = PG + TWARN + F0 + F2 + F4 + F6
nP0 = not P0
Table 18: Fault 16-bit frame (slave-to-master)
MSB
F7
LSB
F6
F5
F4
F3
F2
F1
F0
FB_OK
TWARN
PC
PG
Channel indications are latched and cleared after a communication only.
26/43
DocID027849 Rev 3
P2
P1
P0
nP0
VNI8200XP-32
11
LED driving array
LED driving array
The LED driving array carries out the status of the output channels (ON or OFF).
Figure 9: LED driving array
The following equation is an indication how to choose the Rext resistor value:
Rext= (VCOLmin.) - (VROWmax.)- VF(LED) / IF(LED)
where IF(LED) ≤ 7 mA and (VCOL min.) and (VROW max.) can be found in Table 11: "LED
driving array" and VF(LED) and IF(LED) depend on the electrical characteristics of the LEDs.
DocID027849 Rev 3
27/43
Step-down switching regulator
12
VNI8200XP-32
Step-down switching regulator
The IC embeds a high efficiency 100 mA micropower step-down switching regulator. The
regulator is protected against short-circuit or overload conditions. Pulse-by-pulse current
limit regulation is obtained in normal operation through a current loop control.
A low ESR output capacitor connected to the VREG pin helps to limit the regulated voltage
ripple; a low ESR (less than 10 mΩ) capacitor is preferable. The control loop pin FB allows
3.3 V to be regulated, connecting it directly to VREG, or 5 V connecting it through a voltage
divider Rl/Rfbl. The DC-DC converter can be turned off by connecting the feedback pin to
the DCVDD pin. In some applications it is possible to supply a 5 V or 3.3 V voltage
externally or, in the case of two or more VNI8200XP-32 inside the same board, it's possible
to configure the DC-DC converter on only one device and also supply the other ICs.
if the DC-DC converter is adjusted to provide 3.3 V regulation and the VDC_out is used to
power an external load and not the device, a 33 kΩ resistor has to be connected on V DC_out
pin.
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Typical circuits and conventions
Typical circuits and conventions
Figure 10: Typical circuit for switching regulation VDC-out = 3.3 V
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Typical circuits and conventions
VNI8200XP-32
Figure 11: Typical circuit for switching regulation VDC-out = 5 V
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Typical circuits and conventions
Figure 12: SPI directional logic convention
SDI
VREG
SS
CLK
OUT1
OUT2
SDO
OUT3
OUT4
WD
OUT_EN
WD_EN
TAB=Vcc
OUT5
OUT6
SEL1
OUT7
SEL2
OUT8
PG
FAULT
TWARN
GND
GIPG030420151337LM
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Thermal management
14
VNI8200XP-32
Thermal management
The power dissipation in the IC is the main factor that sets the safe operating condition of
the device in the application. Therefore, it must be taken into account very carefully.
Heatsinking can be achieved using copper on the PCB with proper area and thickness. The
following image shows the junction-to-ambient thermal impedance values for the
PowerSSO-36 package.
Figure 13: PowerSSO-36 thermal impedance vs. time
For instance, three cases have been considered using a PowerSSO-36 packaged with
copper slug soldered on a 1.6 mm thickness FR4 board with dissipating footprint (copper
thickness of 70 µm):
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single layer PCB with just IC footprint dissipating area
2
double layer PCB with footprint dissipating area on the top side and a 2 cm
dissipating layer on the bottom side through 15 via holes
2
double layer PCB with footprint dissipating area on the top side and an 8 cm
dissipating layer on the bottom side through 15 via holes
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14.1
Thermal management
Thermal behavior
Figure 14: Thermal behavior
1 Thermal shutdown
2 Junction hysteresis
3 Restore to idle condition
4 Case hysteresis
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Interface timing diagram
15
VNI8200XP-32
Interface timing diagram
Figure 15: Serial timing
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Switching parameter test conditions
Switching parameter test conditions
Figure 16: dV/dt(ON) and dV/dt(OFF) time diagram test conditions
Figure 17: td(ON) and td(OFF) time diagram test conditions
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Package information
17
VNI8200XP-32
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
17.1
PowerSSO-36 package information
Figure 18: PowerSSO-36 package outline
7587131 rev9
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Package information
Figure 19: PowerSSO-36 package outline details
Not in scale (section A-A)
Figure 20: PowerSSO-36 package outline details (section B-B)
Not in scale (section B-B)
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Package information
VNI8200XP-32
Table 19: PowerSSO-36 mechanical data
mm
Dim.
Min.
Typ.
ɵ
0°
8°
ɵ1
5°
10°
ɵ2
0°
A
2.15
2.45
A1
0.00
0.10
A2
2.15
2.35
b
0.18
0.32
b1
0.13
c
0.23
c1
0.20
0.25
D1
0.20
0.30
10.30 BSC
7.00
7.40
D2
3.65
D3
4.30
e
0.50 BSC
E
10.30 BSC
E1
7.50 BSC
E2
0.30
0.32
D
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Max.
4.20
4.60
E3
2.30
E4
2.90
G1
1.20
G2
1.00
G3
0.80
h
0.30
L
0.60
0.40
0.70
L1
1.40 REF
L2
0.25 BSC
N
36
R
0.30
R1
0.20
S
0.25
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0.85
VNI8200XP-32
17.2
Package information
Packing information
Figure 21: PowerSSO-36 tube shipment outline
Table 20: PowerSSO-36 tube shipment mechanical data
Description
Value
Base quantity
49
Bulk quantity
1225
Tube lenght (± 0.5)
532
A
3.5
B
13.8
C (± 0.1)
0.6
All dimensions are in mm
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Package information
VNI8200XP-32
Figure 22: PowerSSO-36 tape dimension outline
Table 21: PowerSSO-36 tape dimension mechanical data
Description
Dimensions
Value
Tape width
W
24
Tape hole spacing
P0 (± 0.1)
4
Component spacing
P
12
Hole diameter
D (± 0.05)
1.55
Hole diameter
D1 (min.)
1.5
Hole position
F (± 0.1)
11.5
Compartment depth
K (max.)
2.85
Hole spacing
P1 (± 0.1)
2
According to the Electronic Industries Association (EIA) standard 481 rev. A, Feb
1986
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Package information
Figure 23: PowerSSO-36 reel shipment outline
Table 22: PowerSSO-36 reel dimension mechanical data
Description
Value
Base quantity
1000
Bulk quantity
1000
A max.
330
B min.
1.5
C (± 0.2)
13
F
20.2
G (2 ± 0)
24.4
N min.
100
T min.
30.4
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Revision history
18
VNI8200XP-32
Revision history
Table 23: Document revision history
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Date
Revision
Changes
08-May-2015
1
Initial release.
09-Jun-2015
2
Updated VCC supply current parameter in table 5 and
updated VPGH1, VPGH2, VUSD, IPEAK, ILIM and Hyst
parameters in table 9.
24-Aug-2015
3
Updated programmable watchdog time table.
Datasheet status promoted from preliminary data to
production data.
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