VNL5030J-E
VNL5030S5-E
OMNIFET III
fully protected low-side driver
Datasheet - production data
Description
PowerSSO-12
The VNL5030J-E and VNL5030S5-E are
monolithic devices made using
STMicroelectronics® VIPower® technology,
intended for driving resistive or inductive loads
with one side connected to the battery. Built-in
thermal shutdown protects the chip from
overtemperature and short-circuit. Output current
limitation protects the devices in an overload
condition. In case of long duration overload, the
device limits the dissipated power to a safe level
up to thermal shutdown intervention.Thermal
shutdown, with automatic restart, allows the
device to recover normal operation as soon as a
fault condition disappears. Fast demagnetization
of inductive loads is achieved at turn-off.
SO-8
Features
Type
Vclamp
RDS(on)
ID
41 V
30 mΩ
25 A
VNL5030J-E
VNL5030S5-E
• Automotive qualified
• Drain current: 25 A
• ESD protection
• Overvoltage clamp
• Thermal shutdown
• Current and power limitation
• Very low standby current
• Very low electromagnetic susceptibility
• Compliant with European directive 2002/95/EC
• Open drain status output
Table 1. Devices summary
Order codes
Package
Tube
Tape and reel
PowerSSO-12
VNL5030J-E
VNL5030JTR-E
SO-8
VNL5030S5-E
VNL5030S5TR-E
November 2013
This is information on a product in full production.
DocID022767 Rev 6
1/28
www.st.com
Contents
VNL5030J-E/ VNL5030S5-E
Contents
1
Block diagrams and pins configurations . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
4
5
6
2/28
MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2
SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4
PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5
SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DocID022767 Rev 6
VNL5030J-E/ VNL5030S5-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Devices summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PowerMOS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Source drain diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PowerSSO-12 thermal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SO-8 thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DocID022767 Rev 6
3/28
3
List of figures
VNL5030J-E/ VNL5030S5-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
4/28
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagrams (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Source diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Static drain source on-resistance vs. drain current (VIN = 3.5 V) . . . . . . . . . . . . . . . . . . . . 11
Static drain source on-resistance vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Static drain source on-resistance vs. drain current (VIN = 5 V). . . . . . . . . . . . . . . . . . . . . . 11
Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transfer characteristics (inside view for VIN = 2 V to 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output characteristics (Tcase = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
On-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PowerSSO-12 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . 16
PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 17
Thermal fitting model of a LSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SO-8 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . 19
SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Thermal fitting model of a LSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DocID022767 Rev 6
VNL5030J-E/ VNL5030S5-E
1
Block diagrams and pins configurations
Block diagrams and pins configurations
Figure 1. Block diagram
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Table 2. Pin function
Name
Function
INPUT
Voltage controlled input pin with hysteresis, CMOS compatible; it controls output
switch state.
DRAIN
PowerMOS drain.
SOURCE
PowerMOS source and ground reference for the control section.
SUPPLY
Supply voltage connected to the signal part (5 V).
STATUS
Open drain digital diagnostic pin.
TAB
Exposed pad. PowerMOS drain.
DocID022767 Rev 6
5/28
27
Block diagrams and pins configurations
VNL5030J-E/ VNL5030S5-E
Figure 2. Current and voltage conventions
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Table 3. Suggested connections for unused and N.C. pins
Connection / pin
Status
N.C.
Input
Floating
X(1)
X
X
To ground
Not allowed
X
Through 10 kΩ resistor
1. X: do not care.
6/28
DocID022767 Rev 6
VNL5030J-E/ VNL5030S5-E
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 4 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 4. Absolute maximum ratings
Value
Symbol
Parameter
Unit
PowerSSO-12
VDS
Internally clamped
V
Internally limited
A
30
A
ID
DC drain current
-ID
Reverse DC drain current
IS
DC supply current
-1 to 10
mA
IIN
DC input current
-1 to 10
mA
ISTAT
DC status current
-1 to 10
mA
VESD1
Electrostatic discharge
(R = 1.5 kΩ; C = 100 pF)
– DRAIN
– SUPPLY, INPUT, STATUS
VESD2
Electrostatic discharge on output pin only
(R = 330 Ω, C = 150 pF)
V
5000
4000
2000
V
Junction operating temperature
-40 to 150
°C
Tstg
Storage temperature
-55 to 150
°C
EAS
Single pulse avalanche energy
(L = 1.16 mH, Tj = 150 °C, RL = 0, IOUT = IlimL)
184
mJ
Tj
2.2
Drain-source voltage (VIN = 0 V)
SO-8
Thermal data
Table 5. Thermal data
Maximum value
Symbol
Parameter
Rthj-amb Thermal resistance junction-ambient
DocID022767 Rev 6
Unit
PowerSSO-12
SO-8
61
101
°C/W
7/28
27
Electrical specifications
2.3
VNL5030J-E/ VNL5030S5-E
Electrical characteristics
Values specified in this section are for VSUPPLY = VIN = 4.5 V to 5.5 V, -40°C < Tj < 150°C,
unless otherwise stated.
Table 6. PowerMOS section
Symbol
Parameter
Test conditions
VSUPPLY Operating supply voltage
RON
ON-state resistance
Min.
Typ.
Max.
Unit
3.5
5
5.5
V
ID = 2.8 A; Tj = 25°C;
VSUPPLY = VIN = 5 V
30
ID = 2.8 A; Tj = 150°C;
VSUPPLY = VIN = 5 V
60
mΩ
VCLAMP
Drain-source clamp
voltage
VIN = 0 V; ID = 2.8 A
41
VCLTH
Drain-source clamp
threshold voltage
VIN = 0 V; ID = 2 mA
36
VIN = 0 V; VDS = 13 V;
Tj = 25°C
0
VIN = 0 V; VDS = 13 V;
Tj = 125°C
0
IDSS
OFF-state output current
46
52
V
V
3
µA
5
Table 7. Source drain diode
Symbol
VSD
Parameter
Test conditions
Forward on voltage
ID = 2.8 A; VIN = 0 V
Min.
Typ.
Max.
Unit
—
0.8
—
V
Max.
Unit
Table 8. Status pin
Symbol
Parameter
Test conditions
Min.
Typ.
VSTAT
Status low output voltage
ISTAT = 1 mA
0.5
V
ILSTAT
Status leakage current
Normal operation; VSTAT = 5 V
10
µA
CSTAT
Status pin input
capacitance
Normal operation; VSTAT = 5 V
100
pF
VSTCL
Status clamp voltage
ISTAT = 1 mA
5.5
7
V
ISTAT = -1 mA
-0.7
Table 9. Logic input
Symbol
8/28
Parameter
Test conditions
VIL
Low-level input voltage
IIL
Low-level input current
VIH
High-level input voltage
IIH
High-level input current
VI(hyst)
Input hysteresis voltage
VIN = 0.9 V
Min.
Max.
Unit
0.9
V
1
µA
2.1
V
VIN = 2.1 V
DocID022767 Rev 6
Typ.
10
0.13
µA
V
VNL5030J-E/ VNL5030S5-E
Electrical specifications
Table 9. Logic input (continued)
Symbol
VICL
Parameter
Test conditions
Min.
IIN = 1 mA
Input clamp voltage
Typ.
5.5
Max.
Unit
7
V
IIN = -1 mA
-0.7
Table 10. Open-load detection
Symbol
VOl
td(oloff)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0.6
1.2
1.7
V
45
425
1100
µs
Min.
Typ.
Max.
Unit
OFF-state; Tj = 25°C;
VIN = VDRAIN = 0 V;
10
25
ON-state; VIN = 5 V; VDS = 0 V
25
65
Open-load OFF-state voltage
detection threshold
VIN = 0 V
Delay between INPUT falling
edge and STATUS falling edge IOUT = 0 A
in openload condition
Table 11. Supply section
Symbol
IS
VSCL
Parameter
Test conditions
Supply current
Supply clamp voltage
µA
ISCL = 1 mA
5.5
7
V
ISCL = -1 mA
-0.7
Table 12. Switching characteristics(1)
PowerSSO-12
Symbol
Parameter
SO-8
Test conditions
Unit
Min.
Typ.
Max
Min.
Typ.
Max.
td(ON)
Turn-on delay
time
RL = 4.5 Ω;
VCC = 13 V(2)
—
7.6
—
—
7.6
—
µs
td(OFF)
Turn-off delay
time
RL = 4.5 Ω;
VCC = 13 V(2)
—
18.8
—
—
18.8
—
µs
tr
Rise time
RL = 4.5 Ω;
VCC = 13 V(2)
—
8
—
—
8
—
µs
tf
Fall time
RL = 4.5 Ω;
VCC = 13 V(2)
—
9
—
—
9
—
µs
WON
Switching energy
losses at turn-on
RL = 4.5 Ω;
VCC = 13 V(2)
—
0.068
—
—
0.068
—
mJ
WOFF
Switching energy
losses at turn-off
RL = 4.5 Ω;
VCC = 13 V(2)
—
0.077
—
—
0.077
—
mJ
Qg
Total gate charge
VSUPPLY = VIN = 5
V
—
6
—
—
6
—
nC
1. See Figure 14: Application schematic.
2. See Figure 13: Switching characteristics.
DocID022767 Rev 6
9/28
27
Electrical specifications
VNL5030J-E/ VNL5030S5-E
Table 13. Protection and diagnostics
Symbol
Parameter
IlimH
DC short-circuit current
VDS = 13 V;
VSUPPLY = VIN = 5 V
IlimL
Short-circuit current
during thermal cycling
VDS = 13 V; TR < Tj < TTSD;
VSUPPLY = VIN = 5 V
15
A
tdlimL
Step response current
limit
VDS = 13 V; Vinput = 5 V
44
µs
TTSD
Shutdown temperature
TR
Reset temperature
TRS
Thermal reset of
STATUS
THYST
10/28
Test conditions
Min.
Typ.
Max.
Unit
25
35
49
A
150
175
TRS + 1 TRS + 5
135
Thermal hysteresis
(TTSD - TR)
°C
°C
°C
7
DocID022767 Rev 6
200
°C
VNL5030J-E/ VNL5030S5-E
2.4
Electrical specifications
Electrical characteristics curves
Figure 4. Source diode forward characteristics Figure 5.
Static drain source on-resistance
vs. drain current (VIN = 3.5 V)
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Figure 6. Static drain source on-resistance vs. Figure 7.
input voltage
Static drain source on-resistance
vs. drain current (VIN = 5 V)
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DocID022767 Rev 6
("1($'5
11/28
27
Electrical specifications
VNL5030J-E/ VNL5030S5-E
Figure 8. Transfer characteristics
Figure 9.
Transfer characteristics (inside
view for VIN = 2 V to 3 V)
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Figure 10. Output characteristics (Tcase = 25°C) Figure 11. On-resistance vs. temperature
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Figure 12. Input threshold vs. temperature
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DocID022767 Rev 6
("1($'5
VNL5030J-E/ VNL5030S5-E
Electrical specifications
Table 14. Truth table
Conditions
INPUT
DRAIN
STATUS
Normal operation
L
H
H
L
H
H
Current limitation
L
H
H
X
H
H
Overtemperature
L
H
H
H
H
L
Undervoltage
L
H
H
H
X
X
Output voltage < VOL
L
H
L
L
L
H
Figure 13. Switching characteristics
DocID022767 Rev 6
13/28
27
Application information
3
VNL5030J-E/ VNL5030S5-E
Application information
Figure 14. Application schematic
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3.1
MCU I/O protection
ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from
latching up(a). The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the LSD I/Os (input levels compatibility) with the
latch-up limit of microcontroller I/Os:
Equation 1
( V OHμC – V IH )
0.7
-------------------- ≤ R prot ≤ ---------------------------------------I latchup
I IH max
Let:
•
Ilatchup > 20 mA
•
VOHµC > 4.5 V
•
35 Ω ≤ Rprot ≤ 100 KΩ
a. In case of negative transient on the drain pin.
14/28
DocID022767 Rev 6
VNL5030J-E/ VNL5030S5-E
Application information
Then, the recommended value is Rprot = 1 KΩ
Figure 15 shows the turn-off current drawn during the demagnetization.
Figure 15. Maximum demagnetization energy (VCC = 13.5 V)
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DocID022767 Rev 6
15/28
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Package and PC board thermal data
VNL5030J-E/ VNL5030S5-E
4
Package and PC board thermal data
4.1
PowerSSO-12 thermal data
Figure 16. PowerSSO-12 PC board
("1($'5
1. Layout condition of Rth and Zth measurements (board finish thickness 1.6 mm +/- 10%; board double
layer; board dimension 77x86; board material FR4; Cu thickness 0.070mm (front and back side); thermal
vias separation 1.2 mm; thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm;
footprint dimension 4.1 mm x 6.5 mm).
Figure 17. PowerSSO-12 Rthj-amb vs PCB copper area in open box free air condition
57+MDPE
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16/28
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VNL5030J-E/ VNL5030S5-E
Package and PC board thermal data
Figure 18. PowerSSO-12 thermal impedance junction ambient single pulse
=7+ &:
&XIRRWSULQW
&X FP
&X FP
7LPH V
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Equation 2: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
Figure 19. Thermal fitting model of a LSD in PowerSSO-12
GAPGCFT00533
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
DocID022767 Rev 6
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27
Package and PC board thermal data
VNL5030J-E/ VNL5030S5-E
Table 15. PowerSSO-12 thermal parameters
18/28
Area/island (cm2)
Footprint
R1 (°C/W)
0.7
R2 (°C/W)
1.2
R3 (°C/W)
3
R4 (°C/W)
2
8
8
8
7
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1 (W.s/°C)
0.001
C2 (W.s/°C)
0.005
C3 (W.s/°C)
0.08
C4 (W.s/°C)
0.1
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
DocID022767 Rev 6
VNL5030J-E/ VNL5030S5-E
SO-8 thermal data
Figure 20. SO-8 PC board
GAPGCFT00534
1. Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm,
Cu thickness = 35 µm (front and back side), Copper areas: from minimum pad lay-out to 2 cm2).
Figure 21. SO-8 Rthj-amb vs PCB copper area in open box free air condition
57+MDPE
IRRWSULQW
24 (J?A MB &:
4.2
Package and PC board thermal data
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DocID022767 Rev 6
19/28
27
Package and PC board thermal data
VNL5030J-E/ VNL5030S5-E
Figure 22. SO-8 thermal impedance junction ambient single pulse
=7+ &:
&X IRRWSULQW
&X FP
7LPH V
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Equation 3: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
Figure 23. Thermal fitting model of a LSD in SO-8
GAPGCFT00533
1. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
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VNL5030J-E/ VNL5030S5-E
Package and PC board thermal data
Table 16. SO-8 thermal parameters
Area/island (cm2)
Footprint
R1 (°C/W)
0.3
R2 (°C/W)
2.2
R3 (°C/W)
3.5
R4 (°C/W)
21
R5 (°C/W)
16
R6 (°C/W)
58
C1 (W.s/°C)
0.0001
C2 (W.s/°C)
0.002
C3 (W.s/°C)
0.0075
C4 (W.s/°C)
0.045
C5 (W.s/°C)
0.35
C6 (W.s/°C)
1.05
DocID022767 Rev 6
2
28
2
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Package and packing information
VNL5030J-E/ VNL5030S5-E
5
Package and packing information
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSSO-12 mechanical data
Figure 24. PowerSSO-12 package dimensions
("1($'5
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VNL5030J-E/ VNL5030S5-E
Package and packing information
Table 17. PowerSSO-12 mechanical data
mm.
inch
DIM.
Min.
Typ.
Min.
Typ.
A
1.25
1.62
A
1.25
A1
0
0.1
A1
0
A2
1.10
1.65
A2
1.10
B
0.23
0.41
B
0.23
C
0.19
0.25
C
0.19
D
4.8
5.0
D
4.8
E
3.8
4.0
E
3.8
e
0.8
e
Max.
0.8
H
5.8
6.2
H
5.8
h
0.25
0.5
h
0.25
L
0.4
1.27
L
0.4
k
0°
8°
k
0°
X
1.9
2.5
X
1.9
Y
3.6
4.2
Y
3.6
0.1
ddd
ddd
5.3
Max.
SO-8 mechanical data
Figure 25. SO-8 package dimensions
GAPGCFT00145
DocID022767 Rev 6
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27
Package and packing information
VNL5030J-E/ VNL5030S5-E
Table 18. SO-8 mechanical data
Millimeters
Symbol
Min.
Typ.
A
Max.
1.75
A1
0.10
A2
1.25
b
0.28
0.48
c
0.17
0.23
D(1)
4.80
4.90
5.00
E
5.80
6.00
6.20
E1(2)
3.80
3.90
4.00
e
0.25
1.27
h
0.25
0.50
L
0.40
1.27
L1
k
1.04
0°
ccc
8°
0.10
1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15 mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
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VNL5030J-E/ VNL5030S5-E
5.4
Package and packing information
PowerSSO-12 packing information
The devices can be packed in tube or tape and reel shipments (see the Table 1: Devices
summary).
Figure 26. PowerSSO-12 tube shipment (no suffix)
B
C
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
GA P GC FT000123
Figure 27. PowerSSO-12 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
DocID022767 Rev 6
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27
Package and packing information
5.5
VNL5030J-E/ VNL5030S5-E
SO-8 packing information
Figure 28. SO-8 tube shipment (no suffix)
%
&
$
("1($'5
Base q.ty
Bulk q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
100
2000
532
3.2
6
0.6
All dimensions are in mm.
Figure 29. SO-8 tape and reel shipment (suffix “TR”)
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VNL5030J-E/ VNL5030S5-E
6
Revision history
Revision history
Table 19. Document revision history
Date
Revision
14-Feb-2012
1
Initial release.
14-Jun-2012
2
Updated Table 2: Pin function
Updated Figure 3: Configuration diagrams (top view)
Table 12: Switching characteristics:
– Qg: added row
14-Sep-2012
3
Table 4: Absolute maximum ratings:
– -ID, IS, ISTAT: updated values
Updated Table 5: Thermal data and Table 12: Switching characteristics
15-May-2013
4
Removed Table: Input section.
Updated Figure 14: Application schematic
Updated Section 3.1: MCU I/O protection
18-Sep-2013
5
Updated disclaimer.
6
Updated Features list
Added Section 2.4: Electrical characteristics curves
Table 11: Supply section:
– IS: updated max value
Updated Figure 15: Maximum demagnetization energy (VCC = 13.5 V)
21-Nov-2013
Changes
DocID022767 Rev 6
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VNL5030J-E/ VNL5030S5-E
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