VNLD5090-E

VNLD5090-E OMNIFET III fully protected low-side driver for automotive applications Datasheet - production data Description SO-8 Features Type Vclamp RDS(on) ID VNLD5090-E 41 V 90 m 25 A The VNLD5090-E is a monolithic device made using STMicroelectronics® VIPower® technology, intended for driving resistive or inductive loads with one side connected to the battery. Built-in thermal shutdown protects the chip from overtemperature and short-circuit. Output current limitation protects the device in an overload condition. In case of long duration overload, the device limits the dissipated power to a safe level up to thermal shutdown intervention.Thermal shutdown, with automatic restart, allows the device to recover normal operation as soon as a fault condition disappears. Fast demagnetization of inductive loads is achieved at turn-off.  AEC-Q100 qualified  Drain current: 13 A  ESD protection  Overvoltage clamp  Thermal shutdown  Current and power limitation  Very low standby current  Very low electromagnetic susceptibility  In compliance with the 2002/95/EC European directive Table 1. Devices summary Order codes Package SO-8 October 2017 This is information on a product in full production. Tube Tape and reel VNLD5090-E VNLD5090TR-E DocID023206 Rev 5 1/20 www.st.com Contents VNLD5090-E Contents 1 Block diagrams and pins configurations . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 5 6 2/20 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DocID023206 Rev 5 VNLD5090-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Devices summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and n.c. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PowerMOS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Source drain diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SO-8 thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DocID023206 Rev 5 3/20 3 List of figures VNLD5090-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. 4/20 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Configuration diagrams (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Maximum demagnetization energy (VCC = 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SO-8 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . 13 SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal fitting model of a LSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DocID023206 Rev 5 VNLD5090-E 1 Block diagrams and pins configurations Block diagrams and pins configurations Figure 1. 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DI ,/')# /&&3TATE /PENLOAD #URRENT ,IMITATION 0OWER #LAMP ).63500,9 ).63500,9 $2)6%2 /6%24%-0%2!452% 02/4%#4)/. 34!453 34!453 /6%2,/!$02/4%#4)/. !#4)6%0/7%2,)-)4!4)/. 3/52#% 3/52#% ("1($'5 Table 2. Pin function Name IN1,2/VSUPPLY1,2 DRAIN1,2 Function Voltage controlled input pin with hysteresis, CMOS compatible. They controls output switch state PowerMOS drain SOURCE1,2 PowerMOS source and ground reference for the control section STATUS1,2 Open drain digital diagnostic pin DocID023206 Rev 5 5/20 19 Block diagrams and pins configurations VNLD5090-E Figure 2. Current and voltage conventions *% 7%4 %3"*/  **/ 7*/ *45"5 */ 74611-:  45"564   745"5 4063$&  ("1($'5 Figure 3. Configuration diagrams (top view) 3/52#% $2!). 3/52#% $2!).         34!453 ).63500,9 34!453 ).63500,9 3/  '!0'#&4 Table 3. Suggested connections for unused and n.c. pins Connection / pin STATUS1,2 N.C. INPUT1,2 Floating X(1) X X To ground Not allowed X Through 10 kresistor 1. X: do not care. 6/20 DocID023206 Rev 5 VNLD5090-E Electical specifications 2 Electical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in the Table 4 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Absolute maximum ratings Value Symbol Parameter Unit SO-8 VDS Internally clamped V Internally limited A 12.5 A ID DC drain current -ID Reverse DC drain current IS DC supply current -1 to 10 mA IIN DC input current -1 to 10 mA ISTAT DC status current -1 to 10 mA VESD1 Electrostatic discharge (R = 1.5 k; C = 100 pF) – DRAIN – SUPPLY, INPUT, STATUS VESD2 Electrostatic discharge on output pin only (R = 330 , C = 150 pF) 5000 4000 V 2000 V Junction operating temperature -40 to 150 °C Tstg Storage temperature -55 to 150 °C EAS Single pulse avalanche energy (L = 1.1 mH; Tj = 150 °C; RL = 0; IOUT = IlimL) 50 mJ Tj 2.2 Drain-source voltage (VIN = 0 V) Thermal data Table 5. Thermal data Maximum value Symbol Parameter Unit SO-8 Rthj-amb Thermal resistance junction-ambient DocID023206 Rev 5 108 °C/W 7/20 19 Electical specifications 2.3 VNLD5090-E Electrical characteristics Values specified in this section are for VINx/SUPPLYx = 4.5 V to 5.5 V, -40°C < Tj < 150°C, unless otherwise stated. Table 6. PowerMOS section Symbol RON Parameter Test conditions ON-state resistance Min. IDSS Drain-source clamp threshold voltage OFF-state output current Max. ID = 1.6 A; Tj = 25°C, VINx/SUPPLYx = 5 V 90 ID = 1.6 A; Tj = 150°C, VINx/SUPPLYx = 5 V 180 ID = 1.6 A; Tj = 150°C, VINx/SUPPLYx = 4.5 V 190 VCLAMP Drain-source clamp voltage VIN = 5 V; ID = 1.6 A VCLTH Typ. 41 VIN = 0 V; ID = 2 mA 36 VIN = 0 V; VDS = 13 V; Tj = 25°C 0 VIN = 0 V; VDS = 13 V; Tj = 125°C 0 46 52 Unit m V V 3 μA 5 Table 7. Source drain diode Symbol VSD Parameter Test conditions Forward on voltage ID = 1.6 A; VIN = 0 V Min. Typ. Max. Unit — 0.8 — V Table 8. Input section Symbol IISS VICL VINTH Parameter Test conditions Supply current from input pin Min. Typ. Max. ON-state: VINx/SUPPLYx = 5 V; VDS = 0 V 30 65 OFF-state; Tj = 25°C; VIN = VDRAIN = 0 V; 10 IS = 1 mA Input clamp voltage μA 25 5.5 IS = -1 mA Input threshold voltage 7 -0.7 VDS = VIN; ID = 1 mA Unit 1 3.5 V V Table 9. Status pin Symbol 8/20 Parameter Test conditions Min. Typ. Max. Unit VSTAT Status low output voltage ISTAT = 1 mA 0.5 V ILSTAT Status leakage current Normal operation; VSTAT = 5 V 10 μA CSTAT Status pin input capacitance Normal operation; VSTAT = 5 V 100 pF DocID023206 Rev 5 VNLD5090-E Electical specifications Table 9. Status pin (continued) Symbol VSTCL Parameter Test conditions Min. ISTAT = 1 mA Status clamp voltage Typ. 5.5 ISTAT = -1 mA Max. 7 -0.7 Unit V Table 10. Switching characteristics(1) Symbol Parameter Test conditions Min. Typ. Max. Unit (2) td(ON) Turn-on delay time RL = 8.2 VCC = 13 V — 8 — μs td(OFF) Turn-off delay time RL = 8.2 VCC = 13 V(2) — 3.4 — μs RL = 8.2 VCC = 13 V(2) — 10 — μs Fall time RL = 8.2 VCC = 13 V(2) — 2.7 — μs WON Switching energy losses at turn-on RL = 8.2 VCC = 13 V(2) — 57 — μJ WOFF Switching energy losses at turn-off RL = 8.2 VCC = 13 V(2) — 14 — μJ Qg Total gate change VINx/SUPPLYx = 5 V tr tf Rise time 2 nC 1. See Figure 5: Application schematic. 2. See Figure 4: Switching characteristics. Table 11. Protection and diagnostics Symbol Parameter IlimH DC short-circuit current VDS = 13 V; VINx/SUPPLYx = 5 V IlimL Short-circuit current during thermal cycling VDS = 13 V; TR < Tj < TTSD; VINx/SUPPLYx = 5 V 8 A tdlimL Step response current limit VDS = 13 V; Vinput = 5 V 44 μs TTSD Shutdown temperature TR Reset temperature TRS Thermal reset of STATUS THYST Test conditions Min. Typ. Max. Unit 13 18 25 A 150 175 TRS + 1 TRS + 5 135 Thermal hysteresis (TTSD - TR) °C °C °C 7 DocID023206 Rev 5 200 °C 9/20 19 Electical specifications VNLD5090-E Table 12. Truth table Conditions INPUT DRAIN STATUS Normal operation L H H L H H Current limitation L H H X H H Overtemperature L H H H H L Undervoltage L H H H X X Figure 4. Switching characteristics 10/20 DocID023206 Rev 5 VNLD5090-E 3 Application information Application information Figure 5. Application schematic 9FF 9 5/ 0LFUR&RQWUROOHU ,196833/< '5$,1 5SURW 9 67$786 5SURW 6285&( ("1($'5 3.1 MCU I/O protection ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from latching up(a). The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the LSD I/Os (input levels compatibility) with the latch-up limit of microcontroller I/Os: Equation 1  V OHC – V IH  0.7 --------------------  R prot  --------------------------------------I latchup I IH max Let:  Ilatchup > 20 mA  VOHμC > 4.5 V  35  Rprot  100 K a. In case of negative transient on the drain pin. DocID023206 Rev 5 11/20 19 Application information VNLD5090-E Then, the recommended value is Rprot = 1 K Figure 6 shows the turn-off current drawn during the demagnetization. Figure 6. Maximum demagnetization energy (VCC = 16 V) 91/'  0D[LPXPWXUQRIIFXUUHQWYHUVXVLQGXFWDQFH  ,$   91/'6LQJOH3XOVH 5HSHWLWLYHSXOVH7MVWDUW ƒ& 5HSHWLWLYHSXOVH7MVWDUW ƒ&    /P+    91/' 0D[LPXPWXUQRII(QHUJ\YHUVXV7GHPDJ  91/'6LQJOH3XOVH 5HSHWLWLYHSXOVH7MVWDUW ƒ& 5HSHWLWLYHSXOVH7MVWDUW ƒ& (>P-@       7GHPDJ>PV@   *$3*&)7 12/20 DocID023206 Rev 5 VNLD5090-E Package and PC board thermal data 4 Package and PC board thermal data 4.1 SO-8 thermal data Figure 7. SO-8 PC board ("1($'5 Note: Layout condition of Rth and Zth measurements (Board finish thickness 1.6 mm +/- 10%; Board double layer; Board dimension 78 mm x 86 mm; Board Material FR4; Cu thickness 0.070 mm (front and back side); Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm). Figure 8. SO-8 Rthj-amb vs PCB copper area in open box free air condition 57+MDPE             ("1($'5 DocID023206 Rev 5 13/20 19 Package and PC board thermal data VNLD5090-E Figure 9. SO-8 thermal impedance junction ambient single pulse =7+ƒ&:  &X IRRWSULQW &X FP        7LPHV   ("1($'5 Equation 2: pulse calculation formula Z TH = R TH   + Z THtp  1 –   where  = tP/T Figure 10. Thermal fitting model of a LSD in SO-8 ("1($'5 Note: 14/20 The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. DocID023206 Rev 5 VNLD5090-E Package and PC board thermal data Table 13. SO-8 thermal parameters Area/island (cm2) Footprint 2 R1 = R7 (°C/W) 0.8 0.8 R2 = R8 (°C/W) 2.7 2.7 R3 = R9 (°C/W) 1.5 1.5 R4 = R10 (°C/W) 32 25 R5 (°C/W) 36 20 R6 (°C/W) 35 27 C1 = C7 (W.s/°C) 0.00005 0.00005 C2 = C8 (W.s/°C) 0.001 0.001 C3 = C9 (W.s/°C) 0.01 0.01 C4 = C10 (W.s/°C) 0.02 0.02 C5 (W.s/°C) 0.1 0.15 C6 (W.s/°C) 2.5 3.5 DocID023206 Rev 5 15/20 19 Package and packing information VNLD5090-E 5 Package and packing information 5.1 ECOPACK® In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 SO-8 mechanical data Figure 11. SO-8 package dimensions GAPGCFT00145 16/20 DocID023206 Rev 5 VNLD5090-E Package and packing information Table 14. SO-8 mechanical data Millimeters Symbol Min. Typ. A Max. 1.75 A1 0.10 A2 1.25 b 0.28 0.48 c 0.17 0.23 D(1) 4.80 4.90 5.00 E 5.80 6.00 6.20 E1(2) 3.80 3.90 4.00 e 0.25 1.27 h 0.25 0.50 L 0.40 1.27 L1 k 1.04 0° ccc 8° 0.10 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15 mm in total (both side). 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. DocID023206 Rev 5 17/20 19 Package and packing information 5.3 VNLD5090-E SO-8 packing information Figure 12. SO-8 tube shipment (no suffix) B Base q.ty Bulk q.ty Tube length (± 0.5) A B C (± 0.1) C A 100 2000 532 3.2 6 0.6 All dimensions are in mm. Figure 13. SO-8 tape and reel shipment (suffix “TR”) Reel dimensions Base q.ty Bulk q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 All dimensions are in mm. Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape hole spacing Component spacing Hole diameter Hole diameter Hole position Compartment depth Hole spacing W P0 (± 0.1) P D (+ 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 All dimensions are in mm. End Start Top cover tape No components Components Empty components pockets saled with cover tape. User direction of feed 18/20 DocID023206 Rev 5 No components 500mm min 500mm min VNLD5090-E 6 Revision history Revision history Table 15. Document revision history Date Revision Changes 16-May-2012 1 Initial release. 21-Jun-2012 2 Updated Figure 3: Configuration diagrams (top view) 13-Nov-2013 3 Updated Features list Table 4: Absolute maximum ratings: – -ID, EAS: updated values Updated Table 5: Thermal data Table 6: PowerMOS section: – VCLAMP: updated parameter Table 8: Input section: – IISS: updated maximum value Table 10: Switching characteristics: – WON, WOFF: updated unit values Updated Figure 5: Application schematic Updated Section 3.1: MCU I/O protection Added Chapter 4: Package and PC board thermal data 26-Feb-2015 4 Table 12: Truth table: removed “Output voltage < VOL” condition 26-Oct-2017 5 Added in cover page “automotive” word in the title and the icon of the car. Updated Features on page 1. DocID023206 Rev 5 19/20 19 VNLD5090-E IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 20/20 DocID023206 Rev 5