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VNP7N04FI

VNP7N04FI

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    ISOWATT220-3

  • 描述:

    IC PWR DRVR N-CH 1:1 ISOWATT220

  • 数据手册
  • 价格&库存
VNP7N04FI 数据手册
® VND7N04/VND7N04-1 VNP7N04FI/K7N04FM ”OMNIFET”: FULLY AUTOPROTECTED POWER MOSFET T YPE VND7N04 VND7N04-1 VNP7N04F I VNK7N04F M s s s s s s V c lamp 42 42 42 42 V V V V R DS(on) 0.14 0.14 0.14 0.14 Ω Ω Ω Ω I l im 7 7 7 7 A A A A 3 3 2 1 s s s LINEAR CURRENT LIMITATION THERMAL SHUT DOWN SHORT CIRCUIT PROTECTION INTEGRATED CLAMP LOW CURRENT DRAWN FROM INPUT PIN DIAGNOSTIC FEEDBACK THROUGH INPUT PIN ESD PROTECTION DIRECT ACCESS TO THE GATE OF THE POWER MOSFET (ANALOG DRIVING) COMPATIBLE WITH STANDARD POWER MOSFET 1 DPAK TO-252 IPAK TO-251 3 1 2 DESCRIPTION The VND7N04, VND7N04-1, VNP7N04FI and VNK7N04FM are monolithic devices made using STMicroeletronics VIPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh BLOCK DIAGRAM ISOWATT220 SOT82-FM enviroments. Fault feedback can be detected by monitoring the voltage at the input pin. February 2000 1/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM ABSOLUTE MAXIMUM RATING Symbol Parameter DPAK IP AK V DS V in ID IR V esd P tot Tj Tc T stg Drain-source Voltage (V in = 0) Input Voltage Drain Current Reverse DC O utput Current Electrostatic Discharge (C= 100 pF, R=1.5 KΩ ) Total Dissipation at T c = 25 C Operating Junction T emperature Case O perating T emperature Storage Temperature o Value ISOW AT T220 Internally Clamped 18 Internally Limited -7 2000 60 24 Internally Limited Internally Limited -55 to 150 9 SOT -82FM Unit V V A A V W o o o C C C THERMAL DATA DPAK/IPAK R t hj-ca se Thermal Resistance Junction-case Max R t hj-a mb Thermal Resistance Junction-ambient Max 3.75 100 ISOW AT T220 5.2 62.5 SO T82-FM 14 100 o C/W C/W o ELECTRICAL CHARACTERISTICS (-40 < Tj < 125 oC unless otherwise specified) OFF Symb ol V CLAMP V CL TH V I NCL I DSS I I SS Parameter Drain-source Clamp Voltage Drain-source Clamp Threshold Voltage Input-Source Reverse Clamp Voltage Zero Input Voltage Drain Current (V in = 0) Supply Current from Input Pin Test Cond ition s I D = 200 mA I D = 2 mA I in = -1 mA V DS = 13 V V DS = 25 V V DS = 0 V V in = 0 V in = 0 Vin = 10 V 250 V in = 0 V in = 0 Min. 32 31 -1.1 -0.25 75 200 550 Typ . 42 Max. 52 Un it V V V µA µA µA ON (∗) Symb ol V IN(th) R DS( on) Parameter Input Threshold Voltage Static Drain-source On Resistance V DS = Vin Test Cond ition s ID + Ii n = 1 mA A A A A Min. 0.8 Typ . Max. 3 0.14 0.28 0.28 0.56 Un it V Ω Ω Ω Ω V i n = 10 V I D = 3.5 ID = 3.5 Vi n = 5 V -40 < T j < 25 oC V i n = 10 V I D = 3.5 ID = 3.5 Vi n = 5 V o T j = 125 C 2/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM ELECTRICAL CHARACTERISTICS (continued) DYNAMIC Symb ol g fs ( ∗ ) C oss Parameter Forward Transconductance Output Capacitance Test Cond ition s V DS = 13 V V DS = 13 V I D = 3.5 A f = 1 MHz Vin = 0 Min. 2 Typ . 5 250 500 Max. Un it S pF SWITCHING (**) Symb ol t d(on) tr t d(of f) tf t d(on) tr t d(of f) tf (di/dt) on Qi Parameter Turn-on Delay Time Rise Time Turn-off Delay Time Fall T ime Turn-on Delay Time Rise Time Turn-off Delay Time Fall T ime Turn-on Current Slope Total Input Charge Test Cond ition s V DD = 15 V V gen = 10 V (see figure 3) V DD = 15 V V gen = 10 V (see figure 3) V DD = 15 V V i n = 10 V V DD = 12 V Id = 3.5 A R gen = 10 Ω Min. Typ . 50 60 130 50 140 0.4 2.5 1 50 18 Max. 150 180 300 200 500 1.1 7 4 Un it ns ns ns ns ns µs µs µs A/ µ s nC Id = 3.5 A R gen = 1000 Ω ID = 3.5 A R gen = 10 Ω ID = 3.5 A V i n = 10 V SOURCE DRAIN DIODE Symb ol V SD ( ∗ ) t r r (∗∗ ) Q r r (∗∗ ) I RRM ( ∗∗ ) Parameter Forward O n Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Test Cond ition s I SD = 3.5 A V in = 0 40 0.2 3.6 I SD = 3.5 A di/dt = 100 A/ µ s Tj = 25 oC V DD = 30 V (see test circuit, figure 5) Min. Typ . Max. 1.7 Un it V ns µC A PROTECTION Symb ol I lim t dl im (∗∗ ) T jsh (∗∗ ) T j rs (∗∗ ) I gf ( ∗∗ ) E as ( ∗∗ ) Parameter Drain Current Limit Step Response Current Limit Overtemperature Shutdown Overtemperature Reset Fault Sink Current Single Pulse Avalanche Energy V i n = 10 V Vi n = 5 V VDS = 13 V V DS = 13 V o Test Cond ition s V i n = 10 V Vi n = 5 V V i n = 10 V Vi n = 5 V VDS = 13 V V DS = 13 V Min. 4 4 Typ . 7 7 13 15 Max. 11 11 20 25 Un it A A µs µs o 150 135 50 20 0.4 C C o mA mA J starting T j = 25 C V DD = 20 V V i n = 10 V R gen = 1 K Ω L = 30 mH ( ∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % ( ∗∗) Parameters guaranteed by design/characterization 3/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM PROTECTION FEATURES During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user’s standpoint is that a small DC current (Iiss) flows into the Input pin in order to supply the internal circuitry. The device integrates: - OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 150oC. The device is automatically restarted when the chip temperature falls below 135oC. - OVERVOLTAGE CLAMP PROTECTION: internally set at 42V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh. - STATUS FEEDBACK: In the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 Ω. The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)). - LINEAR CURRENT LIMITER CIRCUIT: limits 4/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM Thermal Impedance For DPAK / IPAK Thermal Impedance For ISOWATT220 Derating Curve Output Characteristics Transconductance Static Drain-Source On Resistance vs Input Voltage 5/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM Static Drain-Source On Resistance Static Drain-Source On Resistance Input Charge vs Input Voltage Capacitance Variations Normalized Input Threshold Voltage vs Temperature Normalized On Resistance vs Temperature 6/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM Normalized On Resistance vs Temperature Turn-on Current Slope Turn-on Current Slope Turn-off Drain-Source Voltage Slope Turn-off Drain-Source Voltage Slope Switching Time Resistive Load 7/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM Switching Time Resistive Load Switching Time Resistive Load Current Limit vs Junction Temperature Step Response Current Limit Source Drain Diode Forward Characteristics 8/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM Fig. 1: Unclamped Inductive Load Test Circuits Fig. 2: Unclamped Inductive Waveforms Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Input Charge Test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 6: Waveforms 9/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 V2 0.60 0o 2.20 0.90 0.03 0.64 5.20 0.45 0.48 6.00 6.40 4.40 9.35 0.8 1.00 8o 0.024 0o TYP. MAX. 2.40 1.10 0.23 0.90 5.40 0.60 0.60 6.20 6.60 4.60 10.10 MIN. 0.087 0.035 0.001 0.025 0.204 0.018 0.019 0.236 0.252 0.173 0.368 0.031 0.039 0o inch TYP. MAX. 0.094 0.043 0.009 0.035 0.213 0.024 0.024 0.244 0.260 0.181 0.398 DIM. P032P_B 10/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM TO-251 (IPAK) MECHANICAL DATA DIM. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 V1 0.45 0.48 6.00 6.40 4.40 15.90 9.00 0.80 0.80 10 o mm MIN. 2.20 0.90 0.70 0.64 5.20 0.30 0.95 0.60 0.60 6.20 6.60 4.60 16.30 9.40 1.20 1.00 0.018 0.019 0.237 0.252 0.173 0.626 0.354 0.031 TYP. MAX. 2.40 1.10 1.30 0.90 5.40 0.85 MIN. 0.087 0.035 0.028 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.035 0.213 0.033 0.012 0.037 0.024 0.024 0.244 0.260 0.181 0.642 0.370 0.047 0.031 10 o 0.039 P032N_E 11/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM ISOWATT220 MECHANICAL DATA DIM. MIN. A B D E F F1 F2 G G1 H L2 L3 L4 L6 L7 Ø 28.6 9.8 15.9 9 3 4.4 2.5 2.5 0.4 0.75 1.15 1.15 4.95 2.4 10 16 30.6 10.6 16.4 9.3 3.2 1.126 0.385 0.626 0.354 0.118 mm TYP. MAX. 4.6 2.7 2.75 0.7 1 1.7 1.7 5.2 2.7 10.4 MIN. 0.173 0.098 0.098 0.015 0.030 0.045 0.045 0.195 0.094 0.393 0.630 1.204 0.417 0.645 0.366 0.126 inch TYP. MAX. 0.181 0.106 0.108 0.027 0.039 0.067 0.067 0.204 0.106 0.409 A B L3 L6 L7 F1 ¯ F D G1 E H F2 123 L2 L4 P011G 12/14 G VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM SOT-82FM MECHANICAL DATA mm MIN. A A1 b b1 b2 c D e E L L1 2.85 1.47 0.40 1.4 1.3 0.45 10.5 2.2 7.45 15.5 1.95 TYP. MAX. 3.05 1.67 0.60 1.6 1.5 0.6 10.9 2.8 7.75 15.9 2.35 MIN. 1.122 0.578 0.157 0.551 0.511 0.177 4.133 0.866 2.933 6.102 0.767 inch TYP. MAX. 1.200 0.657 0.236 0.630 0.590 0.236 4.291 1.102 3.051 6.260 0.925 DIM. P032R 13/14 VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 14/14
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