VNQ6004SA-E
Quad-channel high-side driver with 16-bit SPI interface
Datasheet - production data
– Reverse battery protected through power
outputs self turn-on (no external
components)
– Load dump protected
– Protection against loss of ground
PSSO36
Description
Features
Channel
VCC
RON(typ)
ILIMH(min)
0–1
28 V
30 mΩ
25 A
2–3
28 V
10 mΩ
55 A
• General
– 16-bit ST-SPI for full and diagnostic
– Programmable Bulb/LED mode for ch. 0–1
– Integrated PWM and phase shift generation
unit
– 160 Hz internal PWM fallback frequency
– Advanced limp home functionalities for
robust fail-safe system
– Very low standby current
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
• Diagnostic functionalities
– Multiplex proportional load current sense
– Synchronous diagnostic of over load and
short to GND, output shorted to VCC,
ON-state and OFF-state open-load
– Programmable case over temperature
warning
• Protection
– Load current limitation
– Self limiting of fast thermal transients
– Power limitation and over temperature
shutdown (latching-off or auto restart)
– Undervoltage shutdown
– Overvoltage clamp
March 2015
This is information on a product in full production.
The VNQ6004SA-E is a device made using
STMicroelectronics® VIPower® technology. It is
intended for driving resistive or inductive loads
directly connected to ground. The device is
protected against voltage transient on VCC pin.
Programming, control and diagnostics are
implemented via the SPI bus.
An analog current feedback for each channel is
connected to the CURRENT-SENSE pin via a
multiplexer. A CS_SYNC pin delivers a
synchronous signal for sampling the current
sense while the corresponding output is on.
The device detects open-load for both on and
OFF-state conditions.
Real time diagnostic is available through the SPI
bus (open-load, output short to VCC, over
temperature, communication error, power
limitation).
Output current limitation protects the device in an
over load condition. The device can limit the
dissipated power to a safe level up to thermal
shutdown intervention. Thermal shutdown can be
configured as latched off or with automatic restart.
The device enters a limp home mode in case of
loss of digital supply (VDD), reset of digital
memory or CSN monitoring time-out event. In this
mode states of channel 0, 1, 2 or 3 are
respectively controlled by four dedicated pins IN0,
IN1, IN2 and IN3. Channel 0,1 can be
programmed in BULB/LED mode.
DocID022315 Rev 5
1/73
www.st.com
Contents
VNQ6004SA-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
2.3
3
2.1.1
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.2
Fail Safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.3
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.4
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.5
Sleep mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.6
Sleep mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.7
Battery undervoltage mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Programmable functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1
Outputs configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.2
Case over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.3
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.4
Open-load ON-state detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.5
Open-load OFF-state detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.6
Current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Test mode (reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1
3.2
3.3
2/73
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPI communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.1
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.2
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.3
SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1
SDI, SDO format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.2
Global status byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.3
Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.1
Address 00h - Control Register (CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.2
Address 01h - SPI Output Control Register (SOCR) . . . . . . . . . . . . . . . 34
3.3.3
Address 02h - Direct Input Enable Control Register (DIENCR) . . . . . . . 35
DocID022315 Rev 5
VNQ6004SA-E
4
Address 03h - Current Sense Multiplexer Control Register (CSMUXCR)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.5
Address 04h - Current Sense Ratio Control Register (CSRATCR) . . . . 36
3.3.6
Address 05h - PWM Mode Control Register (PWMCR) . . . . . . . . . . . . 36
3.3.7
Address 06h - Open-load ON-State Control Register (OLONCR) . . . . . 37
3.3.8
Address 07h - Open-load OFF-State Control Register (OLOFFCR) . . . 37
3.3.9
Address 08h - Automatic Shutdown Control Register (ASDTCR) . . . . . 37
3.3.10
Address 09h - Channel Control Register (CCR) . . . . . . . . . . . . . . . . . . 38
3.3.11
Address 10h - 13h - Duty Cycle Control Register (DUTYXCR) . . . . . . . 38
3.3.12
Address 18h - 1Ah - Phase Control Register (PHASEXCR) . . . . . . . . . 39
3.3.13
Address 2Eh - Channel Read Back Status Register (CHDRVR) . . . . . . 39
3.3.14
Address 2Fh - General Status Register (GENSTR) . . . . . . . . . . . . . . . . 40
3.3.15
Address 30h - Over Temperature Status Register (OTFLTR) . . . . . . . . 40
3.3.16
Address 31h - Open-Load ON-State Status Register (OLFLTR) . . . . . . 41
3.3.17
Address 32h - Open-Load OFF-State / Stuck to VCC Status Register
(STKFLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.18
Address 33h - Power Limitation Status Register (PWLMFLTR) . . . . . . . 42
3.3.19
Address 34h - Over Load Status Register (OVLFLTR) . . . . . . . . . . . . . 43
3.3.20
Minimum duty cycle vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.21
Address 3Eh - Test Register (TEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.22
Address 3Fh - Configuration Register (GLOBCTR) . . . . . . . . . . . . . . . . 45
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.1
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.2
BULB mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3.3
LED mode (Channel 0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 62
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1
6
3.3.4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4
5
Contents
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.2
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DocID022315 Rev 5
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4
Contents
VNQ6004SA-E
6.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4/73
DocID022315 Rev 5
VNQ6004SA-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Pin functionality description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Example of DUTYCXCR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Example of PHASEXCR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Activation of blanking filter in case of power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Nominal open-load thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STKFLTR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Current sense ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Input data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Output data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Operating codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SPI output control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Direct enable control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Current sense multiplexer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Current sense ratio control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PWM mode control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Open-load ON-state control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Open-load OFF-state control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Automatic shutdown control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Channel control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DUTYCXCR - duty cycle control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PHASECXCR - duty cycle control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Channel read back status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Over temperature status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Open-load ON-state status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Open-load OFF-state / stuck to VCC status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power limitation status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Over load status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
AC characteristics (SDI, SCK, CSN, SDO, PWMCLK pins) . . . . . . . . . . . . . . . . . . . . . . . . 49
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CS_sync pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Logic inputs (IN0,1,2,3 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DocID022315 Rev 5
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6
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
6/73
VNQ6004SA-E
Open-load detection (8 V < VCC < 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
BULB - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
BULB - switching (VCC = 13 V channel 0,1,2,3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
BULB - open-load detection (8 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
BULB - protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
BULB - current sense (8 V < VCC < 18 V, channel 0,1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
BULB - current sense (8 V < VCC < 18 V, channel 2,3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
LED - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LED - switching (VCC = 13 V channel 0,1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LED - open-load detection (8 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LED - protection and diagnosis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LED - current sense (8 V < VCC < 18 V, channel 0,1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DocID022315 Rev 5
VNQ6004SA-E
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
SPI configurable functionalities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPI diagnostic reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Connection diagram (top view—not in scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Battery undervoltage shutdown diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Example of PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Open-load OFF-state detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Example of CS_SYNC synchronization and the current sense pin . . . . . . . . . . . . . . . . . . 25
Bus master and two devices in a normal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Supported SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SPI read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SPI read and clear operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SPI read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Behaviour of overtemperature status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Behaviour of power limitation status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Min duty cycle vs frequency - BULB_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Min duty cycle vs frequency - LED_MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Application schematic (simplified). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Maximum turn off current versus inductance (channel 0, 1) . . . . . . . . . . . . . . . . . . . . . . . . 62
Maximum turn off current versus inductance (channel 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . 63
PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . . 65
PowerSSO-36 Thermal impedance junction ambient single pulse (one channel ON) . . . . 66
Thermal fitting model of a double channel HSD in PowerSSO-36 . . . . . . . . . . . . . . . . . . . 67
PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DocID022315 Rev 5
7/73
7
Block diagram and pin description
1
VNQ6004SA-E
Block diagram and pin description
Figure 1. SPI configurable functionalities
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8/73
DocID022315 Rev 5
VNQ6004SA-E
Block diagram and pin description
Figure 3. Block diagram
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hardware design.
Figure 4. Connection diagram (top view—not in scale)
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&6B6 VDDR: fail safe
–
–
–
–
– Reset or sleep 1:
VDD > VDDR
– Standby or sleep 2:
CSN low for t > tstdby_out
– Normal:
EN = 0
or CSN time out
or SW reset
– VDD < VDDR: reset
– SPI sequence
1. UNLOCK = 1
2. STBY = 0
and EN = 1: normal
– SPI sequence
1. UNLOCK = 1
2. STBY = 1
and EN = 0: fail safe
– Outputs: according to INX
– SPI: active
– Registers: read/writeable,
cleared if entered after HW or
SW reset
– Diagnostics: SPI possible
CurrentSense not possible
Normal
– Fail Safe:
SPI sequence
1. UNLOCK = 1
2. STBY = 0
and EN = 1
– VDD < VDDR: reset
– SPI sequence
1. UNLOCK = 1
2. STBY = 1
and EN = 0: standby
– EN = 0
or CSN time out
or SW reset: fail safe
– Outputs: according to SPI
register settings and INX
– SPI: active
– Registers: read/writeable
– Diagnostics: SPI and
CurrentSense possible
– Regular toggling of CSN
necessary
Standby
– Normal: SPI sequence
1. UNLOCK = 1
2. STBY = 1 and EN = 0
– Fail Safe: SPI sequence
1. UNLOCK = 1
2. STBY = 1 and EN = 0
– Sleep 2:
INX low to high
– VDD < VDDR: reset
– CSN low for t>tstdby_out: fail
safe
– All INX low: sleep 2
–
–
–
–
–
Outputs: according to INX
SPI: inactive
Registers: frozen
Diagnostics: not available
Low supply current from VDD
–
–
–
–
–
Outputs: OFF
SPI: inactive
Registers: cleared
Diagnostics: not available
Low supply current from VDD and
VCC
Reset
Fail Safe
Sleep 1
Reset: all INX = 0
– VDD > VDDR: fail safe
– INX low to high: reset
DocID022315 Rev 5
Outputs: according to INX
SPI: inactive
Registers: cleared
Diagnostics: not available
13/73
72
Functional description
VNQ6004SA-E
Table 2. Operating modes (continued)
Operating
mode
Entering conditions
Sleep 2
Standby: all INX = 0
Battery
Any mode: VCC < VUSD
undervoltage
2.1.1
Leaving conditions
– VDD < VDDR: reset
– CSN low for t > tstdby_out: fail
safe
– INX low to high: standby
VCC > VUSD: back to last mode
Characteristics
–
–
–
–
–
Outputs: OFF
SPI: inactive
Registers: frozen
Diagnostics: not available
Low supply current from VDD and
VCC
–
–
–
–
Outputs: OFF
SPI: active
Register: read/writeable
Diagnostics: SPI possible,
CurrentSense not possible
Reset mode
The device enters Reset mode under three conditions:
•
Automatically during startup
•
If it is in any other mode and if VDD falls below VDDR
•
If it is in Sleep mode 1 and if one input INX is set to 1
In Reset mode, the output stages are according to the inputs INX. The SPI is inactive and all
SPI registers are cleared. The reset bit inside the Global Status Byte is set to 0. The
diagnostics is not available, but the protection are fully functional. In case of over
temperature or power limitation, the outputs work in Autorestart.
Reset mode can be left with 2 conditions:
2.1.2
•
If VDD rises above VDDR, the device enters Fail Safe mode
•
If all inputs INX are 0, the device enters Sleep mode 1.
Fail Safe mode
The device enters Fail Safe mode under five conditions:
•
If it is in Reset mode or in Sleep mode 1 and VDD rises above VDDR
•
If it is in Standby mode or in Sleep mode 2 and CSN is low for t > tstdby_out
•
If it is in Normal mode and bit EN is cleared
•
If it is in Normal mode and CSN is not toggled within tWHCH (CSN timeout)
•
If it is in Normal mode and the SPI sends a SW reset (Command byte = FFh).
In Fail Safe mode, the output stages are according to the inputs INX. The SPI is active. The
reset bit is 0 if the last state was Reset mode or the last command was a SW reset and it is
set to 1 after the first SPI access. The SPI diagnostics is available, the CurrentSense pin is
not available. The protection are fully functional. In case of over temperature or power
limitation, the outputs work in Autorestart.
14/73
DocID022315 Rev 5
VNQ6004SA-E
Functional description
The device exits Fail Safe mode under two conditions:
•
•
•
2.1.3
If the SPI sends the goto Normal mode sequence, the device enters Normal mode:
–
In a first communication set bit UNLOCK = 1
In the consecutive communication set bit STBY = 0 and bit EN = 1
–
This mechanism avoids entering the Normal mode unintentionally.
If the SPI sends the goto standby mode sequence, the device enters Standby mode:
–
In a first communication set bit UNLOCK = 1
In the consecutive communication set bit STBY = 1 and bit EN = 0
–
This mechanism avoids entering the Standby mode unintentionally.
If VDD falls below VDDR, the device enters Reset mode.
Normal mode
The device enters Normal mode if it is in Fail Safe mode and the SPI sends the goto Normal
mode sequence:
•
In a first communication set bit UNLOCK = 1
In the consecutive communication set bit STBY = 0 and bit EN = 1
•
This mechanism avoids entering the Normal mode unintentionally.
In Normal mode, the output stages are controlled by the SPI and the INX settings. The SPI
is active. CSN must be toggled regularly within tWHCH to keep the device in Normal mode.
The SPI diagnostics and the CurrentSense pin are both available. The protection are fully
functional. The outputs can be set to Autorestart or Latch. In Autorestart the outputs are
switched on again automatically after an over temperature or power limitation event, while in
Latch the relevant status register has to be cleared to switch them on again.
Normal mode can be left with 5 conditions:
•
If VDD falls below VDDR, the device enters Reset mode.
•
If the SPI sends the goto standby sequence, the devices enters Standby mode:
–
In a first communication set UNLOCK = 1
In the consecutive communication set STBY = 1 and EN = 0
–
This mechanism avoids entering the Standby mode unintentionally.
•
If the SPI clears the EN bit (EN = 0), the devices enters Fail Safe mode
•
CSN time out: If CSN is not toggled within the minimum CSN monitoring timeout period
tWHCH, the device enters Fail Safe mode.
•
If the SPI sends a SW reset command (Command byte = FFh), all registers are cleared
and the device enters Fail Safe mode.
DocID022315 Rev 5
15/73
72
Functional description
2.1.4
VNQ6004SA-E
Standby mode
The device enters Standby mode under three conditions:
•
•
•
If it is in Fail Safe mode and the SPI sends the goto standby sequence:
–
In a first communication set UNLOCK = 1
In the consecutive communication set STBY = 1 and EN = 0
–
This mechanism avoids entering the Standby mode unintentionally.
If it is in Normal mode and the SPI sends the goto standby sequence:
–
In a first communication set UNLOCK = 1
In the consecutive communication set STBY = 1 and EN = 0
–
This mechanism avoids entering the Standby mode unintentionally.
If it is in Sleep mode 2 and one input INX is set to one.
The output stages are according to INX settings, the current from VDD is nearly 0.The SPI is
inactive and all registers are frozen to the last state. The diagnostics is not available.
Standby mode can be left with three conditions:
2.1.5
•
If VDD falls below VDDR, the device enters Reset mode.
•
If CSN is low for t > tstdby_out, the device wakes up. As EN has been set to 0, the device
enters Fail Safe mode and recovers full functionality with command of the outputs and
diagnostics.
•
If all direct inputs INX are 0, the device enters Sleep Mode 2 resulting in minimal supply
current from VCC and VDD.
Sleep mode 1
The device enters Sleep mode 1, if it is in Reset mode and if all inputs INX are 0.
All outputs are off, the current from VDD is nearly 0, and the current from VCC is reduced to
ISoff. The SPI is inactive and all registers are cleared. The diagnostics is not available.
Sleep mode 1 can be left with two conditions:
2.1.6
•
If VDD rises above VDDR, the device enters Fail Safe mode.
•
If one of the inputs INX is set to 1, the device enters Reset mode.
Sleep mode 2
The device enters Sleep mode 2, if it is in Standby mode and if all inputs INX are 0.
All outputs are off, the current from VDD is nearly 0, and the current from VCC is reduced to
ISoff. The SPI is inactive and all registers are frozen to the last state. The diagnostics is not
available.
Sleep mode 2 can be left with three conditions:
•
16/73
If VDD falls below VDDR, the device enters Reset mode.
•
If CSN is low for t > tstdby_out, the device enters Fail Safe mode.
•
If one of the inputs INX is set to 1, the device enters Standby mode.
DocID022315 Rev 5
VNQ6004SA-E
2.1.7
Functional description
Battery undervoltage mode
If the battery supply voltage VCC falls below the undervoltage shutdown threshold VUSD
while VDD remains above the reset threshold VDDR, the device enters Battery undervoltage
mode independent from the operation mode. In Battery undervoltage mode, the outputs are
turned off. The SPI is active and the SPI register contents are retained. The SPI diagnostics
is available, the CurrentSense pin is not available. The bit VCCUV in the general status
register GENSTR is set. If VCC rises above the threshold VUSD + VUSDhyst, the device
returns to the last mode and VCCUV is cleared.
Figure 5. Battery undervoltage shutdown diagram
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DocID022315 Rev 5
17/73
72
Functional description
VNQ6004SA-E
Figure 6. Device state diagram
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