VNQ7040AY
Quad channel high-side driver with MultiSense analog feedback
for automotive applications
Datasheet - production data
Features
Load current limitation
Self limiting of fast thermal transients
Configurable latch-off on
overtemperature or power limitation
with dedicated fault reset pin
Loss of ground and loss of VCC
Reverse battery through self turn-on
Electrostatic discharge protection
Applications
Max transient supply voltage
VCC
41 V
Operating voltage range
VCC
4 to 28 V
Typ. on-state resistance (per ch)
RON
40 mΩ
Current limitation (typ)
ILIMH
34 A
Standby current (max)
ISTBY
0.5 µA
All types of Automotive resistive, inductive
and capacitive loads
Specially intended for Automotive Turn
Indicators (up to P27W or SAE1156 and
R5W paralleled or LED Rear Combinations)
Description
AEC-Q100 qualified
General
Quad channel smart high-side driver
with MultiSense analog feedback
LED Mode for channel 0 and 1
Very low standby current
Compatible with 3 V and 5 V CMOS
outputs
MultiSense diagnostic functions
Multiplexed analog feedback of:
Load current with high precision
proportional current mirror;
VCC supply voltage;
TCHIP device temperature
Overload and short to ground (power
limitation) indication
Thermal shutdown indication
OFF-state open load detection
Output short to VCC detection
Sense enable/disable
Protections
Undervoltage shutdown
Overvoltage clamp
December 2017
The device is a quad channel high-side driver
manufactured using the latest ST proprietary
VIPower® technology and housed in a
PowerSSO-36 package. The device is designed
to drive 12 V automotive grounded loads through
a 3 V and 5 V CMOS-compatible interface, and to
provide protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions such as high precision proportional load
current sense, supply voltage feedback and chip
temperature sense, in addition to the detection of
overload and short circuit to ground, short to VCC
and OFF-state open-load.
The device features a dedicated LED Mode.
DocID027406 Rev 4
This is information on a product in full production.
1/50
www.st.com
Contents
VNQ7040AY
Contents
1
Block diagram and pin description ................................................ 4
2
Electrical specification .................................................................... 6
3
4
2.1
Absolute maximum ratings ................................................................ 6
2.2
Thermal data ..................................................................................... 7
2.3
Electrical characteristics .................................................................... 7
2.3.1
General electrical specification ........................................................... 7
2.3.2
Bulb mode (default) .......................................................................... 16
2.3.3
Electrical characteristics curves - Bulb Mode ................................... 20
2.3.4
LED Mode (Channel 0 and 1) ........................................................... 24
2.3.5
Electrical characteristics curves - LED mode ................................... 27
2.3.6
Truth tables ....................................................................................... 28
Protections..................................................................................... 30
3.1
Power limitation ............................................................................... 30
3.2
Thermal shutdown ........................................................................... 30
3.3
Current limitation ............................................................................. 30
3.4
Negative voltage clamp ................................................................... 30
Application information ................................................................ 31
4.1
GND protection network against reverse battery............................. 31
4.2
Immunity against transient electrical disturbances .......................... 32
4.3
MCU I/Os protection ........................................................................ 32
4.4
Multisense - analog current sense .................................................. 33
4.4.1
Principle of Multisense signal generation ......................................... 34
4.4.2
TCASE and VCC monitor ................................................................. 36
4.4.3
Short to VCC and OFF-state open-load detection ........................... 37
5
Maximum demagnetization energy (VCC = 16 V) ........................ 38
6
Package and PCB thermal data .................................................... 39
6.1
7
8
2/50
PowerSSO-36 thermal data ............................................................ 39
Package information ..................................................................... 43
7.1
PowerSSO-36 package information ................................................ 43
7.2
PowerSSO-36 packing information ................................................. 45
7.3
PowerSSO-36 marking information ................................................. 47
Order codes ................................................................................... 48
DocID027406 Rev 4
VNQ7040AY
9
Contents
Revision history ............................................................................ 49
DocID027406 Rev 4
3/50
Block diagram and pin description
1
VNQ7040AY
Block diagram and pin description
Figure 1: Block diagram
Table 1: Pin functions
Name
VCC
OUTPUT0,1,2,3
GND
Battery connection.
Power output.
Ground connection.
INPUT0,1,2,3
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS
outputs. They control output switch state.
MultiSense
Multiplexed analog sense output pin; it delivers a current proportional to the selected
diagnostic: load current, supply voltage or chip temperature.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the
MultiSense diagnostic pin
LED0,1
Active high compatible with 3 V and 5 V CMOS outputs pin; they enable the LED
mode on logic high level (see Table 15: "Truth table").
SEL0,1,2
Active high compatible with 3 V and 5 V CMOS outputs pin; they address the
MultiSense multiplexer (see Table 15: "Truth table").
FaultRST
4/50
Function
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in
case of fault; If kept low, sets the outputs in auto-restart mode.
DocID027406 Rev 4
VNQ7040AY
Block diagram and pin description
Figure 2: Configuration diagram (top view)
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
N.C.
N.C.
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
N.C.
LED1
LED0
SEn
SEL2
SEL1
SEL0
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TAB/Vcc
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
OUTPUT3
OUTPUT3
OUTPUT3
OUTPUT3
N.C.
N.C.
OUTPUT0
OUTPUT0
OUTPUT0
OUTPUT0
N.C.
INPUT3
INPUT2
INPUT1
INPUT0
MultiSense
GND
FaultRST
PowerSSO-36 PACKAGE
Table 2: Suggested connections for unused and not connected pins
Connection /
pin
MultiSense
N.C.
Floating
Not allowed
(1)
To ground
Through 1 kΩ
resistor
X
X
SEn, SELx, LEDx,
Output
Input
X
X
X
Not
allowed
Through 15 kΩ
resistor
Through 15 kΩ
resistor
FaultRST
Notes:
(1)X:
do not care.
DocID027406 Rev 4
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Electrical specification
2
VNQ7040AY
Electrical specification
Figure 3: Current and voltage conventions
IS
V CC
IF R
F a u ltR S T
V FR
V SEn
M u ltiS en se
V SENSE
L E D 0 ,1
0 ,1 ,2 ,3
V IN
V LED
V SEL
VOUT
IS E N S E
SEn
IN P U T
S E L 0,1 ,2
I LE D
I IN
V CC
O U T P U T 0 ,1,2 ,3
IS E n
IS E L
V Fn
IO U T
IG N D
GAPG0910151354CFT
VFn = VOUTn - VCC
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in the table below for extended
periods may affect device reliability.
Table 3: Absolute maximum ratings
Symbol
Value
VCC
DC supply voltage
38
-VCC
Reverse DC supply voltage
16
VCCPK
Maximum transient supply voltage (ISO7637-2:2004 Pulse 5b level
IV clamped to 40 V; RL = 4 Ω)
40
VCCJS
Maximum jump start voltage for single pulse short circuit protection
28
-IGND
DC reverse ground pin current
200
IOUT
OUTPUT0,1,2,3 DC output current
Unit
V
mA
Internally
limited
-IOUT_0,1
OUTPUT0,1 Reverse DC output current
10
-IOUT_2,3
OUTPUT2,3 Reverse DC output current
10
IIN
6/50
Parameter
A
INPUT0,1,2,3 DC input current
ILED
LED0,1 DC input current
ISEn
SEn DC input current
ISEL
SEL0,1,2 DC input current
DocID027406 Rev 4
-1 to 10
mA
VNQ7040AY
Electrical specification
Symbol
Parameter
Unit
IFR
FaultRST DC input current
-1 to 10
mA
VFR
FaultRST DC input voltage
7.5
V
MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V)
-10
mA
MultiSense pin DC output current in reverse (VCC < 0 V)
20
mA
Maximum switching energy (single pulse)
(TDEMAG = 0.4 ms; Tjstart = 150 °C)
36
mJ
4000
2000
4000
4000
4000
V
V
V
V
V
750
V
ISENSE
EMAX
Electrostatic discharge (JEDEC 22A-114F)
INPUT0,1,2,3
MultiSense
VESD
VESD
LED0,1, SEn, SEL0,1,2, FaultRST
OUTPUT0,1,2,3
VCC
Charge device model (CDM-AEC-Q100-011)
Tj
Tstg
2.2
Value
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
°C
Thermal data
Table 4: Thermal data
Symbol
Parameter
Thermal resistance junction-board (JEDEC JESD 51-8)
Rthj-board
Rthj-amb
Rthj-amb
Typ. value
(1)(2)
Unit
4.9
Thermal resistance junction-ambient (JEDEC JESD 51-2)
(1)(3)
53
Thermal resistance junction-ambient (JEDEC JESD 51-2)
(1)(2)
18.5
°C/W
Notes:
(1)One
2.3
channel ON.
(2)Device
mounted on four-layers 2s2p PCB
(3)Device
mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
Electrical characteristics
7 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified.
2.3.1
General electrical specification
Table 5: Power section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
4
13
28
VCC
Operating supply
voltage
VUSD
Undervoltage
shutdown
4
Undervoltage
shutdown reset
5
VUSDReset
DocID027406 Rev 4
Unit
V
7/50
Electrical specification
VNQ7040AY
Symbol
Parameter
VUSDhyst
Undervoltage
shutdown
hysteresis
Vclamp
Clamp voltage
ISTBY
Supply current in
standby at
VCC = 13 V (1)
Test conditions
IS = 20 mA; 25 °C < Tj < 150 °C
41
IS = 20 mA; Tj = -40 °C
38
VCC = 13 V;
VINx = VOUTx = VFR = VSEn = 0 V;
VSEL0,1,2 = 0 V; VLED0,1 = 0 V;
Tj = 125 °C
3
µA
300
550
µs
10
16
mA
18.5
mA
VCC = 13 V; VSEn = 5 V;
VFR = VSEL0,1 = 0 V; VINx = 5 V;
IOUT0,1,2,3 = 2.5 A
8/50
60
VINx = VOUTx = 0 V; VCC = 13 V;
Tj = 25 °C
0
VINx = VOUTx = 0 V; VCC = 13 V;
Tj = 125 °C
0
IOUT = -2.5 A; Tj = 150 °C
Notes:
(3)For
V
µA
Control stage
current
consumption in ON
state. All channels
active.
(2)Parameter
V
0.5
VCC = 13 V;
VSEn = VFR = VSEL0,1 = 0 V; VINx = 5 V;
IOUT0,1,2,3 = 0 A
(1)PowerMOS
52
VCC = 13 V;
VINx = VOUTx = VFR = VSEn = 0 V;
VSEL0,1,2 = 0 V; VLED0,1 = 0 V;
Tj = 85 °C (2)
Supply current
Output - VCC diode
voltage (3)
46
µA
IS(ON)
VF
Unit
0.5
VCC = 13 V; VINx = VOUTx = VFR = 0 V;
VSEL0,1,2 = 0 V; VLED0,1 = 0 V;
VSEn = 5 V to 0 V
IL(off)
Max.
VCC = 13 V;
VINx = VOUTx = VFR = VSEn = 0 V;
VSEL0,1,2 = 0 V; VLED0,1 = 0 V;
Tj = 25 °C
Standby mode
blanking time
Off-state output
current at
VCC = 13 V(1)
Typ.
0.3
tD_STBY
IGND(ON)
Min.
leakage included.
specified by design; not subject to production test.
each channel.
DocID027406 Rev 4
0.01
0.5
µA
3
0.7
V
VNQ7040AY
Electrical specification
Table 6: Logic Inputs
7 V < VCC < 28 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0.9
V
INPUT0,1,2,3 characteristics
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
5.3
IIN = -1 mA
µA
7.2
-0.7
V
FaultRST characteristics
VFRL
Input low level voltage
IFRL
Low level input current
VFRH
Input high level voltage
IFRH
High level input current
VFR(hyst)
Input hysteresis voltage
VFRCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
5.3
IIN = -1 mA
µA
7.5
-0.7
V
SEL0,1,2 characteristics (7 V < VCC < 18 V)
VSELL
Input low level voltage
ISELL
Low level input current
VSELH
Input high level voltage
ISELH
High level input current
VSEL(hyst)
Input hysteresis voltage
VSELCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
5.3
IIN = -1 mA
µA
7.2
-0.7
V
LED0,1 characteristics (7 V < VCC < 18 V)
VLEDL
Input low level voltage
ILEDL
Low level input current
VLEDH
Input high level voltage
ILEDH
High level input current
VLED(hyst)
Input hysteresis voltage
VLEDCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
5.3
IIN = -1 mA
µA
7.2
-0.7
V
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
0.9
VIN = 0.9 V
VIN = 2.1 V
DocID027406 Rev 4
V
1
µA
2.1
V
10
µA
9/50
Electrical specification
VNQ7040AY
7 V < VCC < 28 V; -40 °C < Tj < 150 °C
Symbol
VSEn(hyst)
VSEnCL
Parameter
Test conditions
Input hysteresis voltage
Typ.
Max.
0.2
IIN = 1 mA
Input clamp voltage
Min.
V
5.3
IIN = -1 mA
Unit
7.2
-0.7
V
Table 7: Protections
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
TTSD
TR
TRS
Parameter
Test conditions
Shutdown
temperature
Reset temperature
(1)
Thermal reset of
fault diagnostic
indication
Min.
Typ.
Max.
150
175
200
TRS + 1
TRS + 5
°C
VFR = 0 V; VSEn =5 V
135
THYST
Thermal hysteresis
(TTSD-TR)(1)
5
ΔTJ_SD
Dynamic
temperature
60
tLATCH_RST
VDEMAG
VON
Fault reset time for
output unlatch(1)
Turn-off output
voltage clamp
Output voltage drop
limitation
VFR = 5 V to 0 V; VSEn = 5 V;
VINx = 5 V; VSEL0,1,2 = 0 V
3
IOUT= 2 A; L = 6 mH; Tj = 40 °C
VCC 38
IOUT= 2 A; L = 6 mH;
Tj = 25 °C to 150 °C
VCC 41
IOUT= 0.25 A
Notes:
(1)Parameter
10/50
Unit
guaranteed by design and characterization; not subject to production test.
DocID027406 Rev 4
10
K
20
µs
V
VCC 46
20
VCC 52
V
mV
VNQ7040AY
Electrical specification
Table 8: MultiSense
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
VSENSE_CL
MultiSense clamp
voltage
VSEn = 0 V; ISENSE = 1 mA
Min.
Typ.
-17
VSEn = 0 V; ISENSE = -1 mA
Max.
Unit
-12
V
7
V
Current Sense characteristics
MultiSense disabled:
VSEn = 0 V;
0
0.5
-0.5
0.5
MultiSense enabled:
VSEn = 5 V
All channels ON; IOUTX = 0 A;
ChX diagnostic selected;
E.g. Ch0:
VIN0 = 5 V; VIN1,2,3 = 5 V;
VSEL0,1,2 = 0 V;
IOUT0 = 0 A;
IOUT1,2,3 = 2.5 A
0
2
MultiSense enabled:
VSEn = 5 V
ChX OFF; ChX diagnostic
selected:
E.g. Ch0:
VIN0 = 0 V; VIN1,2,3 = 5 V;
VSEL0,1,2 = 0 V;
IOUT0 = 0 A;
IOUT1,2,3 = 2.5 A
0
MultiSense disabled: (1)
-1 V < VSENSE < 5 V
MultiSense
leakage current
ISENSE0
µA
2
Output Voltage
for MultiSense
shutdown
VSEn = 5 V; RSENSE = 2.7 kΩ
E.g. Ch0:
VIN0 = 5 V; VSEL0,1,2 = 0 V;
IOUT0 = 2.5 A
VSENSE_SAT
Multisense
saturation voltage
VCC = 7 V; RSENSE = 2.7 K;
VSEn = 5 V; VIN0 = 5 V;
VSEL0,1,2 = 0 V; IOUT0 = 4.5 A;
Tj = 150°C
5
V
ISENSE_SAT(1)
CS saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0,1,2 = 0 V; Tj = 150°C
4
mA
IOUT_SAT_BULB(1)
Output saturation
current in BULB
mode
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0,1,2 = 0 V; Tj = 150°C
8
A
IOUT_SAT_LED(1)
Output saturation
current in LED
mode
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0,1,2 = 0 V; Tj = 150°C
2.3
A
VOUT_MSD
(1)
5
V
OFF-state diagnostic
VOL
OFF state open
load voltage
detection
threshold
VSEn = 5V; ChX OFF; ChX
diagnostic selected
E.g. Ch0:
VIN0 = 0 V; VSEL0,1,2 = 0 V
DocID027406 Rev 4
2
3
4
V
11/50
Electrical specification
VNQ7040AY
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
IL(off2)
OFF state output
sink current
VIN = 0 V; VOUT = VOL;
Tj = -40°C to 125°C
-100
tDSTKON
OFF state
diagnostic delay
time from falling
edge of INPUT
(see Figure 4:
"Switching times
and Pulse skew")
VSEn = 5 V; ChX ON to OFF
transition; ChX diagnostic
selected
E.g. Ch0:
VIN0 = 5 V to 0 V;
VSEL0,1,2 = 0 V;
VOUT0 > 4 V
100
tD_OL_V
Settling time for
valid OFF-state
open load
diagnostic
indication from
rising edge of
SEn
VINx = 0 V; VFR = 0 V;
VSEL0,1,2 = 0 V; VOUT0 = 4 V;
VSEn = 0 V to 5 V
tD_VOL
OFF state
diagnostic delay
time from rising
edge of VOUT
VSEn = 5V; ChX OFF;
ChX diagnostic selected
E.g. Ch0:
VIN0 = 0 V; VSEL0,1,2 = 0 V;
VOUT0 = 0 V to 4 V
Typ.
Max.
Unit
-15
µA
700
µs
60
µs
5
30
µs
350
Chip temperature analog feedback
VSENSE_TC
dVSENSE_TC/dT
(2)
MultiSense
output voltage
proportional to
chip temperature
Temperature
coefficient
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; VSEL2 = 5 V;
RSENSE = 1 kΩ; VINx = 0 V; Tj = 40°C
2.325
2.41
2.495
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; VSEL2 = 5 V;
RSENSE = 1 kΩ; VINx = 0 V;
Tj = 25°C
1.985
2.07
2.155
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; VSEL2 = 5 V;
RSENSE = 1 kΩ; VINx = 0 V;
Tj = 125°C
1.435
1.52
1.605
V
Tj = -40°C to 150°C
Transfer function
-5.5
mV/K
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC/dT * (T-T0)
VCC supply voltage analog feedback
VSENSE_VCC
MultiSense
output voltage
proportional to
VCC supply
voltage
VCC = 13 V; VSEn = 5 V;
VSEL0,1,2 = 5 V; VINx = 0 V;
RSENSE = 1 kΩ
Transfer function(2)
3.16
3.23
3.3
V
6.6
V
VSENSE_VCC = VCC / 4
Fault diagnostic feedback (see Table 15: "Truth table")
VSENSEH
12/50
MultiSense
output voltage in
fault condition
VCC = 13 V; RSENSE = 1 kΩ
DocID027406 Rev 4
5
VNQ7040AY
Electrical specification
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
ISENSEH
Parameter
Test conditions
MultiSense
output current in
fault condition
VCC = 13 V; VSENSE = 5 V
Min.
Typ.
Max.
Unit
7
20
30
mA
MultiSense timings (Chip Temperature Sense mode - see Figure 6: "Multisense timings (chip
temperature and VCC sense mode)")
tDSENSE3H
VSENSE_TC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V;
VSEL0 = VSEL1 = 0 V;
VSEL2 = 5 V; RSENSE = 1 kΩ
60
µs
tDSENSE3L
VSENSE_TC disable
delay time from
falling edge of
SEn
VSEn = 5 V to 0 V;
VSEL0 = VSEL1 = 0 V;
VSEL2 = 5 V; RSENSE = 1 kΩ
20
µs
MultiSense timings (VCC Voltage Sense mode - see Figure 6: "Multisense timings (chip
temperature and VCC sense mode)")
tDSENSE4H
VSENSE_VCC
settling time from
rising edge of
SEn
VSEn = 0 V to 5 V;
VSEL0 = VSEL1 = VSEL2 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE4L
VSENSE_VCC
disable delay
time from falling
edge of SEn
VSEn = 5 V to 0 V;
VSEL0 = VSEL1 = VSEL2 = 5 V;
RSENSE = 1 kΩ
20
µs
MultiSense Timings (Multiplexer transition times) (3)
tD_XtoY
MultiSense
transition delay
from ChX to ChY
VIN2 = 5 V; VIN3 = 5 V;
VSEn = 5 V; VSEL0 = 0 V to 5 V;
VSEL1 = 5 V; VSEL2 = 0 V;
IOUT2 = 0 A; IOUT3 = 2.5 A;
RSENSE = 1 kΩ
20
µs
tD_CStoTC
MultiSense
transition delay
from current
sense to TC
sense
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = VSEL2 = 0 V
to 5 V;
IOUT0 = 1.25 A; RSENSE = 1 kΩ
60
µs
tD_TCtoCS
MultiSense
transition delay
fromTC sense to
current sense
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V;
VSEL1 = VSEL2 = 5 V to 0 V;
IOUT0 = 1.25 A; RSENSE = 1 kΩ
20
µs
tD_CStoVCC
MultiSense
transition delay
from current
sense to VCC
sense
VIN2 = 5 V; VSEn = 5 V;
VSEL0 = 5 V;
VSEL1 = 5 V; VSEL2 = 0 V to 5 V;
IOUT2 = 1.25 A; RSENSE = 1 kΩ
60
µs
tD_VCCtoCS
MultiSense
transition delay
from VCC sense to
current sense
VIN2 = 5 V; VSEn = 5 V;
VSEL1 = 5 V;
VSEL0 = VSEL2 = 5 V to 0 V;
IOUT2 = 1.25 A; RSENSE = 1 kΩ
20
µs
DocID027406 Rev 4
13/50
Electrical specification
VNQ7040AY
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
tD_TCtoVCC
MultiSense
transition delay
from TC sense to
VCC sense
Min.
Typ.
Max.
Unit
VSEn = 5 V; VSEL1,2 = 5 V;
VSEL0 = 0 V to 5 V;
RSENSE = 1 kΩ
20
µs
tD_VCCtoTC
MultiSense
transition delay
from VCC sense to
TC sense
VSEn = 5 V; VSEL1,2 = 5 V;
VSEL0 = 5 V to 0 V;
RSENSE = 1 kΩ
20
µs
tD_CStoVSENSEH
MultiSense
transition delay
from stable
current sense on
ChX to VSENSEH on
ChY
VIN0 = 5 V; VIN1 = 0 V;
VOUT1 > 4 V; VSEn = 5 V;
VSEL2 = 0 V; VSEL1 = 0 V;
VSEL0 = 0 V to 5 V;
IOUT0 = 2.5 A;
RSENSE = 1 kΩ
60
µs
Notes:
(1)Parameter
(2)V
CC
guaranteed by design and characterization; not subject to production test.
sensing and TC sensing are referred to GND potential.
(3)Transition
delay is measured up to +/- 10% of final conditions.
Figure 4: Switching times and Pulse skew
twon
VOUT
twoff
Vcc
80% Vcc
ON
OFF
dVOUT/dt
dVOUT/dt
20% Vcc
t
INPUT
td(off)
td(on)
tpLH
tpHL
t
14/50
DocID027406 Rev 4
VNQ7040AY
Electrical specification
Figure 5: MultiSense timings (current sense mode)
IN1
High
SEn
Low
High
SEL0
Low
High
SEL1
Low
High
SEL2
Low
IOUT1
Current Sense
tDSENSE2H
tDSENSE1 L
tDSENSE1H
tDSENSE2 L
Figure 6: Multisense timings (chip temperature and VCC sense mode)
DocID027406 Rev 4
15/50
Electrical specification
VNQ7040AY
Figure 7: TDSKON
VINPU T
VOU T
VOU T > VOL
MultiSense
TDSTKON
GAPG2609141140CFT
2.3.2
Bulb mode (default)
Table 9: Power section in Bulb Mode
7 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified
Symbol
Parameter
Test conditions
Min.
Max.
Unit
IOUT = 2.5 A;
Tj = 150°C
80
mΩ
IOUT = 2.5 A;
VCC = 4 V; Tj = 25°C
60
IOUT = 2.5 A;
Tj = 25°C
RON_0,1,2,3_BULB
On-state resistance in Bulb
Mode Ch0, Ch1, Ch2 and
Ch3
40
RON_REV_0,1,2,3
On-state resistance in
Reverse Battery Ch0, Ch1,
Ch2 and Ch3
VCC = -13V;
IOUT = -2.5A;
Tj = 25°C
DC short circuit current in
Bulb Mode Ch0, Ch1, Ch2
and Ch3
VCC = 13 V
ILIMH_0,1,2,3_BULB(1)
ILIML_0,1,2,3_BULB
Short circuit current
during thermal cycling in
Bulb Mode Ch0, Ch1, Ch2
and Ch3
VCC = 13 V;
TR < Tj < TTSD
9
VON_0,1,2,3_BULB
Output voltage drop
limitation in Bulb Mode Ch0,
Ch1, Ch2 and Ch3
IOUT = 0.25 A
20
4 V < VCC < 18 V
mΩ
40
24
34
(2)
48
48
A
Notes:
16/50
Typ.
(1)Parameter
guaranteed by an indirect test sequence.
(2)Parameter
guaranteed by design and characterization; not subject to production test.
DocID027406 Rev 4
mV
VNQ7040AY
Electrical specification
Table 10: Switching in Bulb Mode
VCC = 13 V; -40 °C < Tj < 150 °C, unless otherwise specified
Symbol
Test
conditions
Parameter
Min.
Typ.
Max.
Unit
Channel 0, 1, 2 and 3
td(on)_0,1,2,3(1)
Turn-on delay time at
Tj = 25 °C
RL = 5.2 Ω
10
60
145
td(off)_0,1,2,3(1)
Turn-off delay time at
Tj = 25 °C
RL = 5.2 Ω
10
50
100
(dVOUT/dt)on_0,1,2,3(1)
Turn-on voltage slope at
Tj = 25 °C
RL = 5.2 Ω
0.1
0.5
0.7
(dVOUT/dt)off_0,1,2,3(1)
Turn-off voltage slope at
Tj = 25 °C
RL = 5.2 Ω
0.1
0.5
0.7
WON_0,1,2,3
Switching energy losses at
turn-on (twon)
RL = 5.2 Ω
—
0.2
WOFF_0,1,2,3
Switching energy losses at
turn-off (twoff)
RL = 5.2 Ω
—
Differential pulse skew
(tPHL - tPLH)
RL = 5.2 Ω
-100
tSKEW_0,1,2,3(1)
µs
V/µs
0.52
(2)
mJ
0.2
0.5(2)
mJ
-15
35
µs
Typ.
Max.
Unit
35
%
Notes:
(1)See Figure 4: "Switching times and Pulse skew" .
(2)Parameter
guaranteed by design and characterization, not subject to production test.
Table 11: MultiSense in Bulb Mode
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Current sense characteristics
Channel 0, 1, 2 and 3
KOL_CH0,1_B
IOUT/ISENSE
IOUT = 10 mA;
VSENSE = 0.5 V;
VSEn = 5 V
430
KOL_CH2,3_B
IOUT/ISENSE
IOUT = 10 mA;
VSENSE = 0.5 V;
VSEn = 5 V
430
dKcal/Kcal(1)(2)
Current sense ratio drift at
calibration point
ICAL = 30 mA;
IOUT = 10 mA to 50 mA;
VSENSE = 0.5 V;
VSEn = 5 V
-35
KLED_CH0,1_B
IOUT/ISENSE
IOUT = 0.05 A;
VSENSE = 0.5 V;
VSEn = 5 V
720
1440
2160
KLED_CH2,3_B
IOUT/ISENSE
IOUT = 0.05 A;
VSENSE = 0.5 V;
VSEn = 5 V
720
1440
2160
DocID027406 Rev 4
17/50
Electrical specification
VNQ7040AY
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
K0_CH0,1_B
IOUT/ISENSE
IOUT = 0.25 A;
VSENSE = 0.5 V;
VSEn = 5 V
930
1550
2170
K0_CH2,3_B
IOUT/ISENSE
IOUT = 0.25 A;
VSENSE = 0.5 V;
VSEn = 5 V
930
1550
2170
dK0/K0(1)(2)
Current sense ratio drift
IOUT = 0.25 A;
VSENSE = 0.5 V;
VSEn = 5 V
-20
K1_CH0,1_B
IOUT/ISENSE
IOUT = 0.5 A;
VSENSE = 4 V;
VSEn = 5 V
1110
1590
2070
K1_CH2,3_B
IOUT/ISENSE
IOUT = 0.5 A;
VSENSE = 4 V;
VSEn = 5 V
1085
1550
2015
dK1/K1(1)(2)
Current sense ratio drift
IOUT = 0.5 A;
VSENSE = 4V; VSEn = 5 V
K2_CH0,1_B
IOUT/ISENSE
IOUT = 2 A;
VSENSE = 4 V;
VSEn = 5 V
1160
1450
1740
K2_CH2,3_B
IOUT/ISENSE
IOUT = 2 A;
VSENSE = 4 V;
VSEn = 5 V
1130
1410
1690
dK2/K2(1)(2)
Current sense ratio drift
IOUT = 2 A;
VSENSE = 4 V;
VSEn = 5 V
-10
K3_CH0,1_B
IOUT/ISENSE
IOUT = 6 A;
VSENSE = 4 V;
VSEn = 5 V
1295
1440
1585
K3_CH2,3_B
IOUT/ISENSE
IOUT = 6 A;
VSENSE = 4 V;
VSEn = 5 V
1260
1400
1540
dK3/K3(1)(2)
Current sense ratio drift
IOUT = 6 A;
VSENSE = 4 V;
VSEn = 5 V
-5
Unit
20
-15
15
10
5
%
%
%
%
MultiSense timings (Current Sense mode see Figure 5: "MultiSense timings (current sense
mode)")
Channel 0, 1, 2 and 3
18/50
tDSENSE1H
Current sense settling time
from rising edge of SEn
VIN = 5 V; VSEn = 0 V to
5 V;
RSENSE = 1 kΩ;
RL = 5.2 Ω
tDSENSE1L
Current sense disable delay
time from falling edge of SEn
VSEn = 5 V to 0 V;
RSENSE = 1 kΩ;
RL = 5.2 Ω
DocID027406 Rev 4
5
60
µs
20
µs
VNQ7040AY
Electrical specification
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Current sense settling time
from rising edge of INPUT
VIN = 0 V to 5 V;
VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 5.2 Ω
ΔtDSENSE2H
Current sense settling time
from rising edge of IOUT
(dynamic response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 5.2 Ω
tDSENSE2L
Current sense turn-off delay
time from falling edge of
INPUT
VIN = 5 V to 0 V;
VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 5.2 Ω
tDSENSE2H
Min.
Typ.
Max.
Unit
100
250
µs
100
µs
250
µs
50
Notes:
(1)Parameter
(2)All
specified by design; not subject to production test.
values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified.
Figure 8: Bulb Mode - IOUT/ISENSE versus IOUT
DocID027406 Rev 4
19/50
Electrical specification
VNQ7040AY
Figure 9: Bulb Mode - current sense precision vs. IOUT
65.0
60.0
55.0
50.0
45.0
40.0
35.0
%
30.0
25.0
20.0
15.0
10.0
5.0
0.0
Current sense uncalibrated precision
Current sense calibrated precision
0
1
2
3
4
5
6
7
IOUT [A]
2.3.3
Electrical characteristics curves - Bulb Mode
Figure 11: Standby current
Figure 10: OFF-state output current
ISTBY [µA]
Iloff [nA]
1
1000
0.9
900
0.8
800
Vcc = 13V
0.7
700
0.6
Off State
Vcc = 13V
Vin = Vout = 0
600
500
0.5
400
0.4
300
0.3
200
0.2
100
0.1
0
0
-100
-50
-25
0
25
50
75
100
125
150
175
-25
0
25
50
T [°C]
T [°C]
20/50
-50
DocID027406 Rev 4
75
100
125
150
175
VNQ7040AY
Electrical specification
Figure 12: IGND(ON) vs. Iout
Figure 13: Logic Input high level voltage
ViH, VFRH, VSELH, VSEnH [V]
IGND(ON) [mA]
12.0
2
1.8
10.0
1.6
1.4
8.0
1.2
Vcc = 13V
Iout0 = Iout1 = 2.5A
6.0
1
0.8
4.0
0.6
0.4
2.0
0.2
0
0.0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
T [°C]
T [°C]
Figure 14: Logic Input low level voltage
Figure 15: High level logic input current
VilL VFRL, VSELL, VSEnL [V]
IiH, IFRH, ISELH, ISEnH [µA]
2
4
1.8
3.5
1.6
3
1.4
2.5
1.2
1
2
0.8
1.5
0.6
1
0.4
0.5
0.2
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
T [°C]
50
75
100
125
150
175
T [°C]
Figure 16: Low level logic input current
Figure 17: Logic Input hysteresis voltage
Vi(hyst), VFR(hyst), VSEL(hyst), VSEn(hyst) [V]
IiL, IFRL, ISELL, ISEnL [µA]
1
3.5
0.9
3
0.8
2.5
0.7
0.6
2
0.5
1.5
0.4
0.3
1
0.2
0.5
0.1
0
0
-50
-25
0
25
50
75
100
125
150
175
T [°C]
-50
-25
0
25
50
75
100
125
150
175
T [°C]
DocID027406 Rev 4
21/50
Electrical specification
VNQ7040AY
Figure 18: FaultRST Input clamp voltage
Figure 19: Undervoltage shutdown
VUSD [V]
VFRCL [V]
8
8
7
7
Iin = 1mA
6
6
5
5
4
4
3
3
2
2
1
Iin = -1mA
1
0
0
-1
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
Figure 20: On-state resistance vs. Tcase
Ron [mOhm]
175
Figure 21: On-state resistance vs. VCC
Ron [mOhm]
100
80
90
70
80
T = 150 °C
60
70
T = 125 °C
50
Iout = 2.5A
Vcc = 13V
60
50
40
T = 25 °C
40
30
T = -40 °C
30
20
20
10
10
0
0
-50
-25
0
25
50
75
100
125
150
175
0
5
10
15
T [°C]
20
25
30
35
40
Vcc [V]
Figure 22: Turn-on voltage slope
Figure 23: Turn-off voltage slope
(dVout/dt)Off [V/µs]
(dVout/dt)On [V/µs]
1
1
0.9
0.9
0.8
0.8
Vcc = 13V
Rl = 5.2Ω
0.7
Vcc = 13V
Rl = 5.2Ω
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
T [°C]
T [°C]
22/50
150
T [°C]
T [°C]
DocID027406 Rev 4
100
125
150
175
VNQ7040AY
Electrical specification
Figure 24: Won vs. Tcase
Figure 25: Woff vs. Tcase
Won [mJ]
Woff [mJ]
1
1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
T [°C]
75
100
125
150
175
T [°C]
Figure 27: OFF-state open-load voltage
detection threshold
Figure 26: ILIMH vs. Tcase
Ilimh [A]
VOL [V]
40
4
35
3.5
3
30
Vcc = 13V
2.5
25
2
20
1.5
15
1
0.5
10
-50
-25
0
25
50
75
100
125
150
175
0
-50
T [°C]
-25
0
25
50
75
100
125
150
175
T [°C]
Figure 28: Vsense clamp vs. Tcase
Figure 29: Vsenseh vs. Tcase
VSENSEH [V]
VSENSE_CL [V]
10
10
9
9
8
8
7
Iin = 1mA
7
6
6
5
5
4
4
3
3
2
2
1
Iin = -1mA
1
0
0
-1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
T [°C]
T [°C]
DocID027406 Rev 4
23/50
Electrical specification
2.3.4
VNQ7040AY
LED Mode (Channel 0 and 1)
Table 12: Switching in LED Mode
VCC = 13 V; -40 °C < Tj < 150 °C, unless otherwise specified
Symbol
Test
conditions
Parameter
Min.
Typ.
Max.
10
65
145
Unit
td(on)_0,1_LED(1)
Turn-on delay time at
Tj = 25 °C
RL = 22.8 Ω
(1)
Turn-off delay time at
Tj = 25 °C
RL = 22.8 Ω
10
40
100
(dVOUT/dt)on_0,1_LED(1)
Turn-on voltage slope at
Tj = 25 °C
RL = 22.8 Ω
0.2
0.5
0.8
(dVOUT/dt)off_0,1_LED(1)
Turn-off voltage slope at
Tj = 25 °C
RL = 22.8 Ω
0.1
0.5
0.7
WON_0,1_LED
Switching energy losses at
turn-on (twon)
RL = 22.8 Ω
—
0.04
0.1 (2)
mJ
WOFF_0,1_LED
Switching energy losses at
turn-off (twoff)
RL = 22.8 Ω
—
0.045
0.11(2)
mJ
Differential Pulse skew (tPHL tPLH)
RL = 22.8 Ω
-100
-25
25
µs
td(off)_0,1_LED
tSKEW_0,1_LED(1)
µs
V/µs
Notes:
(1)See Figure 4: "Switching times and Pulse skew" .
(2)Parameter
guaranteed by design and characterization, not subject to production test.
Table 13: Power section in LED Mode
7 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified
Symbol
Parameter
Test conditions
Min.
Max.
Unit
IOUT = 0.57 A;
Tj = 150°C
280
mΩ
IOUT = 0.57 A;
VCC = 5 V; Tj = 25°C
210
IOUT = 0.57 A;
Tj = 25°C
On-state resistance in LED
Mode Ch0 and Ch1
RON_0,1_LED
140
DC short circuit current in Bulb
Mode Ch0 and Ch1
VCC = 13 V
ILIML_0,1_LED
Short circuit current during
thermal cycling in Bulb Mode
Ch0 and Ch1
VCC = 13 V;
TR < Tj < TTSD
2
VON_0,1_LED
Output voltage drop limitation
in LED Mode Ch0 and Ch1
IOUT = 0.07 A
20
ILIMH_0,1_LED(1)
4 V < VCC < 18 V
5.5
8
(2)
11
A
Notes:
24/50
Typ.
(1)Parameter
guaranteed by an indirect test sequence.
(2)Parameter
guaranteed by design and characterization; not subject to production test.
DocID027406 Rev 4
mV
VNQ7040AY
Electrical specification
Table 14: MultiSense in LED Mode
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
IOUT/ISENSE
IOUT = 0.01 A;
VSENSE = 0.5 V;
VSEn = 5 V
120
Current sense ratio drift at
calibration point
Ical = 17.5 mA;
IOUT = 10 mA to 25 mA;
VSENSE = 0.5 V;
VSEn = 5 V
-30
IOUT/ISENSE
IOUT = 0.025 A;
VSENSE = 0.5 V;
VSEn = 5 V
150
Current sense ratio drift
IOUT = 0.025 A;
VSENSE = 0.5 V;
VSEn = 5 V
-25
K0_CH0,1_L
IOUT/ISENSE
IOUT = 0.15 A;
VSENSE = 4 V;
VSEn = 5 V
240
dK0/K0(1)(2)
Current sense ratio drift
IOUT = 0.15 A;
VSENSE = 4 V;
VSEn = 5 V
-15
K1_CH0,1_L
IOUT/ISENSE
IOUT = 0.7 A;
VSENSE = 4 V;
VSEn = 5 V
300
dK1/K1(1)(2)
Current sense ratio drift
IOUT = 0.7 A;
VSENSE = 4 V;
VSEn = 5 V
-8
KOL
dKcal/Kcal(1)(2)
KLED
dKLED/KLED(1)(2)
Typ.
380
Max.
Unit
30
%
610
25
405
570
15
380
%
%
460
8
%
MultiSense timings (Current Sense mode - see Figure 5: "MultiSense timings (current sense
mode)")
tDSENSE1H
Current sense settling time
from rising edge of SEn
VIN = 5 V;
VSEn = 0 V to 5 V;
RSENSE = 1 kΩ;
RL = 22.8 Ω
tDSENSE1L
Current sense disable delay
time from falling edge of
SEn
VSEn = 5 V to 0 V;
RSENSE = 1 kΩ;
RL = 22.8 Ω
tDSENSE2H
Current sense settling time
from rising edge of INPUT
60
µs
20
µs
VIN = 0 V to 5 V;
VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 22.8 Ω
250
µs
ΔtDSENSE2H
Current sense settling time
from rising edge of IOUT
(dynamic response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 22.8 Ω
100
µs
tDSENSE2L
Current sense turn-off delay
time from falling edge of
INPUT
VIN = 5 V to 0 V;
VSEn = 5 V;
RSENSE = 1 kΩ;
RL = 22.8 Ω
250
µs
5
50
Notes:
DocID027406 Rev 4
25/50
Electrical specification
(1)Parameter
(2)All
VNQ7040AY
specified by design; not subject to production test.
values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified.
Figure 30: LED Mode - IOUT/ISENSE versus IOUT
800
Max_CH0,1
700
Min_CH0,1
600
Typ_CH0,1
K-factor
500
400
300
200
100
0
0
0.2
0.4
IOUT [A]
0.6
0.8
Figure 31: LED Mode - current sense precision vs. IOUT
65.0
60.0
55.0
50.0
45.0
40.0
35.0
%
30.0
25.0
20.0
15.0
10.0
5.0
0.0
Current sense uncalibrated precision
Current sense calibrated precision
0
26/50
0.2
0.4
IOUT [A]
DocID027406 Rev 4
0.6
0.8
VNQ7040AY
2.3.5
Electrical specification
Electrical characteristics curves - LED mode
Figure 32: On-state resistance vs. Tcase
Ron [mOhm]
Ron [mOhm]
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
Iout = 0.57A
Vcc = 13V
-50
Figure 33: On-state resistance vs. VCC
-25
0
25
50
75
100
125
150
T = 150 °C
T = 125 °C
T = 25 °C
T = -40 °C
0
175
5
10
15
20
25
30
35
40
Vcc [V]
T [°C]
Figure 34: Turn-on voltage slope
Figure 35: Turn-off voltage slope
(dVout/dt)On [V/µs]
(dVout/dt)Off [V/µs]
1
1
0.9
0.9
0.8
0.8
Vcc = 13V
Rl = 22.8Ω
0.7
Vcc = 13V
Rl = 22.8Ω
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
T [°C]
75
100
125
150
175
150
175
T [°C]
Figure 36: Won vs. Tcase
Figure 37: Woff vs. Tcase
Woff [mJ]
Won [mJ]
1
1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-50
-25
0
25
50
75
100
125
150
175
T [°C]
-50
-25
0
25
50
75
100
125
T [°C]
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Electrical specification
VNQ7040AY
Figure 38: ILIMH vs. Tcase
Ilimh [A]
20
15
Vcc = 13V
10
5
0
-50
-25
0
25
50
75
100
125
150
175
T [°C]
2.3.6
Truth tables
Table 15: Truth table
Mode
Standby
Conditions
All logic inputs low
Nominal load
connected;
Tj < 150°C
Normal
INX
FR
SEn
SELX
OUTX
MultiSense
L
L
L
L
L
Hi-Z
L
X
L
See (1)
H
L
H
See (1)
Outputs configured for
auto-restart
H
H
H
See (1)
Outputs configured for
Latch-off
L
See (1)
H
See (1)
Output cycles with
temperature hysteresis
L
See (1)
Output latches-off
L
L
Hi-Z
Hi-Z
Re-start when
VCC > VUSD +
VUSDhyst (rising)
H
See (1)
H
See (1)
< 0V
See (1)
Overload or short to
GND causing:
Tj > TTSD or
ΔTj > ΔTj_SD
L
X
H
L
H
H
Under-voltage
VCC < VUSD (falling)
X
X
OFF-state
diagnostics
Short to VCC
L
X
Open load
L
X
Negative output
voltage
Inductive loads turn
off
L
X
Overload
See (1)
See (1)
X
X
See (1)
See (1)
Notes:
(1)Refer
28/50
to Table 16: "MultiSense multiplexer addressing"
DocID027406 Rev 4
Comments
Low quiescent current
consumption
External pull-up
VNQ7040AY
Electrical specification
Table 16: MultiSense multiplexer addressing
SEn
SEL2
SEL1
SEL0
MultiSense output
MUX
channel
Normal mode
Overload
OFF-state
diag. (1)
Negative
output
L
X
X
X
Hi-Z
H
L
L
L
Channel 0
diagnostic
ISENSE =
1/K * IOUT0
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
L
L
H
Channel 1
diagnostic
ISENSE =
1/K * IOUT1
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
L
H
L
Channel 2
diagnostic
ISENSE =
1/K * IOUT2
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
L
H
H
Channel 3
diagnostic
ISENSE =
1/K * IOUT3
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
H
L
L
TCHIP Sense
VSENSE = VSENSE_TC
H
H
L
H
VCC Sense
VSENSE = VSENSE_VCC
H
H
H
L
TCHIP Sense
VSENSE = VSENSE_TC
H
H
H
H
VCC Sense
VSENSE = VSENSE_VCC
Notes:
(1)In
case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, Multisense
pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX
channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX
channel = channel 0 diagnostic; Mutisense = VSENSEH
Table 17: Bulb/LED Mode Configuration
Configuration
LED1
LED0
Channel 1
Channel 0
L
L
Bulb
Bulb
L
H
Bulb
LED
H
L
LED
Bulb
H
H
LED
LED
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Protections
VNQ7040AY
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of ΔT j_SD. According to the voltage level on the
FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low)
or remains off (FaultRST = High). The protection prevents fast thermal transient effects
and, consequently, reduces thermo-mechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon
as its junction temperature drops to T R (FaultRST = Low) or remains off (FaultRST = High).
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
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VNQ7040AY
4
Application information
Application information
Figure 39: Application diagram
4.1
GND protection network against reverse battery
Figure 40: Simplified internal structure
Vcc
5V
Rprot
INPUT
Rprot
SEn
Rprot
FaultRST
MCU
Dld
OUTPUT
Rprot
Multisense
GND
Rsense
GND
The device does not need any external components to protect the internal logic in case of a
reverse battery condition. The protection is provided by internal structures.
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Application information
VNQ7040AY
In addition, due to the fact that the output MOSFET turns on even in reverse battery mode,
thus providing the same low ohmic path as in regular operating conditions, no additional
power dissipation has to be considered.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 18: "ISO 7637-2 electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 18: ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle /
pulse
repetition time
Pulse duration and
pulse generator
internal impedance
Level
US(1)
1
III
-112 V
500 pulses
0.5 s
2a(3)
III
+55 V
500 pulses
0.2 s
5s
50 µs, 2 Ω
3a
IV
-220 V
1h
90 ms
100
ms
0.1 µs, 50 Ω
3b
IV
+150 V
1h
90 ms
100
ms
0.1 µs, 50 Ω
4 (2)
IV
-7 V
1 pulse
min
max
2 ms, 10 Ω
100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B(3)
40 V
5 pulse
1 min
400 ms, 2 Ω
Notes:
(1)U
S
4.3
is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test
pulse from ISO 7637-2:2004(E).
(3)With
40 V external suppressor referred to ground (-40°C < Tj < 150 °C).
MCU I/Os protection
If a ground protection network is used and negative transients are present on the V CC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R prot) in line both to
prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
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VNQ7040AY
Application information
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(MultiSense) delivering the following signals:
Current monitor: current mirror of channel output current
VCC monitor: voltage propotional to VCC
TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in MultiSense multiplexer
addressing Table.
Figure 41: MultiSense and diagnostic – block diagram
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Application information
4.4.1
VNQ7040AY
Principle of Multisense signal generation
Figure 42: MultiSense block diagram
Current monitor
When current mode is selected via MultiSense, this output is capable of providing:
Current mirror proportional to the load current in normal operation, delivering current
proportional to the load according to a known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage V SENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can
be done using simple equations
Current provided by MultiSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:
34/50
VSENSE is the voltage measurable on RSENSE resistor
ISENSE is the current provided from MultiSense pin in current output mode
DocID027406 Rev 4
VNQ7040AY
Application information
IOUT is the current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying the ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin
which is switched to a “current limited” voltage source, VSENSEH.
In any case, the current sourced by the MultiSense in this condition is limited to I SENSEH.
The typical behavior in case of overload or hard short circuit is shown in Waveforms
section.
Figure 43: Analogue HSD – open-load detection in off-state
DocID027406 Rev 4
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Application information
VNQ7040AY
Figure 44: Open-load / short to VCC condition
VIN
VSENSE
Pull-up connected
VSENSEH
Open-load
VSENSE = 0
VSENSE
Pull-up
disconnected
tDSTKON
Short to VCC
VSENSEH
Table 19: MultiSense pin levels in off-state
Condition
Output
VOUT > VOL
Open-load
VOUT < VOL
4.4.2
Short to VCC
VOUT > VOL
Nominal
VOUT < VOL
MultiSense
SEn
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because a
voltage shift is generated between the device GND and the microcontroller input GND
reference.
Figure 45: "GND voltage shift" shows the link between VMEASURED and the real VSENSE
signal.
36/50
DocID027406 Rev 4
VNQ7040AY
Application information
Figure 45: GND voltage shift
VCC monitor
Battery monitoring channel provides VSENSE = VCC / 8.
Case temperature monitor
Case temperature monitor is capable of providing information about the actual device
temperature. Since a diode is used for temperature sensing, the following equation
describes the link between temperature and output VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C)).
4.4.3
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable that VPU is switched off during the module standby mode in order to avoid
the overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
Equation
DocID027406 Rev 4
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Maximum demagnetization energy (VCC = 16 V)
5
VNQ7040AY
Maximum demagnetization energy (VCC = 16 V)
Figure 46: Maximum turn off current versus inductance
100
I (A)
10
1
VNQ7040AY - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
0.1
0.1
1
10
L (mH)
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DocID027406 Rev 4
100
1000
VNQ7040AY
Package and PCB thermal data
6
Package and PCB thermal data
6.1
PowerSSO-36 thermal data
Figure 47: PowerSSO-36 PC board
DocID027406 Rev 4
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Package and PCB thermal data
VNQ7040AY
Table 20: PCB properties
Dimension
Value
Board finish thickness
1.6 mm +/- 10%
Board dimension
129 mm x 60 mm
Board Material
FR4
Cu thickness (outer layers)
0.070 mm
Cu thickness (inner layers)
0.035 mm
Thermal vias separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Cu thickness on vias
0.025 mm
Footprint dimension
4.1 mm x 6.5 mm
Figure 48: Rthj-amb vs PCB copper area in open box free air condition
RTHjamb
70
RTHjamb
65
60
55
50
45
40
35
30
0
40/50
2
4
DocID027406 Rev 4
6
8
10
VNQ7040AY
Package and PCB thermal data
Figure 49: PowerSSO-36 thermal impedance junction ambient
ZTH (°C/W)
100
Cu=foot print
Cu=2 cm2
Cu=8 cm2
10
4Layer
1
0.1
0.0001
0.001
0.01
0.1
1
10
100
1000
Time (s)
Figure 50: Thermal fitting model of a HSD in PowerSSO-36
DocID027406 Rev 4
41/50
Package and PCB thermal data
VNQ7040AY
Table 21: Thermal parameters
42/50
Area/island (cm2)
FP
R1 = R7 = R9 = R11 (°C/W)
1.8
R2 = R8 = R10 = R12 (°C/W)
1.7
R3 (°C/W)
3.5
2
8
4L
3.5
3.5
2
R4 (°C/W)
8
6
6
4
R5 (°C/W)
20
14
10
2
R6 (°C/W)
30
26
15
7
C1 = C7 = C9 = C11 (W·s/°C)
0.0005
C2 = C8 = C10 = C12 (W·s/°C)
0.01
C3 (W·s/°C)
0.1
0.1
0.1
0.1
C4 (W·s/°C)
0.5
0.8
0.8
0.8
C5 (W·s/°C)
1
2
3
10
C6 (W·s/°C)
3
5
9
18
DocID027406 Rev 4
VNQ7040AY
7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
PowerSSO-36 package information
Figure 51: PowerSSO-36 package outline
BOTTOM VIEW
TOP VIEW
SECTION A-A
SECTION B-B
GAPG2508150825CF T
Table 22: PowerSSO-36 mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
Max.
Θ
0°
8°
Θ1
5°
10°
Θ2
0°
A
2.15
2.45
A1
0.00
0.10
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Package information
VNQ7040AY
Dimensions
Ref.
Millimeters
Min.
A2
2.15
b
0.18
b1
0.13
c
0.23
c1
0.20
D
D1
Typ.
2.35
0.32
0.25
0.20
0.30
10.30 BSC
6.90
7.50
3.65
D3
4.30
e
0.50 BSC
E
10.30 BSC
E1
7.50 BSC
4.30
5.20
E3
2.30
E4
2.90
G1
1.20
G2
1.00
G3
0.80
h
0.30
L
0.55
0.40
0.70
L1
1.40 REF
L2
0.25 BSC
N
36
R
0.30
R1
0.20
S
0.25
Tolerance of form and position
44/50
0.30
0.32
D2
E2
Max.
aaa
0.20
bbb
0.20
ccc
0.10
ddd
0.20
eee
0.10
fff
0.20
ggg
0.15
DocID027406 Rev 4
0.85
VNQ7040AY
7.2
Package information
PowerSSO-36 packing information
Figure 52: PowerSSO-36 reel 13"
Table 23: Reel dimensions
Description
Value(1)
Base quantity
1000
Bulk quantity
1000
A (max)
330
B (min)
1.5
C (± 0.2)
13
F
20.2
G (+2 / -0)
24.4
N (min)
100
T (max)
30.4
Notes:
(1)All
dimensions are in mm.
DocID027406 Rev 4
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Package information
VNQ7040AY
Figure 53: PowerSSO-36 carrier tape
Table 24: PowerSSO-36 carrier tape dimensions
Description
Value(1)
A0
10.90 ± 0.10
B0
10.80 ± 0.10
K0
2.75 ± 0.10
K1
2.45 ± 0.10
D0
1.50 (+0.10 / -0)
D1
1.60 ± 0.10
P0
4.00 ± 0.10
P1
12.00 ± 0.10
P2
2.00 ± 0.10
P10
40.00 ± 0.20
E
1.75 ± 0.10
F
11.50 ± 0.10
W
24.00 ± 0.30
T
0.30 ± 0.05
Notes:
(1)All
46/50
dimensions are in mm.
DocID027406 Rev 4
VNQ7040AY
Package information
Figure 54: PowerSSO-36 schematic drawing of leader and trailer tape
7.3
PowerSSO-36 marking information
Figure 55: PowerSSO-36 marking information
Engineering Samples: Parts marked as “&” are not yet qualified and therefore not
approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of
these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a
qualification activity.
Commercial Samples: fully qualified parts from ST standard production with no
usage restrictions.
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Order codes
8
VNQ7040AY
Order codes
Table 25: Device summary
Order codes
Package
Tape and reel
PowerSSO-36
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VNQ7040AYTR
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VNQ7040AY
9
Revision history
Revision history
Table 26: Document revision history
Date
Revision
Changes
21-Oct-2015
1
Initial release.
02-May-2016
2
Added “AEC-Q100 qualified” in Features
Upated Table 4: "Thermal data"
Upated Table 8: "MultiSense"
Updated Section 6: "Package and PCB thermal data"
15-Jul-2016
3
Updated Figure 52: "PowerSSO-36 reel 13""and Table 23: "Reel
dimensions"
21-Dec-2017
4
Updated Table 10: "Switching in Bulb Mode" and Table 12:
"Switching in LED Mode"
DocID027406 Rev 4
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VNQ7040AY
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
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