VNQ7050AJTR-E

VNQ7050AJ Quad channel high-side driver with CurrentSense analog feedback for automotive applications Datasheet - production data − − − − − Features Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 50 mΩ Current limitation (typ) ILIMH 27 A Stand-by current (max) ISTBY 0.5 µA • • • • Automotive qualified General − Quad channel smart high-side driver with CS analog feedback − Very low standby current − Compatible with 3 V and 5 V CMOS outputs CurrentSense diagnostic functions − Analog feedback of load current with high precision proportional current mirror − Overload and short to ground (power limitation) indication − Thermal shutdown indication − OFF-state open-load detection − Output short to VCC detection − Sense enable/disable Protections − Undervoltage shutdown − Overvoltage clamp − Load current limitation June 2015 Applications • • All types of Automotive resistive, inductive and capacitive loads Specially intended for Automotive Signal Lamps (up to P27W or SAE1156 or LED Rear Combinations) Description The device is a quad channel high-side driver manufactured using ST proprietary VIPower® M0-7 technology and housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. DocID027405 Rev 1 This is information on a product in full production. Self limiting of fast thermal transients Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin Loss of ground and loss of VCC Reverse battery with external components Electrostatic discharge protection 1/42 www.st.com Contents VNQ7050AJ Contents 1 Block diagram and pin description ................................................ 5 2 Electrical specification.................................................................... 7 3 4 2.1 Absolute maximum ratings ................................................................ 7 2.2 Thermal data ..................................................................................... 8 2.3 Main electrical characteristics ........................................................... 8 2.4 Waveforms ...................................................................................... 16 2.5 Electrical characteristics curves ...................................................... 19 Protections..................................................................................... 23 3.1 Power limitation ............................................................................... 23 3.2 Thermal shutdown........................................................................... 23 3.3 Current limitation ............................................................................. 23 3.4 Negative voltage clamp ................................................................... 23 Application information ................................................................ 24 4.1 GND protection network against reverse battery............................. 24 4.1.1 Diode (DGND) in the ground line ..................................................... 25 4.2 Immunity against transient electrical disturbances .......................... 25 4.3 MCU I/Os protection........................................................................ 25 4.4 CS - analog current sense .............................................................. 26 4.4.1 Principle of CurrentSense signal generation .................................... 27 4.4.2 Short to VCC and OFF-state open-load detection ........................... 29 5 Maximum demagnetization energy (VCC = 16 V) ........................ 31 6 Package and PCB thermal data .................................................... 32 6.1 7 8 9 2/42 PowerSSO-16 thermal data ............................................................ 32 Package information ..................................................................... 35 7.1 PowerSSO-16 package information ................................................ 35 7.2 PowerSSO-16 packing information ................................................. 37 7.3 PowerSSO-16 marking information ................................................. 39 Order codes ................................................................................... 40 Revision history ............................................................................ 41 DocID027405 Rev 1 VNQ7050AJ List of tables List of tables Table 1: Pin functions ................................................................................................................................. 5 Table 2: Suggested connections for unused and not connected pins ........................................................ 6 Table 3: Absolute maximum ratings ........................................................................................................... 7 Table 4: Thermal data ................................................................................................................................. 8 Table 5: Power section ............................................................................................................................... 8 Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified) ................................... 9 Table 7: Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C)................................................................ 10 Table 8: Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C) ................................................................. 10 Table 9: CurrentSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) ............................................................. 11 Table 10: Truth table ................................................................................................................................. 15 Table 11: Current sense multiplexer addressing ...................................................................................... 16 Table 12: ISO 7637-2 - electrical transient conduction along supply line................................................. 25 Table 13: CurrentSense pin levels in off-state .......................................................................................... 29 Table 14: PCB properties ......................................................................................................................... 32 Table 15: Thermal parameters ................................................................................................................. 34 Table 16: PowerSSO-16 mechanical data................................................................................................ 35 Table 17: Reel dimensions ....................................................................................................................... 37 Table 18: PowerSSO-16 carrier tape dimensions .................................................................................... 38 Table 19: Device summary ....................................................................................................................... 40 Table 20: Document revision history ........................................................................................................ 41 DocID027405 Rev 1 3/42 List of figures VNQ7050AJ List of figures Figure 1: Block diagram .............................................................................................................................. 5 Figure 2: Configuration diagram (top view)................................................................................................. 6 Figure 3: Current and voltage conventions ................................................................................................. 7 Figure 4: Switching times and Pulse skew ............................................................................................... 14 Figure 5: Current sense timings (current sense mode) ............................................................................ 14 Figure 6: TDSKON .................................................................................................................................... 15 Figure 7: Latch functionality - behavior in hard short circuit condition (TAMB