VNQ810MTR-E

VNQ810M-E QUAD CHANNEL HIGH SIDE DRIVER Table 1. General Features Type VNQ810M-E Figure 1. Package RDS(on) Iout VCC 150mΩ (*) 0.6A (*) 36V ) s ( ct (*) Per each channel CMOS COMPATIBLE INPUTS ■ OPEN DRAIN STATUS OUTPUTS ■ ON STATE OPEN LOAD DETECTION ■ OFF STATE OPEN LOAD DETECTION ■ SHORTED LOAD PROTECTION ■ UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN ■ PROTECTION AGAINST LOSS OF GROUND ■ VERY LOW STAND-BY CURRENT ■ REVERSE BATTERY PROTECTION (**) ■ IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE ■ ) (s u d o r P e t e l o s b O t c u DESCRIPTION The VNQ810M-E is a quad HSD formed by assembling two VND810M-E chips in the same SO-28 package. The VNQ810M-E is a monolithic device made by using STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The current limitation threshold is aimed at detecting the 21W/12V standard bulb as an overload fault. The device detects open load condition both in on and off state . Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection. od r P e SO-28 (DOUBLE ISLAND) t e l o s b O Table 2. Order Codes Package SO-28 Tube VNQ810M-E Tape and Reel VNQ810MTR-E Note: (**) See application schematic at page 10 Rev. 1 October 2004 1/21 VNQ810M-E Figure 2. Block Diagram VCC1,2 Vcc OVERVOLTAGE CLAMP UNDERVOLTAGE GND1,2 ) s ( ct CLAMP 1 INPUT1 DRIVER 1 e t e l CURRENT LIMITER 1 DRIVER 2 LOGIC OVERTEMP. 1 OPENLOAD ON 1 INPUT2 OPENLOAD OFF 1 ) (s STATUS2 t c u OVERTEMP. 2 GND3,4 od r P e Vcc CLAMP let o s b OUTPUT2 CURRENT LIMITER 2 OPENLOAD ON 2 OPENLOAD OFF 2 VCC3,4 OVERVOLTAGE UNDERVOLTAGE CLAMP 3 OUTPUT3 INPUT3 O b O so OUTPUT1 o r P CLAMP 2 STATUS1 du DRIVER 3 CLAMP 4 STATUS3 CURRENT LIMITER 3 LOGIC DRIVER 4 OUTPUT4 OVERTEMP. 3 OPENLOAD ON 3 CURRENT LIMITER 4 INPUT4 OPENLOAD OFF 3 OPENLOAD ON 4 STATUS4 OPENLOAD OFF 4 OVERTEMP. 4 2/21 VNQ810M-E Table 3. Absolute Maximum Ratings Symbol VCC Parameter DC Supply Voltage Value Unit 41 V - VCC Reverse DC Supply Voltage -0.3 V - Ignd DC Reverse Ground Pin Current -200 mA IOUT DC Output Current Internally Limited A -6 A DC Input Current +/- 10 mA DC Status Current +/- 10 mA - IOUT IIN ISTAT Reverse DC Output Current Electrostatic Discharge R=1.5KΩ; C=100pF) VESD (Human Body 4000 - INPUT - STATUS Tstg (L=310mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=0.9A) Junction Operating Temperature Storage Temperature ) (s b O V 174 mJ 6.25 W Internally Limited °C -55 to 150 °C e t e l so Power dissipation (per island) at Tlead=25°C V Pr 5000 Maximum Switching Energy Tj u d o 5000 - VCC Ptot V 4000 - OUTPUT EMAX ) s ( ct Model: V Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins od t c u r P e s b O t e l o VCC1,2 1 28 GND 1,2 VCC1,2 OUTPUT1 INPUT1 OUTPUT1 STATUS1 OUTPUT1 STATUS2 OUTPUT2 INPUT2 OUTPUT2 VCC1,2 OUTPUT2 VCC3,4 OUTPUT3 GND 3,4 OUTPUT3 INPUT3 OUTPUT3 STATUS3 OUTPUT4 STATUS4 OUTPUT4 OUTPUT4 INPUT4 VCC3,4 14 Connection / Pin Status Floating X To Ground 15 N.C. X X Output X VCC3,4 Input X Through 10KΩ resistor 3/21 VNQ810M-E Figure 4. Current and Voltage Conventions IS3,4 IS1,2 VCC3,4 VCC3,4 VCC1,2 VF1 (*) VCC1,2 IIN1 INPUT1 ISTAT1 VIN1 IIN2 VSTAT1 VIN4 OUTPUT3 IOUT4 INPUT4 ISTAT4 OUTPUT4 STATUS4 GND3,4 VSTAT4 Symbol r P e IGND1,2 t e l o ct Parameter du u d o s b O (*) V Fn = VCCn - VOUTn during reverse battery condition ) (s VOUT3 VOUT4 GND1,2 IGND3,4 Table 4. Thermal Data (Per island) ) s ( ct VOUT2 IOUT3 STATUS3 IIN4 VSTAT3 OUTPUT2 INPUT3 ISTAT3 VIN3 VOUT1 IOUT2 STATUS2 IIN3 VSTAT2 OUTPUT1 INPUT2 ISTAT2 VIN2 IOUT1 STATUS1 Value Unit Rthj-lead Thermal Resistance Junction-lead per chip Rthj-amb Thermal Resistance Junction-ambient (one chip ON) 60 (1) 44 (2) °C/W Rthj-amb Thermal Resistance Junction-ambient (two chips ON) 46 (1) 31 (2) °C/W e t e ol o r P 20 °C/W Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35µm thick) connected to all V CC pins. Horizontal mounting and no artificial air flow Note: 2. When mounted on a standard single-sided FR-4 board with 6cm 2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow s b O 4/21 VNQ810M-E ELECTRICAL CHARACTERISTICS (8V TTSD) L Overtemperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L Output Voltage > VOL L H H H Output Current < IOL L H L H ) (s VOUT > VOL VINn IOUT < IOL t c u d o r VSTATn P e t e l o tDOL(off) du e t e ol Figure 5. s b O OPENLOAD STATUS TIMING (with external pull-up) ) s ( ct H H o r P L H H L OVERTEMP STATUS TIMING Tj > TTSD VINn VSTATn tSDL tSDL tDOL(on) s b O 7/21 VNQ810M-E Figure 6. Switching time Waveforms vOUTn 90% 80% dVOUT/dt(off) dVOUT/dt(on) ) s ( ct 10% t VINn td(on) u d o td(off) r P e t e l o ) (s t s b O Table 13. Electrical Transient Requirements On VCC Pin ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 e t e ol s b O ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E 8/21 ct du I o r P -25 V +25 V -25 V +25 V -4 V +26.5 V I C C C C C C II TEST LEVELS III IV -50 V +50 V -50 V +50 V -5 V +46.5 V -75 V +75 V -100 V +75 V -6 V +66.5 V -100 V +100 V -150 V +100 V -7 V +86.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E Delays and Impedance 2 ms 10 Ω 0.2 ms 10 Ω 0.1 µs 50 Ω 0.1 µs 50 Ω 100 ms, 0.01 Ω 400 ms, 2 Ω IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. VNQ810M-E Figure 7. Waveforms NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn ) s ( ct UNDERVOLTAGE VUSDhyst VCC VUSD u d o INPUTn OUTPUT VOLTAGEn STATUSn r P e undefined t e l o OVERVOLTAGE VCC>VOL VCCVOL VOL OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn OVERTEMPERATURE Tj TTSD TR INPUTn OUTPUT CURRENTn STATUSn 9/21 VNQ810M-E Figure 8. Application Schematic +5V +5V +5V VCC1,2 VCC3,4 Rprot STATUS1 Rprot INPUT1 ) s ( ct Dld Rprot STATUS2 Rprot INPUT2 Rprot STATUS3 µC Rprot OUTPUT1 u d o let OUTPUT2 STATUS4 O ) s ( t c Rprot OUTPUT3 OUTPUT4 INPUT4 du e t e ol o s b INPUT3 Rprot r P e o r P GND1,2 GND3,4 RGND VGND +5V +5V DGND s b O Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2. GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / 2(IS(on)max). 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device’s datasheet. Power Dissipation in RGND (when VCC