VNQ810TR-E

VNQ810-E QUAD CHANNEL HIGH SIDE DRIVER Table 1. General Features Type VNQ810-E Figure 1. Package RDS(on) Iout VCC 160mΩ (*) 3.5A (*) 36V ) s ( ct (*) Per each channel CMOS COMPATIBLE INPUTS ■ OPEN DRAIN STATUS OUTPUTS ■ ON STATE OPEN LOAD DETECTION ■ OFF STATE OPEN LOAD DETECTION ■ SHORTED LOAD PROTECTION ■ UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN ■ PROTECTION AGAINST LOSS OF GROUND ■ VERY LOW STAND-BY CURRENT ■ REVERSE BATTERY PROTECTION (**) ■ IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE ■ ) (s u d o r P e t e l o s b O t c u DESCRIPTION The VNQ810-E is a quad HSD formed by assembling two VND810-E chips in the same SO28 package. The VNQ810-E is a monolithic device made by using STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). od r P e SO-28 (DOUBLE ISLAND) Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both in on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection. t e l o s b O Table 2. Order Codes Package SO-28 Tube VNQ810-E Tape and Reel VNQ810TR-E Note: (**) See application schematic at page 9 Rev. 1 October 2004 1/20 VNQ810-E Figure 2. Block Diagram VCC VCC CLAMP OVERVOLTAGE UNDERVOLTAGE GND CLAMP 1 OUTPUT1 INPUT1 DRIVER 1 CLAMP 2 STATUS1 CURRENT LIMITER 1 ) s ( ct DRIVER 2 LOGIC OVERTEMP. 1 OUTPUT2 OPENLOAD ON 1 u d o CURRENT LIMITER 2 INPUT2 OPENLOAD OFF 1 OPENLOAD ON 2 r P e STATUS2 OPENLOAD OFF 2 t e l o OVERTEMP. 2 Table 3. Absolute Maximum Ratings Symbol )- s ( t c DC Supply Voltage VCC Value Unit 41 V - VCC Reverse DC Supply Voltage - 0.3 V - Ignd DC Reverse Ground Pin Current - 200 mA IOUT DC Output Current Pr Internally Limited A -6 A DC Input Current +/- 10 mA DC Status Current +/- 10 mA 4000 V 4000 V 5000 V 5000 V 23 mJ 6.25 W Internally Limited °C - 55 to 150 °C u d o - IOUT ISTAT o s b VESD Reverse DC Output Current e t e l IIN O Parameter s b O Electrostatic Discharge R=1.5KΩ; C=100pF) (Human Body Model: - INPUT - STATUS - OUTPUT - VCC Maximum Switching Energy EMAX Ptot Tj Tstg 2/20 (L=1.38mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=5A) Power dissipation (per island) at Tlead=25°C Junction Operating Temperature Storage Temperature VNQ810-E Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins VCC1,2 1 OUTPUT1 INPUT1 OUTPUT1 STATUS1 OUTPUT1 STATUS2 OUTPUT2 INPUT2 OUTPUT2 VCC1,2 OUTPUT2 VCC3,4 OUTPUT3 GND 3,4 OUTPUT3 INPUT3 OUTPUT3 STATUS3 OUTPUT4 STATUS4 OUTPUT4 INPUT4 OUTPUT4 14 VCC3,4 Connection / Pin Status Floating X To Ground N.C. X X IS3,4 )- VCC3,4 IIN1 s ( t c ISTAT1 du VSTAT1 VIN2 o r P VSTAT2 s b O ISTAT2 IIN3 ISTAT3 VIN3 e t e ol IIN2 VSTAT3 IIN4 VIN4 ISTAT4 VSTAT4 ) s ( ct u d o VCC3,4 15 Figure 4. Current and Voltage Conventions VIN1 VCC1,2 28 GND 1,2 r P e Output X Input X Through 10KΩ resistor t e l o s b O VCC3,4 IS1,2 VCC1,2 VF1 (*) INPUT1 VCC1,2 IOUT1 STATUS1 OUTPUT1 VOUT1 IOUT2 INPUT2 OUTPUT2 STATUS2 VOUT2 IOUT3 INPUT3 OUTPUT3 STATUS3 VOUT3 IOUT4 INPUT4 OUTPUT4 STATUS4 GND3,4 VOUT4 GND1,2 IGND3,4 IGND1,2 (*) VFn = VCCn - VOUTn during reverse battery condition Table 4. Thermal Data (Per island) Symbol Parameter Rthj-lead Thermal Resistance Junction-lead per chip Rthj-amb Thermal resistance Junction-ambient (one chip ON) Rthj-amb Thermal resistance Junction-ambient (two chips ON) Value Unit 20 °C/W 60 (1) 44 (2) °C/W (1) (2) °C/W 46 31 Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick) connected to all VCC pins.Horizontal mounting and no artificial air flow Note: 2. When mounted on a standard single-sided FR-4 board with 6cm 2 of Cu (at least 35µm thick) connected to all VCC pins.Horizontal mounting and no artificial air flow 3/20 VNQ810-E ELECTRICAL CHARACTERISTICS (8V VOL VINn t c u d o r VSTATn P e t e l o s b O 6/20 IOUT < IOL tDOL(off) du e t e ol Figure 5. s b O OPEN LOAD STATUS TIMING (with external pull-up) ) s ( ct H H o r P H L OVER TEMP STATUS TIMING Tj > TTSD VINn VSTATn tSDL tDOL(on) L H tSDL VNQ810-E Figure 6. Switching time Waveforms VOUTn 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% t VINn td(on) ) s ( ct td(off) u d o r P e ISO T/R 7637/1 Test Pulse I 1 2 3a 3b 4 5 -25 V +25 V -25 V +25 V -4 V +26.5 V s b O 1 2 3a 3b 4 5 CLASS C E s ( t c u d o r P e t e l o ISO T/R 7637/1 Test Pulse )- II I C C C C C C -50 V +50 V -50 V +50 V -5 V +46.5 V t e l o s b O Table 13. Electrical Transient Requirements On VCC Pin t TEST LEVELS III IV -75 V +75 V -100 V +75 V -6 V +66.5 V -100 V +100 V -150 V +100 V -7 V +86.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E Delays and Impedance 2 ms 10 Ω 0.2 ms 10 Ω 0.1 µs 50 Ω 0.1 µs 50 Ω 100 ms, 0.01 Ω 400 ms, 2 Ω IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. 7/20 VNQ810-E Figure 7. Waveforms NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn ) s ( ct UNDERVOLTAGE VUSDhyst VCC VUSD u d o INPUTn OUTPUT VOLTAGEn STATUSn t e l o OVERVOLTAGE VCC>VOV VCCV VV >V OUT OL OUT OL VOL OL OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn OVERTEMPERATURE Tj TTSD TR INPUTn OUTPUT CURRENTn STATUSn 8/20 r P e undefined VNQ810-E Figure 8. Application Schematic +5V +5V +5V VCC1,2 VCC3,4 Rprot STATUS1 Rprot INPUT1 ) s ( ct Dld Rprot STATUS2 Rprot INPUT2 Rprot STATUS3 µC Rprot OUTPUT1 u d o r P e t e l o INPUT3 OUTPUT2 Rprot STATUS4 OUTPUT4 INPUT4 du e t e ol OUTPUT3 O ) s ( t c Rprot bs o r P GND1,2 GND3,4 RGND VGND +5V +5V DGND s b O Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2. GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / 2(IS(on)max). 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the of the device’s datasheet. Power Dissipation in RGND (when VCC