VNQ830MTR-E

VNQ830M-E QUAD CHANNEL HIGH SIDE DRIVER Table 1. General Features Type VNQ830M-E Figure 1. Package RDS(on) Iout VCC 60mΩ (*) 6A (*) 36V ) s ( ct (*) Per each channel CMOS COMPATIBLE INPUTS ■ OPEN DRAIN STATUS OUTPUTS ■ ON STATE OPEN LOAD DETECTION ■ OFF STATE OPEN LOAD DETECTION ■ SHORTED LOAD PROTECTION ■ UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN ■ LOSS OF GROUND PROTECTION ■ VERY LOW STAND-BY CURRENT ■ REVERSE BATTERY PROTECTION (**) ■ IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE u d o r P e ■ t e l o bs O ) s ( t c DESCRIPTION The VNQ830M-E is a quad HSD formed by assembling two VND830M-E chips in the same SO-28 package. The VND830M-E is a monolithic device made by using| STMicroelectronics VIPower M0-3 Technology. The VNQ830M-E is intended for driving any type of multiple loads with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). du e t e ol SO-28 (DOUBLE ISLAND) Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both in on and off state. The openload threshold is aimed at detecting the 5W/12V standard bulb as an openload fault in the on state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection o r P s b O Table 2. Order Codes Package SO-28 Tube VNQ830M-E Tape and Reel VNQ830MTR-E Note: (**) See application schematic at page 10 Rev. 1 October 2004 1/21 VNQ830M-E Figure 2. Block Diagram VCC1,2 Vcc OVERVOLTAGE CLAMP UNDERVOLTAGE GND1,2 ) s ( ct CLAMP 1 INPUT1 DRIVER 1 e t e l CURRENT LIMITER 1 DRIVER 2 LOGIC OVERTEMP. 1 OPENLOAD ON 1 INPUT2 OPENLOAD OFF 1 ) (s STATUS2 t c u OVERTEMP. 2 GND3,4 od r P e Vcc CLAMP let o s b OUTPUT2 CURRENT LIMITER 2 OPENLOAD ON 2 OPENLOAD OFF 2 VCC3,4 OVERVOLTAGE UNDERVOLTAGE CLAMP 3 OUTPUT3 INPUT3 O b O so OUTPUT1 o r P CLAMP 2 STATUS1 du DRIVER 3 CLAMP 4 STATUS3 CURRENT LIMITER 3 LOGIC DRIVER 4 OUTPUT4 OVERTEMP. 3 OPENLOAD ON 3 CURRENT LIMITER 4 INPUT4 OPENLOAD OFF 3 OPENLOAD ON 4 STATUS4 OPENLOAD OFF 4 OVERTEMP. 4 2/21 VNQ830M-E Table 3. Absolute Maximum Ratings Symbol VCC Parameter Value Unit 41 V DC Supply Voltage - VCC Reverse DC Supply Voltage - 0.3 V - IGND DC Reverse Ground Pin Current - 200 mA Internally Limited A -6 A DC Input Current +/- 10 mA DC Status Current +/- 10 mA IOUT - IOUT IIN ISTAT DC Output Current Reverse DC Output Current Electrostatic Discharge R=1.5KΩ; C=100pF) VESD (Human Body 4000 - INPUT - STATUS Tstg Pr 5000 Power Dissipation Tpins=25°C (L=1mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=10.5A) s b O Junction Operating Temperature Storage Temperature ) (s V V V 6.25 W 77 mJ Internally Limited °C - 55 to 150 °C e t e ol Maximum Switching Energy Tj u d o 5000 - VCC EMAX V 4000 - OUTPUT Ptot ) s ( ct Model: Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins t c u od VCC1,2 e t e ol O bs Pr 1 28 VCC1,2 GND 1,2 OUTPUT1 INPUT1 OUTPUT1 STATUS1 OUTPUT1 STATUS2 OUTPUT2 INPUT2 OUTPUT2 VCC1,2 OUTPUT2 VCC3,4 OUTPUT3 GND 3,4 OUTPUT3 INPUT3 OUTPUT3 STATUS3 OUTPUT4 STATUS4 OUTPUT4 INPUT4 OUTPUT4 VCC3,4 Connection / Pin Floating To Ground 14 Status X N.C. X X 15 Output X VCC3,4 Input X Through 10KΩ resistor 3/21 VNQ830M-E Figure 4. Current and Voltage Conventions IS3,4 IS1,2 VCC3,4 VCC3,4 VCC1,2 VF1 (*) VCC1,2 IIN1 INPUT1 ISTAT1 VIN1 VSTAT1 VSTAT3 OUTPUT2 OUTPUT3 IIN4 STATUS3 IOUT4 INPUT4 VIN4 ISTAT4 OUTPUT4 STATUS4 GND3,4 VSTAT4 Symbol Rthj-lead Rthj-amb Rthj-amb ct Parameter Thermal Resistance Junction-lead per chip Thermal Resistance Junction-ambient Thermal Resistance Junction-ambient (two chips ON) r P e u d o u d o r P e IGND1,2 t e l o s b O (*) VFn = VCCn - VOUTn during reverse battery condition ) (s VOUT3 VOUT4 GND1,2 IGND3,4 Table 4. Thermal Data (Per island) ) s ( ct VOUT2 IOUT3 INPUT3 ISTAT3 VIN3 VOUT1 IOUT2 STATUS2 IIN3 VSTAT2 OUTPUT1 INPUT2 ISTAT2 VIN2 IOUT1 STATUS1 IIN2 Value 20 60 (1) 46 (1) 44 (2) 31 (2) Unit °C/W °C/W °C/W Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35µm thick) connected to all V CC pins. Horizontal mounting and no artificial air flow t e l o Note: 2. When mounted on a standard single-sided FR-4 board with 6cm 2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow s b O 4/21 VNQ830M-E ELECTRICAL CHARACTERISTICS (8V VOL VINn t c u d o r VSTATn P e let o s b IOUT < IOL tDOL(off) du e t e ol Figure 5. s b O OPEN LOAD STATUS TIMING (with external pull-up) ) s ( ct H H o r P L H H L OVER TEMP STATUS TIMING Tj > TTSD VINn VSTATn tSDL tSDL tDOL(on) O 7/21 VNQ830M-E Figure 6. Switching time Waveforms VOUTn 90% 80% dVOUT/dt(off) dVOUT /dt(on) ) s ( ct 10% t VINn td(on) u d o td(off) r P e t e l o ) (s s b O t Table 13. Electrical Transient Requirements On VCC Pin ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 e t e ol s b O ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E 8/21 ct du I o r P -25 V +25 V -25 V +25 V -4 V +26.5 V I C C C C C C II TEST LEVELS III IV -50 V +50 V -50 V +50 V -5 V +46.5 V -75 V +75 V -100 V +75 V -6 V +66.5 V -100 V +100 V -150 V +100 V -7 V +86.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E Delays and Impedance 2 ms 10 Ω 0.2 ms 10 Ω 0.1 µs 50 Ω 0.1 µs 50 Ω 100 ms, 0.01 Ω 400 ms, 2 Ω IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. VNQ830M-E Figure 7. Waveforms NORMAL OPERATION INPUTn LOAD VOLTAGEn STATUSn ) s ( ct UNDERVOLTAGE VUSDhyst VCC VUSD u d o INPUTn LOAD VOLTAGEn STATUS r P e undefined t e l o OVERVOLTAGE VCCVOV VCC INPUTn LOAD VOLTAGEn STATUSn ) (s s b O t c u OPEN LOAD with external pull-up d o r INPUTn LOAD VOLTAGEn P e STATUSn t e l o O bs OPEN LOAD without external pull-up INPUTn VOUT>VOL LOAD VOLTAGEn VOL STATUSn Tj TTSD TR OVERTEMPERATURE INPUTn LOAD CURRENTn STATUSn 9/21 VNQ830M-E Figure 8. Application Schematic +5V +5V +5V VCC1,2 VCC3,4 Rprot STATUS1 Rprot INPUT1 ) s ( ct Dld Rprot STATUS2 Rprot INPUT2 Rprot STATUS3 µC Rprot OUTPUT1 u d o let OUTPUT2 STATUS4 O ) s ( t c Rprot OUTPUT3 OUTPUT4 INPUT4 du e t e ol o s b INPUT3 Rprot r P e o r P GND1,2 GND3,4 RGND VGND +5V +5V DGND s b O Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2. GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / 2(IS(on)max). 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device’s datasheet. Power Dissipation in RGND (when VCC