VNQ9080AJ
Datasheet
Quad channel high-side driver with Current Sense analog feedback
for automotive applications
Features
Description
PowerSSO-16
Parameter
Value
Max transient supply voltage
VCC
36 V
Operating voltage range
VCC
4 to 28 V
Typ. on-state resistance (per Ch)
RON
86 mΩ
Current limitation (typ)
ILIMH
13.6 A
Standby current (max)
ISTBY
0.5 µA
•
•
•
•
Product status link
VNQ9080AJ
Product summary
Order code
VNQ9080AJTR
Package
PowerSSO-16
Packing
Tape and reel
•
AEC-Q100 qualified
Extreme low voltage operation for deep cold cranking applications (compliant
with LV124, revision 2013)
General
–
Quad channel smart high-side driver with current sense analog feedback
–
Very low standby current
–
Compatible with 3 V and 5 V CMOS outputs
CurrentSense diagnostic functions
–
Multiplexed analog feedback of: load current with high precision
proportional current mirror
–
Overload and short to ground (power limitation) indication
–
Thermal shutdown indication
–
OFF-state open-load detection (with external pull-up)
–
Output short to VCC detection
–
Sense enable/disable
Protections
–
Undervoltage shutdown
–
Overvoltage clamp
–
Load current limitation
–
Self limiting of fast thermal transients
–
Configurable latch-off on overtemperature or power limitation with
dedicated fault reset pin
–
Loss of ground and loss of VCC
–
–
Reverse battery with external components
Electrostatic discharge protection
Applications
•
•
•
Automotive resistive, inductive and capacitive loads
Protected supply for ADAS systems: radars and sensors
Automotive signal lamp: R10W and LEDs
DS12654 - Rev 6 - August 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
VNQ9080AJ
Description
The device is a quad channel high-side driver manufactured using ST proprietary
VIPower M0-9 technology and housed in PowerSSO-16 package. The device is
designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOScompatible interface, providing protection and diagnostics.
The device integrates advanced protective functions such as load current limitation,
overload active management by power limitation and overtemperature shutdown with
configurable latch-off.
A FaultRST pin unlatches the output in case of fault or disables the latch-off
functionality.
A dedicated multifunction multiplexed analog output pin delivers diagnostic functions
including high precision proportional load current sense, in addition to the detection
of overload and short circuit to ground, short to VCC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to be disabled during the module
low-power mode as well as external sense resistor sharing among similar devices.
DS12654 - Rev 6
page 2/44
VNQ9080AJ
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
VCC
VCC – GND
clamp
Internal supply
Undervoltage
shut-down
Channel 0
control & diagnostic
VCC – OUT
Clamp
Gate driver
IN0
SEn
Logic
Current
limitation
FaultRST
Power limitation
Overtemperature
Open-Load in OFF
Reverse battery
CS
Current
Sense
OUT0
GND
Table 1. Pin functions
Name
VCC
OUTPUT0,1,2,3
GND
INPUT0,1,2,3
DS12654 - Rev 6
Function
Battery connection.
Power output
Ground connection; must be reverse battery protected by an external diode / resistor network.
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs;
controls output switch state.
CS
analog current sense output pin; it delivers a current proportional to the selected load current.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; enables the CS diagnostic pin.
SEL0,1
Active high compatible with 3 V and 5 V CMOS outputs pin; it addresses the CS multiplexer.
FaultRST
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of
fault - if kept low, sets the output to auto-restart mode.
page 3/44
VNQ9080AJ
Block diagram and pin description
Figure 2. Configuration diagram (top view)
PowerSSO-16
OUTPUT0
SEn
INPUT0
GND
FaultRST
INPUT1
N.C.
OUTPUT1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUTPUT3
SEL1
INPUT3
CS
SEL0
INPUT2
N.C.
OUTPUT2
TAB = VCC
GADG010318144RI
Table 2. Suggested connections for unused and not connected pins
Connection/pin
CS
NC
Output
Input
SEn, SELx, FaultRST
Floating
Not allowed
X
X(1)
X
X
To ground
Through 1 kΩ resistor
X
Not allowed
Through 15 kΩ resistor
Through 15 kΩ resistor
1. X: do not care.
DS12654 - Rev 6
page 4/44
VNQ9080AJ
Electrical specification
2
Electrical specification
Figure 3. Current and voltage conventions
IS
VCC
I SEn
I SEL
VFR
FaultRST
I OUT
OUTPUT 0,1,2,3
V OUT
I SENSE
SE n
CS
SEL 0,1
VSEn
VCC
VFn
I FR
VSENSE
I IN
VSEL
INPUT 0,1,2,3
VIN
I GND
GADG2802181245RI
Note:
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3. Absolute maximum ratings may cause permanent damage
to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the operating sections of this specification is not implied. Exposure to the conditions in the table
below for extended periods may affect the device reliability.
Table 3. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
36
-VCC
Reverse DC supply voltage
0.3
VCCJS
Maximum jump start voltage for single pulse short circuit protection
28
V
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT0,1,2,3 DC output current
-IOUT
Reverse DC output current
IIN
ISEn
ISEL0,1
IFR
ISENSE
EMAX
Internally limited
2.2
INPUT0,1,2,3 DC input current
-1 to 10
SEn DC input current
-1 to 3
SEL0,1 DC input current
FaultRST DC input current
A
mA
-1 to 10
CS pin DC output current (VGND = VCC and VSENSE < 0 V)
10
CS pin DC output current in reverse (VCC < 0 V)
-20
Maximum switching energy (single pulse); Tjstart = 150 °C)
V
4
mA
mJ
Electrostatic discharge (JEDEC 22A-114F)
VESD
DS12654 - Rev 6
INPUT0,1,2,3
2000
CS
2000
SEn, SEL0,1, FaultRST
2000
OUTPUT0,1,2,3
4000
V
page 5/44
VNQ9080AJ
Thermal data
Symbol
Value
Unit
VESD
VCC
4000
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Tstg
2.2
Parameter
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
°C
Thermal data
Table 4. Thermal data
Symbol
Parameter
Typ. value
Rthj-board
Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8)(1)(2)
9.5
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)(3)
54.5
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-7)(1)(2)
22.5
Unit
°C/W
1. One channel ON.
2. Device mounted on four-layer 2s2p PCB.
3. Device mounted on two-layer 2s0p PCB with 2 cm2 heatsink copper trace.
DS12654 - Rev 6
page 6/44
VNQ9080AJ
Main electrical characteristics
2.3
Main electrical characteristics
7 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified.
Table 5. Power section
Symbol
Parameter
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
Test conditions
Min.
Typ.
Max.
Unit
4
13
28
V
2.1
2.7
V
4.5
V
VUSDReset Undervoltage shutdown reset
VUSDhyst
Undervoltage shutdown
hysteresis
0.15
IOUT = 0.7 A; Tj = 25 °C
RON
Vclamp
ISTBY
tD_STBY
IS(ON)
IGND(ON)
IL(off)
VF
On-state resistance(1)
Clamp voltage
Supply current in standby at
VCC = 13 V (2)
190
IOUT = 0.7 A; VCC = 4 V; Tj = 25 °C
149
IOUT = 0.07 A; VCC = 2.7 V; VCC decreasing
516
IS = 20 mA; 25 °C < Tj < 150 °C
36
IS = 20 mA; Tj = -40 °C
36
38
45
0.5
VCC = 13 V;
VIN0,1,2,3 = VOUT0,1,2,3 = VFR = VSEn = 0 V;
VSEL0,1 = 0; Tj = 85 °C (3)
0.5
VCC = 13 V;
VIN0,1,2,3 = VOUT0,1,2,3 = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 125 °C
3
Supply current
VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V;
VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 0 A
Control stage current
consumption in ON state. All
channels active.
VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V;
VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 0.7 A;
60
VIN0,1,2,3 = VOUT0,1,2,3 = 0 V; VCC = 13 V;
Tj = 25 °C
0
VIN0,1,2,3 = VOUT0,1,2,3 = 0 V; VCC = 13 V;
Tj = 125 °C
0
IOUT = -0.7 A; Tj = 150 °C
mΩ
V
V
VCC = 13 V;
VIN0,1,2,3 = VOUT0,1,2,3 = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 25 °C
VCC = 13 V; VIN = VOUT = VFR = VSEL0,1 = 0 V;
VSEn = 5 V to 0 V
Output - VCC diode voltage at
Tj = 150 °C
86
IOUT = 0.7 A; Tj = 150 °C
Standby mode blanking time
Off-state output current at
VCC = 13 V(2)
V
µA
260
550
µs
5.5
7.5
mA
9
mA
0.01
0.5
µA
3
0.7
V
1. For each channel.
2. Power MOSFET leakage included.
3. Parameter specified by design; not subject to production test.
DS12654 - Rev 6
page 7/44
VNQ9080AJ
Main electrical characteristics
Table 6. Switching
VCC = 13 V; -40 °C < Tj < 150 °C, unless otherwise specified
Symbol
Min.
Typ.
Max.
Turn-on delay time at Tj = 25 °C
10
26
120
Turn-off delay time at Tj = 25 °C
10
30
100
(dVOUT/dt)on(1)
Turn-on voltage slope at Tj = 25 °C
0.2
0.42
0.7
(dVOUT/dt)off(1)
Turn-off voltage slope at Tj = 25 °C
0.2
0.45
0.7
td(on)
(1)
td(off)(1)
Parameter
Test conditions
Unit
µs
RL = 18.6 Ω
V/µs
WON
Switching energy losses at turn-on (twon)
0.06
0.095(2)
mJ
WOFF
Switching energy losses at turn-off (twoff)
0.06
0.095(2)
mJ
tSKEW
Differential pulse skew (tPHL - tPLH)
5
55
µs
-45
1. See Figure 4. Switching time and pulse skew.
2. Specified by design and evaluated by characterization, not tested in production.
DS12654 - Rev 6
page 8/44
VNQ9080AJ
Main electrical characteristics
Table 7. Logic inputs
7 V < VCC < 28 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0.9
V
INPUT0,1,2,3 characteristics
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
6
IIN = -1 mA
µA
8.5
-0.7
V
FaultRST characteristics
VFRL
Input low level voltage
IFRL
Low level input current
VFRH
Input high level voltage
IFRH
High level input current
VFR(hyst)
Input hysteresis voltage
VFRCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
6
IIN = -1 mA
µA
8.5
-0.7
V
SEL0,1 characteristics (7 V < VCC < 18 V)
VSELL
Input low level voltage
ISELL
Low level input current
VSELH
Input high level voltage
ISELH
High level input current
VSEL(hyst)
Input hysteresis voltage
VSELCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
V
6
IIN = -1 mA
µA
8.5
-0.7
V
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
VSEn(hyst)
Input hysteresis voltage
VSEnCL
DS12654 - Rev 6
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
ISEN = 1 mA
ISEN = -1 mA
V
µA
V
9
12
-0.7
V
page 9/44
VNQ9080AJ
Main electrical characteristics
Table 8. Protections
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
ILIMH (1)
ILIMH2 (2)
DC short- circuit current
ILIMH at 22 V
Shutdown temperature
TRS
Thermal reset of fault
diagnostic indication
ΔTJ_SD
Min.
Typ.
Max.
VCC = 16 V; Tj = -40 °C
-15%
14
15%
VCC = 16 V; Tj = 150 °C
-15%
10
15%
VCC = 19 V; Tj = -40 °C
-15%
11.2
15%
VCC = 19 V; Tj = 150 °C
-15%
8.9
15%
VCC = 22 V; Tj = 25 °C
TTSD
THYST
Test conditions
175
210
135
Thermal hysteresis
°C
7
(TTSD - TRS) (3)
Dynamic temperature
A
4.2
150
VFR = 0 V; VSEn = 5 V
Unit
VCC = 19 V
55
VCC = 16 V
80
K
VFR = 5 V to 0 V; VSEn = 5 V;
tLATCH_RST
Fault reset time for output
unlatch (3)
For example Ch0:
3
10
20
µs
50
75
ms
VIN0 = 5 V; VSEL0,1 = 0 V
tD_Restart
VDEMAG
Latch-OFF delay time before
automatic restart
Turn-off output voltage clamp
Tj > 125 °C
IOUT = 0.7 A; L = 6 mH; Tj = -40 °C
VCC - 36
IOUT = 0.7 A; L = 6 mH;
Tj = 25 °C to 150 °C
VCC - 36
V
VCC - 38
VCC - 45
V
1. ILIMH guaranteed between 7 V and 16 V, -40 °C < Tj < 150 °C.
2. ILIMH2 guaranteed between 16 V and 19 V, -40 °C < Tj < 150 °C.
3. Specified by design and evaluated by characterization, not tested in production.
DS12654 - Rev 6
page 10/44
VNQ9080AJ
Main electrical characteristics
Table 9. Current Sense
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
VSENSE_CL
CurrentSense clamp voltage
Test conditions
VSEn = 0 V; ISENSE = 1 mA
Min.
Typ.
Max.
-9
-8
-7
VSEn = 0 V; ISENSE = -1 mA
7
Unit
V
CurrentSense characteristics
KOL
IOUT/ISENSE
dKOL/KOL(1)(2)
K0
Current sense ratio drift at
calibration point
IOUT/ISENSE
dK0/K0(1) (2)
K1
CurrentSense ratio drift
IOUT/ISENSE
dK1/K1(1)(2)
K2
CurrentSense ratio drift
IOUT/ISENSE
(1)(2)
dK2/K2
K850
CurrentSense ratio drift
IOUT/ISENSE
dK850/K850(1)(2)
K3
CurrentSense ratio drift
IOUT/ISENSE
dK3/K3 (1) (2)
CurrentSense ratio drift
810
IOUT = 0.01 A; VSENSE = 0.5 V; VSEn = 5 V
IOUT = 0.025 A; VSENSE = 0.5 V; VSEn = 5 V
IOUT = 0.15 A; VSENSE = 0.5 V; VSEn = 5 V
IOUT = 0.7 A; VSENSE = 3.5 V; VSEn = 5 V
IOUT = 0.85 A; VSENSE = 3.5 V; VSEn = 5 V
IOUT = 2.1 A; VSENSE = 3.5 V; VSEn = 5 V
CS disabled: VSEn = 0 V
CS disabled: -1 V < VSENSE < 5 V(1)
-25
25
-35% 1500
-25
-15
-7%
1500
-7
-5%
%
7%
7
1500
%
7%
7
1500
%
15%
15
-7
-7%
+35%
25
-15% 1500
%
%
5%
-5
5
%
0
0.5
-0.5
0.5
0
10
CS enabled: VSEn = 5 V; all channel ON;
IOUTX = 0 A; ChX diagnostic selected;
For example Ch0:
VIN0 = 5 V; VIN1,2,3 = 5 V;
ISENSE0
CurrentSense leakage current V
SEL0,1 = 0 V; IOUT0 = 0 A;
µA
IOUT1,2,3 = 0.7 A
CS enabled: VSEn = 5 V; ChX OFF;
IOUTX = 0 A; ChX diagnostic selected;
For example Ch0:
0
1
VIN0 = 0 V; VIN1,2,3 = 5 V;
VSEL0,1 = 0 V; IOUT0 = 0 A; IOUT1,2,3 = 0.7 A
VSEn = 5 V; RSENSE = 2.7 kΩ;
VOUT_MSD
(1)
Output voltage for
CurrentSense shutdown
For example Ch0:
5
V
VIN0 = 5 V; VSEL0,1 = 0 V; IOUT0 = 0.7 A
VSENSE_SAT
CurrentSense saturation
voltage
VCC = 7 V; RSENSE = 10 kΩ;
VSEn = 5 V; VIN0 = 5 V;
VSEL0,1 = 0 V; IOUT0 = 6 A; Tj = -40 °C
4.8
V
2
mA
VCC = 7 V; VSENSE = 3.5 V;
ISENSE_SAT
(1)
CS saturation current
VIN0 = 5 V; VSEn = 5 V;
VSEL0,1 = 0 V; Tj = 150 °C
DS12654 - Rev 6
page 11/44
VNQ9080AJ
Main electrical characteristics
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VCC = 7 V; VSENSE = 3.5 V;
IOUT_SAT
(1)
Output saturation current
VIN0 = 5 V; VSEn = 5 V;
4
A
VSEL0,1 = 0 V; Tj = 150 °C
OFF-state diagnostic
VSEn = 5 V; ChX OFF;
VOL
OFF-state open-load voltage
detection threshold
ChX diagnostic selected;
For example Ch0:
2
3
4
V
-150
-40
-5
µA
100
170
250
µs
60
µs
30
µs
VIN0 = 0 V; VSEL0,1 = 0 V;
IL(off2)
OFF-state output sink current
VIN = 0 V; VOUT = VOL; Tj = -40 °C to 125 °C
VSEn = 5 V; ChX ON to OFF transition;
tDSTKON
OFF-state diagnostic delay
time from falling edge of
INPUT
(see Figure 6. tDSTKON )
ChX diagnostic selected;
For example Ch0:
VIN0 = 5 V to 0 V; VSEL0,1 = 0 V;
IOUT0 = 0 A; VOUT = 4 V
tD_OL_V
Settling time for valid OFFstate open load diagnostic
indication from rising edge of
SEn
VIN0,1,2,3 = 0 V; VFR = 0 V; VOUT0 = 4 V;
VSEn = 0 V to 5 V
VSEn = 5 V; ChX OFF;
ChX diagnostic selected;
tD_VOL
OFF-state diagnostic delay
time from rising edge of VOUT
For example Ch0:
5
VIN0 = 0 V; VSEL0,1 = 0 V;
VOUT0 = 0 V to 4 V
Fault diagnostic feedback (see Table 10. Truth table)
13 V < VCC < 18 V;
•
VSENSEH
CurrentSense output voltage
in fault condition
For example:
Ch0 in open load; RSENSE = 0.7 kΩ;
VIN0 = 0 V;
VSEn = 5 V; VSEL0,1 = 0 V;
IOUT0 = 0 A; VOUT0 = 4 V
5
7.5
V
VCC = 7 V;
•
For example:
Ch0 in open load; RSENSE = 0.7 kΩ;
VIN0 = 0 V;
VSEn = 5 V; VSEL0,1 = 0 V;
IOUT0 = 0 A; VOUT0 = 4 V
4.3
13 V < VCC < 18 V; VSENSE = 5 V
ISENSEH
DS12654 - Rev 6
CurrentSense output current
in fault condition
•
For example:
Ch0 in open load; VIN0 = 0 V;
VSEn = 5 V; VSEL0,1 = 0 V;
IOUT0 = 0 A; VOUT0 = 4 V
7
8.6
12
mA
page 12/44
VNQ9080AJ
Main electrical characteristics
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VCC = 7 V; VSENSE = 5 V;
ISENSEH
CurrentSense output current
in fault condition
•
For example:
Ch0 in open load; VIN0 = 0 V;
VSEn = 5 V; VSEL0,1 = 0 V;
IOUT0 = 0 A; VOUT0 = 4 V
mA
4.4
CurrentSense timings (current sense mode - see Figure 5. Current Sense timings (current sense mode))(3)
tDSENSE1H
Current sense settling time
from rising edge of SEn
tDSENSE1L
Current sense disable delay
time from falling edge of SEn
tDSENSE2H
Current sense settling time
from rising edge of INPUT
VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 kΩ;
RL = 18.6 Ω
ΔtDSENSE2H
Current sense settling time
from rising edge of IOUT
(dynamic response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ; ISENSE
= 90 % of ISENSEMAX; RL = 18.6 Ω
tDSENSE2L
Current sense turn-off delay
time from falling edge of
INPUT
VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 kΩ;
RL = 18.6 Ω
tDSENSE3H
Current sense latch-OFF
filtering time
VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 kΩ;
RL = 18.6 Ω
1.4
60
µs
5
20
µs
100
200
µs
100
µs
70
250
µs
2
2.6
ms
CurrentSense timings (Multiplexer transition times)(3)
tD_XtoY
CurrentSense transition delay
from ChX to ChY
VIN0 = 5 V; VIN1 = 5 V; VSEn = 5 V; VSEL0 = 0
V to 5 V;
IOUT0 = 0 A; IOUT1 = 0.7 A;
30
RSENSE = 1 kΩ
tD_CStoVSENSEH
CurrentSense transition delay
from stable current sense on
ChX to VSENSEH
VIN0 = 5 V; VIN1 = 0 V; VSEn = 5 V; VSEL0 = 0
V to 5 V;
on ChY
RSENSE = 1 kΩ
IOUT0 = 0.7 A; VOUT1 = 4 V;
µs
20
1. Parameter specified by design; not subject to production test.
2. All values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified.
3. Transition delay is measured up to ±10% of final conditions.
DS12654 - Rev 6
page 13/44
VNQ9080AJ
Main electrical characteristics
Figure 4. Switching time and pulse skew
twon
VOUT
twoff
Vcc
80% Vcc
ON
OFF
dVOUT/dt
dVOUT/dt
20% Vcc
t
INPUT
td(off)
td(on)
tpLH
tpHL
t
Figure 5. Current Sense timings (current sense mode)
IN
High
SEn
Low
IOUT
CURRENT SENSE
tDSENSE2H
tDSENSE1L
tDSENSE1H
tDSENSE2L
GAPG1003141014CFT
DS12654 - Rev 6
page 14/44
VNQ9080AJ
Main electrical characteristics
Figure 6. tDSTKON
VINPUT
VOUT
VOUT > VOL
MultiSense
tDSTKON
GAPG2609141140CFT
Table 10. Truth table
Mode
Standby
Normal
Overload
Undervoltage
OFF-state
diagnostics
Negative output
voltage
Conditions
All logic inputs low
Nominal load connected;
Tj < 150 °C
Overload or short to GND causing:
Tj > TTSD or ΔTj > ΔTj _SD
VCC < VUSD (falling)
INX FR SEn SELX OUTX
L
L
L
X
H
L
H
L
L
L
CS
Hi-Z
Comments
Low quiescent current
consumption
L
H
Outputs configured for
See (1) auto-restart
H
H
Outputs configured for
Latch-off
L
X
L
H
L
H
H
X
X
Short to VCC
L
X
Open-load
L
X
Inductive loads turn-off
L
X
See(1)
See (1)
H
See (1)
L
X
X
See (1)
See (1)
Output latches-off
L
Hi-Z
L
Hi-Z
H
H
Output cycles with
temperature hysteresis
See (1)
Re-start when
VCC > VUSD +
VUSDhyst (rising)
External pull-up
< 0 V See (1)
1. Refer to Table 11. Current sense multiplexer addressing.
DS12654 - Rev 6
page 15/44
VNQ9080AJ
Main electrical characteristics
Table 11. Current sense multiplexer addressing
SEn SEL1 SEL0
DS12654 - Rev 6
MUX channel
CS output
Normal mode
L
X
X
H
L
L
Channel 0
diagnostic
ISENSE = 1/K * IOUT0
H
L
H
Channel 1
diagnostic
ISENSE = 1/K * IOUT1
H
H
L
Channel 2
diagnostic
ISENSE = 1/K * IOUT2
H
H
H
Channel 3
diagnostic
ISENSE = 1/K * IOUT3
Overload
OFF-state diag.
Negative output
VSENSE = VSENSEH
Hi-Z
Hi-Z
VSENSE = VSENSEH
page 16/44
VNQ9080AJ
Waveforms
2.4
Waveforms
Figure 7. Latch-off mode - Intermittent short circuit
Short circuit condition
INPUT
Normal condition
Unlatch command is
stored, but no restart until
tD_Restart is elapsed.
FaultRST
ILIMH
INOM
IOUT
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
tD_Restart
(*) Not in scale
t > tDSENSE3H
Figure 8. Auto-restart mode - Intermittent short circuit
Short circuit condition
Normal condition
INPUT
FaultRST
ILIMH
Power Limitation
INOM
IOUT
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
(*) Not in scale
DS12654 - Rev 6
tD_Restart
t > tDSENSE3H
page 17/44
VNQ9080AJ
Waveforms
Figure 9. Auto-restart mode - Permanent short circuit
INPUT
FaultRST
ILIMH
Power Limitation
ILIMH
Power Limitation
IOUT
CS
OTDIFF
(Internal signal)
OT
(Internal signal)
OT_Fault
(Internal signal)
OT_Fault_Diag
(Internal signal)
tD_Restart
(*) Not in scale
t < tDSENSE3H
Figure 10. Standby mode activation
Figure 11. Standby state diagram
Normal Operation
t > t D_STBY
INx = Low
AND
FaultRST = Low
AND
SEn = Low
INx = High
OR
FaultRST = High
OR
SEn = High
Stand-by Mode
GADG2702181047RI
DS12654 - Rev 6
page 18/44
VNQ9080AJ
Electrical characteristics (curves)
2.5
Electrical characteristics (curves)
Figure 13. Standby current
Figure 12. OFF-state output current
ILoff
(nA)
120
GADG300520221511OFFSI
Off state
VCC = 13 V
VIN = VOUT = 0 V
ISTBY
(µA)
3
80
2
40
1
0
-50
0
50
100
150 T (°C)
Figure 14. IGND(ON) vs Iout
IGND(ON)
(mA)
GADG300520221516GNDon
0
-50
VCC = 13 V
0
50
100
150 T (°C)
Figure 15. Logic input high level voltage
VIH , VFRH , VSELH , VSEnH
(V)
GADG300520221518VIH
1.68
VCC = 13 V
6.5
GADG300520221512ISTBY
IOUT = 0.7 A
1.66
6.0
1.64
5.5
5.0
-50
1.62
0
50
100
150 T (°C)
Figure 16. Logic input low level voltage
VIL , VFRL , VSELL , VSEnL
(V)
GADG300520221521VIL
1.60
-50
IIH , IFRH , ISELH , ISEnH
(µA)
3.75
1.30
3.50
1.25
3.25
DS12654 - Rev 6
0
50
100
150 T (°C)
50
100
150 T (°C)
Figure 17. High level logic input current
1.35
1.20
-50
0
3.00
-50
0
GADG300520221522IIH
50
100
150 T (°C)
page 19/44
VNQ9080AJ
Electrical characteristics (curves)
Figure 18. Low level logic input current
IIL , IFRL , ISELL , ISEnL
(µA)
GADG300520221523IIL
Figure 19. Logic input hysteresis voltage
Vi(hyst) , VFR(hyst) , VSEL(hyst) , VSEn(hyst)
(V)
2.75
0.35
2.50
0.30
2.25
0.25
2.00
-50
0
50
100
150 T (°C)
0.20
-50
Figure 20. FaultRST input clamp voltage
VFRCL
(V)
GADG300520221526VFRCL
0
50
GADG300520221525VI
150 T (°C)
100
Figure 21. Undervoltage shutdown
VUSD
(V)
GADG300520221527USD
IIN = 1 mA
6
2.5
4
2.0
2
IIN = -1 mA
0
-2
-50
0
50
100
1.5
150 T (°C)
Figure 22. On-state resistance vs TC
RON
(mΩ)
GADG300520221530RonT
VCC = 4 V
140
1.0
-50
0
150 T (°C)
100
Figure 23. On-state resistance vs VCC
RON
(mΩ)
GADG300520221531RonVcc
T = 150 °C
T = 125 °C
140
IOUT = 0.7 A
50
110
110
80
80
T = 25 °C
T = -40 °C
50
-50
DS12654 - Rev 6
0
50
100
150 T (°C)
50
0
10
20
30
T (°C)
page 20/44
VNQ9080AJ
Electrical characteristics (curves)
Figure 24. Turn-on voltage slope
(dVout/dt)On
(V/µs)
GADG300520221534dVdton
0.475
Figure 25. Turn-off voltage slope
(dVout/dt)Off
(V/µs)
GADG300520221535dVdtoff
VCC = 13 V
0.45
0.450
RL = 18.6 Ω
0.40
VCC = 13 V
RL = 18.6 Ω
0.425
0.400
-50
0.35
0
50
100
150 T (°C)
0.30
-50
Figure 26. WON vs TC
WON
(μJ)
GADG300520221537Won
WOFF
(µJ)
0.6
0.4
0.4
0.2
0.2
0
50
100
150 T (°C)
100
150 T (°C)
0.0
-50
GADG300520221539Woff
0
50
100
150 T (°C)
Figure 29. OFF-state open-load voltage detection
threshold
Figure 28. ILIMH vs TC
ILIMH
(A)
50
Figure 27. WOFF vs TC
0.6
0.0
-50
0
GADG300520221541IlimH
VOL
(V)
GADG300520221544VOL
14
2.75
VCC = 16 V
13
2.50
12
2.25
11
10
-50
DS12654 - Rev 6
0
50
100
150 T (°C)
2.00
-50
0
50
100
150 T (°C)
page 21/44
VNQ9080AJ
Electrical characteristics (curves)
Figure 30. VSENSE clamp vs TC
VSENSE_CL
(V)
GADG300520221546SenCL
Figure 31. VSENSEH vs TC
VSENSEH
(V)
GADG300520221548SenH
IIN = 1 mA
6
5.75
4
5.50
2
IIN = -1 mA
0
-2
-50
DS12654 - Rev 6
0
50
100
5.25
150 T (°C)
5.00
-50
0
50
100
150 T (°C)
page 22/44
VNQ9080AJ
Protections
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature
swing ΔTJ through the direct measurement of the spatial temperature gradient on the device surface in order
to automatically shut off the output MOSFET as soon as ΔTJ exceeds the safety level of ΔTJ_SD. According to
the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermomechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C),
it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the
FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or
remains off (FaultRST = High).
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other
components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current
flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a
safety level, ILIMH, by operating the output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative
voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor
energy to be dissipated without damaging the device.
DS12654 - Rev 6
page 23/44
VNQ9080AJ
Application information
4
Application information
Figure 32. Application diagram
+5V
VDD
OUT
VCC
Rprot_SEn
OUT
SEn
INPUT
Rprot
OUT
Logic
OUT
Dld
Rprot
FaultRST
Rprot
SEL
OUTPUT
Rprot
ADC in
CS
Current mirror
GND
Cext
Rsense
OUT
R GND
GND
D GND
GND
GND
GND
GND
GND
4.1
GND protection network against reverse battery
Figure 33. Simplified internal structure
5V
Vcc
Rprot
Rprot_SEn
INPUT
SEn
MCU
Dld
Rprot
FaultRST
OUTPUT
Rprot
CS
GND
Rsense
D GND
R GND
GND
DS12654 - Rev 6
GAPGCFT00830
page 24/44
VNQ9080AJ
Immunity against transient electrical disturbances
4.1.1
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence
of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the
microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares
the same diode/resistor network.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the supply lines and injected
into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12. ISO 7637-2 - electrical transient
conduction along supply line.
Test pulses are applied directly to DUT (device under test) both in ON and OFF-state and in accordance to ISO
7637-2:2011(E), chapter 4.
The DUT is intended as the current device only, with external components as shown in Figure 34. M0-9
application schematic.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function
does not perform as designed during the test but returns automatically to normal operation after the test”.
Table 12. ISO 7637-2 - electrical transient conduction along supply line
Test Pulse
2011(E)
Test pulse severity level
with Status II functional
performance status
Minimum number
of pulses or test
time
Burst cycle / pulse
repetition time
Pulse duration and
pulse generator internal
impedance
Level
US (1)
1
III
-112 V
500 pulses
0.5 s
2a
III
+55 V
500 pulses
0.2 s
5s
50 µs, 2 Ω
3a
IV
-220 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
IV
+150 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
IV
-7 V
1 pulse
4
(2)
min
max
2 ms, 10 Ω
100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B (3)
35 V
5 pulse
1 min
400 ms, 2 Ω
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. Test pulse from ISO 7637-2:2004(E).
3. With 35 V external suppressor referred to ground (-40°C < Tj < 150 °C).
DS12654 - Rev 6
page 25/44
VNQ9080AJ
Immunity against transient electrical disturbances
Figure 34. M0-9 application schematic
+5V
VDD
OUT
VCC
Rprot_SEn
OUT
SEn
INPUT
Rprot
OUT
Logic
OUT
Rprot
FaultRST
Rprot
SEL
1μF
OUTPUT
Rprot
ADC in
CS
Current mirror
GND
Cext
Rload_nom
Rsense
OUT
R GND
GND
D GND
GND
GND
GND
GND
GND
Note:
DS12654 - Rev 6
In case of multiple channels, each OUTPUT must be connected to the resistive nominal load.
page 26/44
VNQ9080AJ
MCU I/Os protection
4.3
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins from
latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller and the current
required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
A different value of the resistor has to be used for SEn pin, Rprot_SEn, as reported in Figure 32. Application
diagram.
4.4
CS - analog current sense
Diagnostic information on device and load status is provided by an analog output pin (CS) delivering the following
signal:
•
Current monitor: current mirror of channel output current
This signal is routed through an analog multiplexer which is configured and controlled by means of SELx and SEn
pins, according to the address map in Table 11. Current sense multiplexer addressing.
Figure 35. Current Sense and diagnostic – block diagram
VCC
VCC – GND
Clamp
Internal Supply
Undervoltage
shut-down
Control & Diagnostic
FaultRST
INPUT
VCC – OUT
Clamp
Gate Driver
T
SEL1
SEL 0
SE n
RPROT
Current
Limitation
I SENSE
CS
Fault
Diagnostic
MUX
Short to VCC
Open-Load in OFF
To µC ADC
R SENSE
CURRENT
MONITOR
GND
DS12654 - Rev 6
Power Limitation
Overtemperature
K factor
Current
Sense
Fault
IOUT
OUT
VSENSEH
page 27/44
VNQ9080AJ
CS - analog current sense
4.4.1
Principle of Current Sense signal generation
Figure 36. Current Sense block diagram
Vcc
INPUT
Sense MOS
Main MOS
OUT
Current sense
Current sense Switch Block
Fault
CS
To uC ADC
RPROT
RSENSE
GAPG2307131200CFT
Current sense
The output is capable of providing:
•
Current mirror proportional to the load current in normal operation, delivering current proportional to the load
according to a known ratio named K
•
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted into a voltage VSENSE by using
an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While the device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using
simple equations
Current provided by CS output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:
•
VSENSE is the voltage measurable on RSENSE resistor
•
ISENSE is the current provided from CS pin in current output mode
•
IOUT is the current flowing through output
•
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric
factor spread, current sense amplifier offset and process parameters spread of the overall circuitry,
specifying the ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the CS pin which is switched to a “current
limited” voltage source, VSENSEH.
In any case, the current sourced by the CS in this condition is limited to ISENSEH.
DS12654 - Rev 6
page 28/44
VNQ9080AJ
CS - analog current sense
Figure 37. Analog HSD – open-load detection in off-state
+5V
Vbat
Vbat
100nF/ 50V
100nF
Rpull-up
GND
Microcontroller
GND
VDD
V CC
OUT
SEn
2.2 k
INPUT
External
Pull -Up
switch
OUT
Logic
15k
FaultRST
OUT
SEL
15k
OUTPUT
OUT
OUTPUT
CS
Cu rrent mirror
15k
GND
ADC in
R GN D
4.7k
Rsense
15k
DGN D
10nF /100V
OUT
15k
GND
GND
CEXT
GND
GND
GND
GND
GAPG1201151432CFT
Figure 38. Open-load / short to VCC condition
VIN
VSENSE
VSENSEH
Pull-up connected
Open-load
VSENSE = 0
VSENSE
Short to VCC
DS12654 - Rev 6
Pull-up
disconnected
tDSTKON
VSENSEH
page 29/44
VNQ9080AJ
CS - analog current sense
Table 13. Current Sense pin levels in off-state
Condition
Output
VOUT > VOL
Open-load
VOUT < VOL
4.4.2
Short to VCC
VOUT > VOL
Nominal
VOUT < VOL
CS
SEn
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the
device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature
of the short-circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive
supply voltage VPU.
It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby
current consumption to increase in normal conditions, that is when load is connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation:
RPU <
DS12654 - Rev 6
VPU - 4
IL(off2)min @ 4V
page 30/44
VNQ9080AJ
Maximum demagnetization energy (Vcc = 16 V)
5
Maximum demagnetization energy (Vcc = 16 V)
Figure 39. Maximum turn off current versus inductance
10.00
VNQ9080AJ - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
I (A)
1.00
0.10
0.1
L (mH)
1
10
100
1000
Figure 40. Maximum turn off energy versus inductance
100.00
VNQ9080AJ - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
E (mJ)
10.00
1.00
0.1
Note:
L (mH)
1
10
100
1000
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the
temperature specified above for curves A and B.
DS12654 - Rev 6
page 31/44
VNQ9080AJ
Package and PCB thermal data
6
Package and PCB thermal data
6.1
PowerSSO-16 thermal data
Figure 41. PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5)
Figure 42. PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7)
Table 14. PCB properties
Dimension
Board finish thickness
Board dimension
Board Material
1.6 mm ±10%
77 mm x 86 mm
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
Thermal via diameter
Copper thickness on vias
Footprint dimension (top layer)
Heatsink copper area dimension (bottom layer)
DS12654 - Rev 6
Value
1.2 mm
0.3 mm ±0.08 mm
0.025 mm
2.2 mm x 3.9 mm
Footprint, 2 cm2 or 8 cm2
page 32/44
VNQ9080AJ
PowerSSO-16 thermal data
Figure 43. Rthj-amb vs PCB copper area in open box free air condition (one channel on)
Rthj-amb
90
Rthj-amb
80
70
RTH_J-PCB = 9.5°C/W
60
50
40
30
0
2
4
6
8
10
PCB Cu heatsink area (cm2 )
Figure 44. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
100
ZTH_JA (°C/W)
10
Cu=foot print
Cu=2 cm2
Cu=8 cm2
4 Layer
1
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
DS12654 - Rev 6
page 33/44
VNQ9080AJ
PowerSSO-16 thermal data
Figure 45. Thermal fitting model of a double-channel HSD in PowerSSO-16
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections
(power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 15. Thermal parameters
DS12654 - Rev 6
Area/island (cm2)
FP
2
8
4L
R1 = R7 = R9 = R11 (°C/W)
2
-
-
-
R2 = R8 = R10 = R12 (°C/W)
2.5
-
-
-
R3 (°C/W)
6
5.5
5.5
5
R4 (°C/W)
8.5
7.5
7.5
6
R5 (°C/W)
33
19
9
3
R6 (°C/W)
29
18
18
6
C1 = C7 = C9 = C11 (W·s/°C)
0.00008
-
-
-
C2 = C8 = C10 =C12 (W·s/°C)
0.0008
-
-
-
C3 (W·s/°C)
0.08
-
-
-
C4 (W·s/°C)
0.004
0.004
0.004
0.004
C5 (W·s/°C)
0.4
0.5
0.7
3.5
C6 (W·s/°C)
3
5
7
18
page 34/44
VNQ9080AJ
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
7.1
PowerSSO-16 package information
Figure 46. PowerSSO-16 package dimensions
ggg
D2
D3
Bottom view
C A-B D
ggg
C A-B D
minimum solderable area
Section A-A
E3 E2
h
θ2
h
θ1
R1
H
B
for dual gauge only
eee C
GAUGE PLANE
S
A2
A
R
B
L
θ3
ccc C
θ
e
L1
SEATING PLANE
A1
b
ddd
C
CD
2x
f f f C A-B
D
A
N
Section B-B
D
A
b
WITH PLATING
1.2
for dual gauge only
c
c1
E1 E
index area
(0.25D x 0.75E1)
b1
2x
BASE METAL
aaa C D
Top view
2x N/2 TIPS
bbb C
1
2
3
A
N/2
B
8017965_Rev_9
DS12654 - Rev 6
GAPG1605141159CFT
page 35/44
VNQ9080AJ
PowerSSO-16 package information
Table 16. PowerSSO-16 mechanical data
Symbol
Millimeters
Min.
Typ.
Max.
Θ
0°
Θ1
0°
Θ2
5°
15°
Θ3
5°
15°
8°
A
1.70
A1
0.00
0.10
A2
1.10
1.60
b
0.20
0.30
b1
0.20
c
0.19
c1
0.19
D
0.25
0.28
0.25
0.20
0.23
4.90 BSC
D2
3.31
D3
2.61
3.91
e
0.50 BSC
E
6.00 BSC
E1
3.90 BSC
E2
2.20
E3
1.49
h
0.25
L
0.40
2.80
0.50
0.60
L1
1.00 REF
N
16
R
0.07
R1
0.07
S
0.20
0.85
Tolerance of form and position
DS12654 - Rev 6
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.08
eee
0.10
fff
0.10
ggg
0.15
page 36/44
VNQ9080AJ
PowerSSO-16 packing information
7.2
PowerSSO-16 packing information
Figure 47. PowerSSO-16 reel 13"
Access Hole at
Slot Location
( 40 mm min.)
W2
A
N
D
C
W1
B
If present,
tape slot in core
for tape start:
2.5 mm min. width x
10.0 mm min. depth
TAPG2004151655CFT
Table 17. Reel dimensions
Description
Value(1)
Base quantity
2500
Bulk quantity
2500
A (max)
330
B (min)
1.5
C (+0.5, -0.2)
13
D (min)
20.2
N
100
W1 (+2 /-0)
12.4
W2 (max)
18.4
1. All dimensions are in mm.
DS12654 - Rev 6
page 37/44
VNQ9080AJ
PowerSSO-16 packing information
Figure 48. PowerSSO-16 carrier tape
P0
P2
4.0 ±0.1
2.0 ±0.1
0.30 ±0.05
X
1.55 ±0.05
1.75 ±0.1
1.6 ±0.1
F
W
B0
R 0.5
Typical
Y
K1
Y
X
K0
P1
A0
SECTION X - X
REF 4.18
REF 0.6
REF 0.5
SECTION Y - Y
GAPG2204151242CFT
Table 18. PowerSSO-16 carrier tape dimensions
Description
Value(1)
A0
6.50 ± 0.1
B0
5.25 ± 0.1
K0
2.10 ± 0.1
K1
1.80 ± 0.1
F
5.50 ± 0.1
P1
8.00 ± 0.1
W
12.00 ± 0.3
1. All dimensions are in mm.
Figure 49. PowerSSO-16 schematic drawing of leader and trailer tape
Embossed carrier
Punched carrier
8 mm & 12 mm only
END
Carrier tape
Round sprocket holes
START
Top cover tape
Elongated sprocket holes
(32 mm tape and wider)
Trailer
160 mm minimum
Top cover tape
Components
100 mm min.
Leader
400 mm minimum
User direction feed
GAPG2004151511CFT
DS12654 - Rev 6
page 38/44
VNQ9080AJ
PowerSSO-16 marking information
7.3
PowerSSO-16 marking information
Figure 50. PowerSSO-16 marking information
Special function digit
&: Engineering sample
: Commercial sample
PowerSSO-16 TOP VIEW
(not to scale)
GADG0310161234SMD
Parts marked as ‘&’ are not yet qualified and therefore not approved for use in production. ST is not responsible
for any consequences resulting from such use. In no event will ST be liable for the customer using any of these
engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS12654 - Rev 6
page 39/44
VNQ9080AJ
Revision history
Table 19. Document revision history
Date
Revision
11-Sep-2018
1
Changes
Initial release.
Updated cover page, Figure 1. Block diagram, Table 3. Absolute maximum ratings.
24-Sep-2020
2
Updated Main electrical characteristics, Section 2.4 Waveforms and Section 3 Protections.
Added Application information.
Added:
•
Section 5 Maximum demagnetization energy (Vcc = 16 V);
•
Section 6 Package and PCB thermal data.
Updated:
17-Sep-2021
3
•
Figure 12. Application diagram;
•
Figure 16. Analog HSD – open-load detection in off-state;
•
Table 4. Thermal data;
•
Table 6. Switching;
•
Table 9. Current Sense;
•
Section 7.1 PowerSSO-16 package information.
Minor text changes in:
•
Table 3. Absolute maximum ratings;
•
Table 5. Power section.
Updated features list in cover page.
26-Jan-2022
4
Updated Table 8. Protections and Table 9. Current Sense.
Updated Figure 12. Application diagram, Figure 13. Simplified internal structure, Section 4.2
Immunity against transient electrical disturbances and Section 4.3 MCU I/Os protection.
DS12654 - Rev 6
16-Jun-2022
5
24-Aug-2022
6
Added Section 2.5 Electrical characteristics (curves).
Minor text changes.
Updated Figure 1. Block diagram.
Minor text changes.
page 40/44
VNQ9080AJ
Contents
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
4
2.1
Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.1
Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2
Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3
Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4
Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.1
GND protection network against reverse battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.1
Diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2
Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4
CS - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4.1
Principle of Current Sense signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4.2
Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
Maximum demagnetization energy (Vcc = 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
6.1
7
PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1
PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2
PowerSSO-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3
PowerSSO-16 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
DS12654 - Rev 6
page 41/44
VNQ9080AJ
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Suggested connections for unused and not connected pins . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . .
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current sense multiplexer addressing . . . . . . . . . . . . . . . . .
ISO 7637-2 - electrical transient conduction along supply line
Current Sense pin levels in off-state . . . . . . . . . . . . . . . . . .
PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . .
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 carrier tape dimensions . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . .
DS12654 - Rev 6
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. 7
. 8
. 9
10
11
15
16
25
30
32
34
36
37
38
40
page 42/44
VNQ9080AJ
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
DS12654 - Rev 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration diagram (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching time and pulse skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . .
tDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Latch-off mode - Intermittent short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto-restart mode - Intermittent short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto-restart mode - Permanent short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IGND(ON) vs Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FaultRST input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-state resistance vs TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WON vs TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WOFF vs TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILIMH vs TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OFF-state open-load voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . .
VSENSE clamp vs TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VSENSEH vs TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M0-9 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog HSD – open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . .
Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum turn off current versus inductance. . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum turn off energy versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . .
PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . .
Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . .
PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
Thermal fitting model of a double-channel HSD in PowerSSO-16 . . . . . . . . . . . .
PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 reel 13" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-16 schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . .
PowerSSO-16 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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page 43/44
VNQ9080AJ
IMPORTANT NOTICE – READ CAREFULLY
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DS12654 - Rev 6
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