VNS3NV04D

VNS3NV04D ® “OMNIFET II”: FULLY AUTOPROTECTED POWER MOSFET TYPE VNS3NV04D RDS(on) 120 mΩ (*) Ilim 3.5 A (*) Vclamp 40 V (*) (*)Per each device ) s ( ct n LINEAR CURRENT LIMITATION n THERMAL SHUT DOWN n SHORT CIRCUIT PROTECTION n INTEGRATED CLAMP n LOW CURRENT DRAWN FROM INPUT PIN n DIAGNOSTIC FEEDBACK THROUGH INPUT u d o r P e PIN n ESD PROTECTION t e l o n DIRECT ACCESS TO THE GATE OF THE POWER MOSFET (ANALOG DRIVING) n COMPATIBLE WITH STANDARD POWER MOSFET DESCRIPTION The VNS3NV04D is a device formed by two monolithic OMNIFET II chips housed in a standard SO-8 package. The OMNIFET II are designed in STMicroelectronics VIPower M0-3 Technology: they are intended for replacement of standard Power MOSFETS from DC up to 50KHz ) (s s b O t c u BLOCK DIAGRAM SO-8 applications. Built in thermal shutdown, linear current limitation and overvoltage clamp protects the chip in harsh environments. Fault feedback can be detected by monitoring the voltage at the input pin. d o r P e t e l o O bs INPUT1 DRAIN1 OVERVOLTAGE CLAMP OVERVOLTAGE CLAMP GATE CONTROL GATE CONTROL OVER TEMPERATURE LINEAR CURRENT LIMITER LINEAR CURRENT LIMITER SOURCE1 September 2013 DRAIN2 INPUT2 OVER TEMPERATURE SOURCE2 DocID7396 Rev 4 1/14 1 VNS3NV04D ABSOLUTE MAXIMUM RATING Symbol VDSn VINn IINn RIN MINn IDn IRn VESD1 VESD2 Ptot Tj Tc Tstg Parameter Drain-source Voltage (VINn=0V) Input Voltage Input Current Minimum Input Series Impedance Drain Current Reverse DC Output Current Electrostatic Discharge (R=1.5KΩ, C=100pF) Electrostatic Discharge on output pins only (R=330Ω, C=150pF) Total Dissipation at Tc=25°C Operating Junction Temperature Case Operating Temperature Storage Temperature Value Internally Clamped Internally Clamped +/-20 220 Internally Limited -5.5 4000 16500 4 Internally limited Internally limited -55 to 150 Unit V V mA Ω A A V V W °C °C °C u d o ) s ( ct r P e CONNECTION DIAGRAM (TOP VIEW) bs DRAIN 1 5 DRAIN 2 1 SOURCE 1 INPUT 1 8 O ) SOURCE 2 INPUT 2 4 t e l o DRAIN 1 DRAIN 2 s ( t c u d o r P e CURRENT AND VOLTAGE CONVENTIONS t e l o s b O VIN1 RIN1 IIN1 INPUT 1 IIN2 1 DRAIN 1 RIN2 ID2 INPUT 2 VIN2 2/14 ID1 SOURCE 1 VDS1 DRAIN 2 SOURCE 2 VDS1 VNS3NV04D THERMAL DATA Symbol Rthj-lead Rthj-amb Parameter Thermal Resistance Junction-lead (per channel) Thermal Resistance Junction-ambient Value 30 80(*) MAX MAX Unit °C/W °C/W (*) When mounted on a standard single-sided FR4 board with 50mm2 of Cu (at least 35 µm thick) connected to all DRAIN pins of the relative channel. ELECTRICAL CHARACTERISTICS (-40°C < Tj < 150°C, unless otherwise specified) (Per each device) OFF Symbol VCLAMP VCLTH VINTH IISS VINCL Parameter Drain-source Clamp Voltage Drain-source Clamp Threshold Voltage Input Threshold Voltage Supply Current from Input Pin Input-Source Clamp Test Conditions IDSS Zero Input Voltage Drain Current (VIN=0V) Symbol Parameter Typ Max Unit VIN=0V; ID=1.5A 40 45 55 V VIN=0V; ID=2mA 36 VDS=VIN; ID=1mA 0.5 VDS=0V; VIN=5V IIN=-1mA VDS=13V; VIN=0V; Tj=25°C VDS=25V; VIN=0V RDS(on) Test Conditions VIN=5V; ID=1.5A; Tj=25°C u d o s ( t c VIN=5V; ID=1.5A Pr u d o 6 100 6.8 -1.0 V 2.5 V 150 µA 8 -0.3 30 bs O ) ON Static Drain-source On Resistance e t e ol IIN=1mA Voltage ) s ( ct Min 75 Min Typ Max 120 240 V µA Unit mΩ r P e t e l o s b O 3/14 1 VNS3NV04D ELECTRICAL CHARACTERISTICS (continued) (Tj=25°C, unless otherwise specified) DYNAMIC Symbol gfs (*) COSS Parameter Forward Test Conditions Transconductance Output Capacitance Min Typ Max Unit VDD=13V; ID=1.5A 5.0 S VDS=13V; f=1MHz; VIN=0V 150 pF SWITCHING Symbol td(on) tr td(off) tf td(on) tr td(off) tf Parameter Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time (dI/dt)on Turn-on Current Slope Qi Test Conditions VDD=15V; ID=1.5A Vgen=5V; Rgen=RIN MINn=220Ω (see figure 1) IRRM r P e (see figure 1) let VDD=15V; ID=1.5A Vgen=5V; Rgen=RIN MINn=220Ω VDD=12V; ID=1.5A; VIN=5V so Total Input Charge Igen =2.13mA (see figure 5) Parameter Forward On Voltage Reverse Recovery Time Reverse Recovery Charge )- b O Test Conditions ISD=1.5A; VIN=0V ISD=1.5A; dI/dt=12A/µs Min s ( t c u d o VDD=30V; L=200µH Reverse Recovery Current (see test circuit, figure 2) r P e Typ 90 250 450 250 0.45 2.5 3.3 2.0 Max 300 750 1350 750 1.35 7.5 10.0 6.0 Unit ns ns ns ns µs µs µs µs ) s ( ct u d o VDD=15V; ID=1.5A Vgen=5V; Rgen=2.2KΩ SOURCE DRAIN DIODE Symbol VSD (*) trr Qrr Min 4.7 A/µs 8.5 nC Typ 0.8 107 37 Max 0.7 Unit V ns µC A PROTECTIONS (-40°C < Tj < 150°C, unless otherwise specified) Symbol Ilim Parameter Drain Current Limit t e l o tdlim bs Tjsh O Tjrs Igf Eas Step Response Current Limit Test Conditions VIN=5V; VDS=13V VIN=5V; VDS=13V Overtemperature Shutdown Overtemperature Reset Fault Sink Current Single Pulse Avalanche Energy VIN=5V; VDS=13V; Tj=Tjsh starting Tj=25°C; VDD=24V VIN=5V; Rgen=RIN MINn=220Ω; L=24mH (see figures 3 & 4) (*) Pulsed: Pulse duration = 300µs, duty cycle 1.5% 4/14 2 Min 3.5 Typ 5 Max 7 Unit A µs 10 150 175 200 °C 135 10 15 20 °C mA 100 mJ VNS3NV04D PROTECTION FEATURES During normal operation, the INPUT pin is electrically connected to the gate of the internal power MOSFET through a low impedance path. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50KHz. The only difference from the user’s standpoint is that a small DC current IISS (typ. 100µA) flows into the INPUT pin in order to supply the internal circuitry. The device integrates: - OVERVOLTAGE CLAMP PROTECTION: internally set at 45V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. - LINEAR CURRENT LIMITER CIRCUIT: limits the drain current ID to Ilim whatever the INPUT pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh. ) (s - OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the range 150 to 190 °C, a typical value being 170 °C. The device is automatically restarted when the chip temperature falls of about 15°C below shut-down temperature. - STATUS FEEDBACK: in the case of an overtemperature fault condition (Tj > Tjsh), the device tries to sink a diagnostic current Igf through the INPUT pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the INPUT pin driver is not able to supply the current Igf, the INPUT pin will fall to 0V. This will not however affect the device operation: no requirement is put on the current capability of the INPUT pin driver except to be able to supply the normal operation drive current IISS. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit. ) s ( ct u d o r P e t e l o s b O t c u d o r P e t e l o s b O 5/14 1 VNS3NV04D Fig.1: Switching Time Test Circuit for Resistive Load VD Rgen Vgen ) s ( ct ID u d o 90% tr Vgen s b O td(off) ) (s t e l o tf 10% td(on) r P e t c u t t d o r Fig.2: Test Circuit for Diode Recovery Times P e t e l o s b O A A D I FAST DIODE OMNIFET S L=100uH B B 220Ω D Rgen Vgen VDD I OMNIFET S 8.5 Ω 6/14 1 VNS3NV04D Fig. 3: Unclamped Inductive Load Test Circuits Fig. 4: Unclamped Inductive Waveforms ) s ( ct RGEN VIN PW u d o r P e Fig. 5: Input Charge Test Circuit t e l o ) (s VIN s b O t c u d o r P e t e l o s b O 7/14 1 1 VNS3NV04D Source-Drain Diode Forward Characteristics Static Drain Source On Resistance Vsd (mV) Rds(on) (mohms) 1100 1000 1050 Tj=-40ºC 900 Vin=0V Vin=2.5V 1000 800 950 700 900 600 850 500 800 400 750 300 700 200 650 100 Tj=25ºC ) s ( ct Tj=150ºC 600 u d o 0 0 1 2 3 4 5 6 7 8 9 10 11 12 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 r P e Id (A) Id(A) Static Drain-Source On resistance Vs. Input Voltage Derating Curve t e l o Rds(on) (mohms) 300 bs 275 (s) ct du ro P e -O 250 Tj=150ºC 225 200 175 Id=3.5A Id=1A 150 Tj=25ºC 125 100 Tj=-40ºC 75 Id=3.5A Id=1A 50 Id=3.5A Id=1A 25 0 t e l o 3 3.5 4 4.5 5 5.5 6 6.5 Vin(V) Static Drain-Source On resistance Vs. Input Voltage s b O Transconductance Gfs (S) Rds(on) (mohms) 11 250 10 225 Vds=13V 9 Id=1.5A 200 Tj=-40ºC Tj=25ºC 8 175 Tj=150ºC 7 Tj=150ºC 150 6 125 5 100 4 3 75 Tj=25ºC 2 50 Tj=-40ºC 1 25 0 0 0 3 3.5 4 4.5 Vin(V) 5 5.5 6 6.5 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Id (A) 8/14 1 1 VNS3NV04D Static Drain-Source On Resistance Vs. Id Transfer Characteristics Rds(on) (mohms) Idon (A) 250 6 225 5.5 Vin=5V Vds=13.5V 5 200 Tj=150ºC 4.5 175 4 Tj=150ºC 150 3.5 125 3 Tj=25ºC 100 Tj=-40ºC 2.5 ) s ( ct 2 75 1.5 50 Tj= - 40ºC Tj=25ºC 1 25 u d o 0.5 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 1.5 2 2.5 bs 4.5 3.5 O ) 3 s ( t c 2.5 2 1.5 250 500 1 0.75 0.25 Pr 0 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 Rg(ohm) Rg(ohm) Turn off drain source voltage slope Input Voltage Vs. Input Charge s b O 6 Vin=3.5V Vdd=15V Id=1.5A 1.25 750 1000 1250 1500 1750 2000 2250 2500 e t e ol 5.5 0.5 u d o 1 5 1.5 Vin=5V Vdd=15V Id=1.5A 4 4.5 t e l o di/dt(A/usec) 1.75 5 0 4 Turn On Current Slope di/dt(A/us) 0 3.5 Vin (V) Turn On Current Slope 0.5 3 r P e Id (A) Vin (V) dv/dt(V/usec) 9 300 275 8 Vds=1V Id=1.5A 7 Vin=5V Vdd=15V Id=1.5A 250 225 200 6 175 5 150 125 4 100 3 75 2 50 1 25 0 0 0 0 1 2 3 4 5 6 Qg (nC) 7 8 9 10 11 500 250 1000 750 1500 1250 2000 1750 2500 2250 Rg(ohm) 9/14 1 1 VNS3NV04D Turn Off Drain-Source Voltage Slope Capacitance Variations dv/dt(V/usec) C(pF) 300 350 275 Vin=3.5V Vdd=15V Id=1.5A 250 225 300 f=1MHz Vin=0V 200 250 175 150 200 125 100 ) s ( ct 150 75 50 100 25 u d o 0 0 500 1000 250 750 1500 1250 2000 1750 50 2500 2250 0 5 10 900 3.5 800 bs td(off) Vdd=15V Id=1.5A Vin=5V 700 tr 2.5 ) s ( t 2 tf 1.5 c u d td(on) 0 0 500 250 o r P 1000 750 e t e ol 1500 1250 2000 1750 30 35 2500 tr Vdd=15V Id=1.5A Rg=220ohm 600 500 400 td(off) 300 tf 200 td(on) 0 2250 3.25 3.5 3.75 4 Rg(ohm) 4.25 4.5 4.75 5 5.25 Vin(V) Normalized On Resistance Vs. Temperature Id (A) O -O 100 Output Characteristics bs t e l o t(nsec) 4 0.5 25 Switching Time Resistive Load t(usec) 1 20 Vds(V) Switching Time Resistive Load 3 15 r P e Rg(ohm) Rds(on) (mOhm) 5 4 Vin=5V 4.5 3.5 Vin=4V Vin=5V Id=1.5A 4 3 3.5 Vin=3V 3 2.5 2.5 2 2 1.5 1.5 1 1 0.5 0 0.5 0 1 2 3 4 5 Vds (V) 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 175 Tc )ºC) 10/14 1 1 VNS3NV04D Normalized Input Temperature Threshold Voltage Vs. Vinth (V) Normalized Current Temperature Limit Vs. Junction Ilim (A) 10 2 1.8 9 Vds=Vin Id=1mA 1.6 1.4 7 1.2 6 1 5 0.8 4 0.6 3 0.4 2 0.2 1 0 0 -50 -25 0 Vin=5V Vds=13V 8 25 50 75 100 125 150 175 ) s ( ct -50 -25 Tc (ºC) 25 50 75 100 125 150 175 Tc (ºC) Step Response Current Limit t e l o Tdlim(usec) 13 12.5 Vin=5V Rg=220ohm 12 u d o r P e 0 11.5 ) (s 11 10.5 s b O t c u 10 9.5 d o r 9 8.5 P e 8 7.5 t e l o 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 Vdd(V) s b O 11/14 1 1 VNS3NV04D SO-8 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. a1 1.75 MAX. 0.1 0.068 0.25 a2 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 b 0.35 0.48 0.013 b1 0.19 0.25 0.007 C 0.25 0.5 0.010 c1 45 (typ.) D 4.8 5.0 E 5.8 6.2 e 1.27 e3 3.81 F 3.8 L 0.4 M u d o F o s b u d o Pr 0.228 O ) s ( t c e t e l 0.188 ) s ( ct 0.033 0.018 0.010 0.019 0.196 0.244 0.050 0.150 4.0 0.14 0.157 1.27 0.015 0.050 0.6 0.023 8 (max.) r P e t e l o s b O 12/14 1 VNS3NV04D SO-8 TUBE SHIPMENT (no suffix) B Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) C A 100 2000 532 3.2 6 0.6 All dimensions are in mm. ) s ( ct TAPE AND REEL SHIPMENT (suffix “13TR”) u d o REEL DIMENSIONS r P e Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) t e l o ) (s s b O All dimensions are in mm. t c u d o r TAPE DIMENSIONS 2500 2500 330 1.5 13 20.2 12.4 60 18.4 According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 P e Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing t e l o s b O W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 12 4 8 1.5 1.5 5.5 4.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 13/14 1 VNS3NV04D Please Read Carefully: ) s ( ct Information in this document is provided solely in connection with ST products. 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