VS6524P02S

VS6524 VGA Mobile Camera Module DATA BRIEF FEATURES ■ 640H x 480V active pixels ■ ■ ■ ■ 3.6 µm pixel size, 1/6 inch optical format RGB Bayer color filter array Integrated 10-bit ADC Integrated digital image processing functions, including defect correction, lens shading correction, demosaicing, sharpening, gamma correction and color space conversion Embedded camera controller for automatic exposure control, automatic white balance control, black level compensation, 50/60 Hz flicker detection and cancelling, flashgun support Up to 30 fps progressive scan, subsampling and cropping to QVGA, QQVGA and subQCIF ITU-R BT.656-4 YUV (YCbCr) 4:2:2 with embedded syncs, RGB 565, RGB 444 or Bayer 10-bit output formats 8-bit parallel video interface, horizontal and vertical syncs, 24 MHz clock Two-wire serial control interface On-chip PLL, 6.5 to 27 MHz clock input Analog power supply, from 2.4 to 3.0 V Separate I/O power supply, 1.8 or 2.8 V levels Integrated power management with power switch, automatic power-on reset and powersafe pins Low power consumption, ultra low standby current Dual-element plastic lens, F# 2.8, 50° Horizontal field of view 7 x 7 x 4.5 mm fixed focus camera module with embedded passives 20-wire FPC attachment with board-to-board connector, 22 mm total length ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The VS6524 is a VGA resolution CMOS color digital camera featuring low size and low power consumption and targeting mobile applications. The VS6524 is manufactured in 0.18 µm ST CMOS imaging process. It integrates a high-sensitivity pixel array, a digital image processor and camera control functions. The VS6524 is capable of streaming VGA video up to 30 fps, with ITU-R BT.656-4 YUV 4:2:2 frame format. It supports both 1.8 V and 2.8 V interface and requires a 2.4 to 3.0 V analog power supply. Typically, the VS6524 can operate as a 2.8 V single supply camera or as a 1.8 V / 2.5 V supply camera. The integrated PLL allows for low frequency system clock, and flexibility for successful EMC integration. This complete camera module is ready to connect to camera enabled baseband processors, back-end IC devices or PDA engines. The VS6524 package uses the second generation of SmOP2 packaging technology where the sensor, passives and lens are assembled in a fully automated test and focus process, allowing high volume and low cost production. APPLICATIONS ■ Mobile phone ■ ■ ■ ■ PDA Videophone Rev. 2 February 2005 1/3 VS6524 Figure 1. Application Diagram VS6524 VGA Mobile Camera Module SCL, SDA D[7:0] HSYNC VSYNC PCLK FSO CLK CE Table 1. Technical Specifications Video Interface 8-bit parallel video, hsync, vsync ITU-R BT.656-4 compliant, 24 MHz max 6.5 to 27 MHz square 13 MHz typ. (on-chip PLL) 2.4 to 3.0 V analog 1.8 or 2.8 V +/- 0.1 V CMOS levels Streaming 30 fps: 30 mA max Power down: 10 µA max. 2-element, 50° HFOV, F# 2.8 20 cm to infinite < 1% 45% typ. SmOP2 7.0 x 7.0 x 4.5 mm (wlh) FPC with 20-pin B2B connector, Molex 555600201 or equivalenta Baseband or Application Processor Clock input Supply voltage I/O voltage Power consumption Figure 2. Block diagram VS6524 CLK CE PLL and Clock Management Power Mgmt I²C Receiver Camera Controller Power-On Reset 640 x 480 Pixel array 1152 x 864 VDD DGND Lens Depth of field TV distortion AVDD AGND SCL SDA D[7:0] HSYNC, VSYNC PCLK FSO Y Decoder Relative illumination Package type Parallel Video i/f Readout Video Processor Column ADC X Decoder Line SRAM Package size System attach a. Table 1. Technical Specifications Active pixels Pixel size Array size Color filter array Exposure control Analog gain Dynamic range Signal-to-noise Ratio Frame rate 640H x 480V 3.6 x 3.6µm 2.38 x 1.77 mm RGB Bayer +120 dB +24 dB (max) 61 dB (typical) 35 dB at 100 lux (typical) 1 to 30 Hz VGA, QVGA, QQVGA, subQCIF Arbitrary cropping Horizontal/vertical flipping YUV 4:2:2 RGB 565, RGB 444 Raw Bayer 10-bit Contact us for custom FPC designs and/or ZIF connector variants PART NUMBERING Table 2. Order Codes Part Number VS6524P02S Description SmOP2 7.0 x 7.0 x 4.5 mm FPC attach, tray packing Image format Pixel format 2/3 VS6524 Figure 3. Outline Drawing REVISION HISTORY Table 3. Revision History Date February 2005 February 2005 Revision 1 2 First Issue Same content, format/layout reviewed. Description of Changes Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 3/3