VV6410

VV5410 & VV6410 ® Mono and Colour Digital Video CMOS Image Sensors The VV5410/VV6410 are multi format digital output imaging devices based on STMicroelectronics’s unique CMOS sensor technology. Both sensors require minimal support circuitry. VV5410 (monochrome) and VV6410 (colourised) produce digital video output. The video streams from both devices contain embedded control data that can be used to enable frame grabbing applications as well as providing input data for the external exposure controller. The pixel array in VV6410 is coated with a Bayer colour pattern. This colourised sensor can interface to a range of STMicroelectronics co-processors. A chipset comprising VV6410 and STV0657 will output 8bit YUV or RGB digital video. A USB camera can be realised by partnering VV6410 with STV0672. Finally a high quality digital stills camera can be produced by operating VV6410 with STV0680B-001. Please contact STMicroelectronics for ordering information on all of these products. Both VV5410 and VV6410 are initialised in a power saving mode and must be enabled via I2C control before they can produce video. The I2C allows the master coprocessor to reconfigure the device and control exposure and gain settings. USB systems are catered for with an ultra low power, pin driven, suspend mode. The on board regulator can supply sufficient current drive to power external components, (e.g. the video coprocessor). Key Features • • • • • • • • • • 3.3V operation Multiple video formats available Pan tilt image feature Sub sampled image full FOV feature On board 10 bit ADC On board voltage regulator Low power suspend mode for USB systems Automatic black and dark calibration On board audio amplifier I2C communications Applications • • • • PC camera Personal digital assistant Mobile video phones Digital stills cameras Specifications Effective image sizes after colour processing Pixel resolution Pixel size 352 x 288 (CIF,PAL) 176 x 144 (QCIF) up to 356 x 292 7.5µm x 6.9µm 2.73mm x 2.04mm +81dB +12dB (recommended max) c.56dB 1.17mV 2.1V/lux.sec 46mV/sec 1.2mV 3.0V- 6.0V DC +/− 10% 26.2mA (max,CIF@30fps) 85µA (suspend mode) 0oC - 40oC 36pin CLCC Functional block diagram Array size DATA READOUT STRUCTURE SRAM LINE STORE Exposure control Analogue gain FST LST QCK X-DECODER SNR DIGITAL CONTROL LOGIC COLUMN ADC Random Noise Sensitivity (Green channel) Dark Current SUSPEND OEB SCL SDA YDECODER PIXEL ARRAY VFPN Supply voltage Supply current VOLTAGE REFERENCES,VOLTAGE REGULATORS AND AUDIO AMP CIRCUITRY Operating temperature (ambient) Package type cd5410-6410f: Rev 3.0 28 September 2000 Commercial in confidence 1/105 VV5410 & VV6410 Table of Contents 1. 2. 2.1 2.2 2.3 2.4 Document Revision History ............................................................................................ 4 Introduction ...................................................................................................................... 5 Overview ........................................................................................................................................ 5 Exposure Control............................................................................................................................ 5 Digital Interface .............................................................................................................................. 5 Other Features ............................................................................................................................... 7 3. 3.1 3.2 3.3 3.4 Operating Modes .............................................................................................................. 9 Video Timing .................................................................................................................................. 9 Pixel Array .................................................................................................................................... 10 X-offset and Y-offset..................................................................................................................... 11 QCIF Output Modes ..................................................................................................................... 16 4. 5. 6. 7. 8. 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Black Offset Cancellation .............................................................................................. 18 Dark Offset Cancellation................................................................................................ 20 Exposure Control ........................................................................................................... 21 Timed Serial Interface Parameters ............................................................................... 24 Digital Video Interface Format ...................................................................................... 27 General description ...................................................................................................................... 27 Embedded control data ................................................................................................................ 28 Video timing reference and status/configuration data .................................................................. 31 Detection of sensor using data bus state ..................................................................................... 48 Resetting the Sensor Via the Serial Interface .............................................................................. 48 Resetting the Sensor Via the RESETB pin .................................................................................. 48 Resynchronising the Sensor Via the RESETB pin configured as SINB ....................................... 48 Power-up, Low-power and Sleep modes ..................................................................................... 50 Suspend mode ............................................................................................................................. 52 8.10 Data Qualification Clock, QCK ..................................................................................................... 52 9. 9.1 9.2 9.3 9.4 9.5 9.6 9.6 9.7 Serial Control Bus .......................................................................................................... 60 General Description...................................................................................................................... 60 Serial Communication Protocol .................................................................................................... 60 Data Format ................................................................................................................................. 60 Message Interpretation................................................................................................................. 61 The Programmers Model.............................................................................................................. 61 Types of messages ...................................................................................................................... 82 Types of messages ...................................................................................................................... 82 Serial Interface Timing ................................................................................................................. 85 10. 11. Clock Signal.................................................................................................................... 86 Other Features................................................................................................................ 87 2/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 11.1 Audio Amplifier ............................................................................................................................. 87 11.2 Voltage Regulators ....................................................................................................................... 89 11.3 Valid Supply Voltage Configurations ............................................................................................ 89 11.4 Programmable Pins ...................................................................................................................... 91 12. Characterisation Details ................................................................................................ 92 12.1 VV5410/VV6410 AC/DC Specification ......................................................................................... 92 12.2 VV5410/VV6410 Optical Characterisation Data ........................................................................... 92 12.3 VV5410/VV6410 Power Consumption ......................................................................................... 94 12.4 Digital Input Pad Pull-up and Pull-down Strengths....................................................................... 94 13. Pixel Defect Specification.............................................................................................. 95 13.1 Pixel Fault Definitions ................................................................................................................... 95 13.2 Stuck at White Pixel Fault ............................................................................................................ 95 13.3 Stuck at Black Pixel Fault ............................................................................................................. 95 13.4 Column / Row Faults .................................................................................................................... 95 13.5 Image Array Blemishes ................................................................................................................ 96 14. 15. 16. 17. 18. Pinout and pin descriptions .......................................................................................... 98 Package Details (36pin CLCC) .................................................................................... 101 Recommended VV5410/6410 support circuit............................................................. 102 Evaluation kits (EVK’s) ................................................................................................ 103 Ordering details............................................................................................................ 104 14.1 36pin CLCC Pinout Map............................................................................................................... 98 cd5410-6410f-3-0.fm 3/105 Commercial in confidence VV5410 & VV6410 1. Document Revision History Revision 1.0 2.0 Date 13/06/2000 06/07/2000 • • • • • • • • Original release Comments Package drawing and pin description updated Optical characterisation data added Audio description extended Pixel defect specification added Product numbering updated Reference design for BGA packaged 410 added Gain ceiling recommendation Remove all reference to BGA package option Product maturity moves to Mat29 therefore d/s moves to Release3.0 2.1 3.0 04/09/2000 28/09/2000 • • Table 1 : Document Revision History 4/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 2. 2.1 Introduction Overview VV5410/VV6410 is a CIF format CMOS image sensor. The VV5410 sensor is the basic monochrome device and VV6410 is the colourised variant. The operation of VV5410 and VV6410 is very similar but any differences will be identified and explained. VV6410 can output digital colourised pixel data at frame and line rates compatible with either NTSC or PAL video standards. VV5410 and VV6410 contain the same basic video timing modes. Table 2 summarises these video modes. The various operating modes are detailed in Section 3. Important: VV5410 and VV6410’s output video data stream only contains raw data. A master co-processor is required to generate a video waveform that can be displayed on a VDU Mode QCIF - 25 fps QCIF - 30 fps QCIF - 60 fps CIF - 25 fps CIF - 30 fps NTSC (3.2 fsc) PAL (3.2 fsc) Input Clock (MHz)Note 8.00 8.00 16.00 16.00 16.00 28.636360 / 2.5 35.46895 / 2.5 System Clock Divisor 8 8 8 4 4 2 2 Image Size 180 x 148 180 x 148 180 x 148 356 x 292 356 x 292 306 x 244 356 x 292 Line Time (µs) 250.00 208.00 104.00 125.00 104.00 63.555564 63.999639 Lines per Frame 160 160 160 320 320 525 625 Frame Rate (fps) 25.00000 30.04807 60.09614 25.00000 30.04807 29.97003 25.00014 Table 2 : Video Modes Note: The user can also provide a 24 MHz clock, rather than a 16 MHz clock, for the QCIF-60fps, CIF-25fps and CIF-30fps modes, which the sensor then internally divides by 1.5, (see data_format[22]), to give an effective input clock frequency of 16 MHz. 2.2 Exposure Control VV5410/VV6410 does not include any form of automatic exposure and/or gain control. Thus to produce a correctly exposed image the integration period for the pixels, in the sensor array, an exposure control algorithm must be implemented externally. The new exposure values are written to the sensor via the serial interface. 2.3 Digital Interface The sensor’s offers a very flexible digital interface, the main components of which are listed below: 1. A tri-stateable 5-wire data bus (D[4:0]) for sending both video data and embedded timing references. 2. 4-wire and 8-wire data bus alternatives available. If the 8-wire option is selected then the FST/LST pins are reconfigured to output data information. 3. A data qualification clock, QCK, which can be programmable via the serial interface to behave in a number of different ways (Tri-stateable). 4. A line start signal, LST (Tri-stateable). 5. A frame start signal, FST (Tri-stateable). 6. OEB tri-states all 5 data bus lines, D[4:0], the qualification clock, QCK, LST, FST and D[7]. 7. A 2-wire serial interface (SDA,SCL) for controlling and setting up the device. cd5410-6410f-3-0.fm 5/105 Commercial in confidence VV5410 & VV6410 Introduction SDA CLKI RESETB OEB IMAGE FORMAT EXPOSURE CONTROL OFFSET CANCELLATION SERIAL INTERFACE SCL D[4:0] OUTPUT YDECODER QCK LST FST Digital Logic Analogue Core PHOTO DIODE ARRAY FORMAT Column ADC VREGS, Readout Structure AUDIO AMP., & REFS X-Decoder SRAM line store Figure 1 : Block Diagram of VV5410/VV6410 Image Sensor (5-wire output) 2.3.1 Digital Data Bus Along with the pixel data, codes representing the start and end of fields and the start and end of lines are embedded within the video data stream to allow a co-processor to synchronise with video data the camera module is generating. Section 8. defines the format for the output video data stream. 2.3.2 Frame Grabber Control Signals To complement the embedded control sequences the data qualification clock (QCK), the line start signal (LST) and the field start signal (FST) signals can be independently set-up as follows: 1. Disabled 2. Free-running. 3. Qualify only the control sequences and the pixel data. 4. Qualify the pixel data only There is also the choice of two different QCK frequencies where one is twice the frequency of the other. 1. Fast QCK: the falling edge of the clock qualifies every 8, 5 or 4 bit blocks of data that makes up a pixel value. 2. Slow QCK: the rising edge qualifies 1st, 3rd, 5th, etc. blocks of data that make up a pixel value while the falling edge qualifies the 2nd, 4th, 6th etc. blocks of data. For example in 4-wire mode the rising edge of the clock qualifies the most significant nibbles while the falling edge of the clock qualifies the least significant nibbles. 2.3.3 2-wire Serial Interface The 2-wire serial interface provides complete control over sensor setup and operation. Two serial interface broadcast addresses are supported. One allows all sensors to be written to in parallel while the other allows all sensors and co-processors to be written to in parallel. Section 9. defines the serial interface communications protocol and the register map of all the locations which can be accessed via the serial interface. 6/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 2.3.4 Sensor/Co-processor Interface Options There are 3 main ways of interfacing to the VV5410/VV6410 sensor based on the above signals: 1. The colour co-processor supplies the sensor clock, CLKI, and uses the embedded control sequences to synchronise with the frame and line level timings. Thus the host and sensor are running off derivatives of the same fundamental clock. To allow the co-processor to determine the best sampling position of the video data, during its power-up sequence the sensor outputs a 101010... sequence on each of its data bus lines for the host to lock on to. D[4:0] VV5410/ VV6410 Sensor CLKI SDA Co-processor 1. SCL 2. The colour co-processor supplies the sensor clock, CLKI, and uses a free-running QCK supplied by the sensor to sample the incoming video data stream. The embedded control sequences are used to synchronise the frame and line level timings. D[4:0] VV5410/ VV6410 Sensor CLKI QCK SDA SCL Co-processor 2. 3. The colour co-processor supplies the sensor clock, CLKI, and uses FST, LST and the data only mode for QCK to synchronise to the incoming video data. Primarily intended for interfacing to frame grabbers. D[4:0] CLKI QCK LST FST SDA SCL 3. VV5410/ VV6410 Sensor Co-processor 2.4 2.4.1 Other Features Audio Amplifier Pins AIN and AOUTP & AOUTN are the input and outputs respectively for an audio amplifier. 2.4.2 Voltage Regulator The on-chip voltage regulator requires only a few external components to form a fully functional voltage regulator to 3.3V. cd5410-6410f-3-0.fm 7/105 Commercial in confidence VV5410 & VV6410 Introduction 2.4.3 Serial Interface Programmable Pins The FST and QCK pins are re-configurable to follow the state of 2-bits in a serial register. The user could then use these control bits to control a peripheral device, a motor or shutter mechanism for example. 8/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 3. 3.1 Operating Modes Video Timing The video format mode on power-up is CIF 30fps by default. After power-up the mode can be changed by a serial interface to write to the video_timing register. The frame/field rate is also programmable via the serial interface. Bit [3] of serial register [16] selects between 30 and 25 frames per second for the CIF modes and 60/50 fields per second for the Digital and Analog Timing modes. Please note that the sensor can exit low power in ANY of the available video modes. The number of video lines in each frame is the same (320) for both the CIF modes. The slower frame rate (25 fps) is implemented by simply extending the line period from 416 pixel periods to 500 pixel periods. Table 3 details the setup for each of the video timing modes. A serial write to serial register [16] will force the contents of other registers in the serial interface to change to the appropriate values, regardless of their present state. If for example a different data output mode is required than the default for a particular video mode, a write to the appropriate register after the mode has changed will restore the desired value. Video Mode PAL (3.2 fsc) NTSC (3.2 fsc) CIF - 25 fps CIF - 30 fps QCIF - 25 fps QCIF - 30 fps QCIF - 60 fps Clock (MHz) 28.636360 / 2.5 35.46895 / 2.5 16.0 16.0 8.0 8.0 16.0 System Clock Divisor 2 2 4 4 8 8 8 Video Data Line Length 454 364 500 416 250 208 208 Field Length Data Output Mode 5-wire 5-wire 5-wire 5-wire 5-wire 5-wire 5-wire 356 x 292 306 x 244 356 x 292 356 x 292 180 x 148 180 x 148 180 x 148 312/313 262/263 320 320 160 160 160 Table 3 : Video Timing Modes 3.1.1 Arbitration registers When the operating video mode is changed a number of serial registers are forced into new states. The complete list is as follows: Arbitrated feature line length field length system clock division free running qcknote1 extra black linesnote2 Video mode selected/value automatically programmed PAL NTSC CIF 25fps CIF 30fps PTQCIF 25fps PTQCIF 30fps SSQCIF 25fps SSQCIF 30fps 453 311 2 yes yes 363 261 2 yes yes 499 319 4 no no 415 319 4 no no 249 159 8 no no 207 159 8 no no 249 159 8 no no 207 159 8 no no Table 4 : Arbitration registers cd5410-6410f-3-0.fm 9/105 Commercial in confidence VV5410 & VV6410 Operating Modes note1: The free running qck, slow by default, is enabled by writing 8’h04 to serial register [20]. note2: The contents of the extra black lines are enabled on to the data bus by setting bit [5] of serial register [17]. If bit [0] of serial register [24] is reset, indicating that the preferred coprocessor device is not the VP3 device, (a STMicroelectronics coprocessor), then the extra black lines are enabled by default regardless of the basic video mode selected. The registers that control the image position within the pixel array and also the order in which the pixels are read out have not been included in the table as their values are subject to a secondary series of registers. We will discuss the former in sections 2.2 and 2.3. 3.1.2 Input Clock Frequencies It is recommended that a 16 MHz clock is used to generate CIF-25fps,CIF-30fps and QCIF-60fps and that an 8 MHz clock is used to generate QCIF-25fps and QCIF-30fps, however the sensor can adapt to a range of other input frequencies and still generate the required frame rates. For example, a 24 MHz clock can be used to generate CIF-30fps. By setting bit [7] of serial register [22] the sensor can automatically divide the incoming clock by 1.5 by setting bit [7] of serial register [22], such that the internal clock generator logic will still receive a 16 MHz clock. Note that the clock division register is internally an 8 bit value, although the user may only program the lower nibble. The upper nibble is reserved for setting the clock divisor as we change between primary video modes. The lower nibble can be programmed to reduce the effective frame rate within each video mode. The system clock divisor column in Table 5 assumes that the programmable pixel clock divisor is set to the default of 0, implementing a divide by 1 of the internal pixel clock. Consider the following scenario where a user requires 15 fps CIF resolution image. As can be seen there are a wide range of options to achieve the same result. clk in (MHz) 8 12 16 24 Divide by 3/2 enabled? no yes no yes System clock divisor 4 4 4 4 Pixel clock divisor 1 1 2 2 pclk (MHz) 2 2 2 2 Field Rate 15 15 15 15 Table 5 : System clock divisor options 3.2 Pixel Array The physical pixel array is 364 x 296 pixels. The pixel size is 7.5 µm by 6.9 µm. The image size for NTSC is 306 x 244 pixels, for PAL and CIF it is 356 x 292 pixels, while for the QCIF modes the image size is 180 x 148 pixels. The remaining 4 physical columns on each side of the PAL image size prevent columns 1 and 2 in PAL/CIF modes from being distorted by the edge effects which occur when a pixel is close to the outer edge of the physical pixel array. Please note that these columns can be enabled as part of the visible image if the user is operating the sensor in the pantilt QCIF mode. Figure 3 shows how the 306 x 244 and 180 x 148 sub-arrays are aligned within the bigger 364 x 296 pixel array. The Bayer colourisation pattern requires that the top-left corner of the pixel sub-array is always a Green 1 pixel. To preserve this Bayer colour pattern the NTSC sub-array has been offset relative to the centre of the array. The QCIF size images are centrally orientated. Image read-out is very flexible. Sections 3.3.2 - describe the options available to the user. By default the sensor read out is configured to be horizontally ‘shuffled’ non-interlaced raster scan. The horizontally ‘shuffled’ raster scan order differs from a conventional raster in that the pixels of individual rows are re-ordered, with the odd pixels within a row read-out first, followed by the even pixels. This ‘shuffled’ read-out within a line, groups pixels of the same colour (according to the Bayer pattern - Figure 2) together, reducing cross talk between the colour channels. This option is on by default and is controllable via the serial interface. The horizontal shuffle option would normally only be selected with the colour sensor variant, VV6410. 10/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 Odd Even Columns Columns (1,3,5,...) (2, 4, 6,...) Odd Rows (5, 7, 9,...) Even Rows (4, 6, 8,...) Green 1 Red Blue Green 2 Figure 2 : Bayer Colourisation Pattern (VV6410 only) 3.3 X-offset and Y-offset The image information is retrieved from the pixel array via a 2 dimensional address. The x and y address busses count from a starting point described by x-offset, y-offset up to a maximum count in x and y that is determined by the image size. The order of this count and the count step size is dependent upon the special image format parameters described below. The detailed control of the x and y address counters is entirely handled by the sensor logic As can be seen in Figure 3 the visible array size is 364 columns by 296 rows. The PAL and CIF images are sized, 356 columns by 292 rows, thus we have a “border” of visible pixels that we do not read out if either of these modes are selected. The images that are read out of the sensor are always “centred” on the array, therefore we allow a border of 4 columns at either end of the image in the x-direction and a border of 2 rows at the top and bottom of the image in the y-direction. The pantilt QCIF and NTSC video modes are similarly centred within the full size array. For all the modes except the pantilt QCIF the x and y offset coordinates are fixed. If the user selects the pantilt QCIF mode then they may specify x and y-offsets in the range: • • (xoffset >= 1) and (xoffset = 5) and (yoffset 150mA and will regulate to 3.0V 10% from an input range of 4-6V. When VV5410/VV6410 is in the USB compatible suspend mode, the clocks to the digital logic are removed to limit power consumption to approximately 80µA. If an external 3.3V supply is available, this regulator may be overdriven by an external 3.3V supply to directly power the logic. This voltage regulator is never powered down. 11.2.2 Regulator for Audio Amplifier The output of the regulator for the audio amplifier, Aud3V3, drives the load resistor for the microphone and the audio preamplifier. As this regulator is capable of being powered-down via the serial interface, all control signals from the digital logic are low during low power/standby. This regulator will be powered up by default. 11.2.3 Regulator for Video Supply/Analogue Core The output of the regulator for the video supply,Vid3V3, powers the analog core. This regulator is capable of being powereddown via the serial interface but will be powered up by default. Note that the sensor will be in low power mode initially and therefore 11.3 Valid Supply Voltage Configurations The power supplies to the VV5410 and VV6410 sensors can be configured such that the sensor will operate in a number of systems: • • USB system (sensor will regulate the nominal 5V supply to 3V3 internally) with optional BJT to provide power for a companion chip. Direct drive the sensor with 3V3 (internal voltage regulators will be powered down in this mode). The next 2figures will detail the options described above: 1. Each audio output must have a capacitor (Ccomp) connected to ground to avoid any oscillation cd5410-6410f-3-0.fm 89/105 Commercial in confidence VV5410 & VV6410 Other Features Vddio Vddhi Vddcore pd Digital Logic Digital 5V Regulator Vbg Voltage Doubler 100nF Vbase VIN (5V) Vbus 390 Vout Reg3v3 VVL410 Vout 27uF Aud3v3 220nF Bandgap Audio pd_areg Regulator Vbg 5V (powered up) Vout Audio Amp Vid3v3 220nF 5V Analog pd_creg Regulator Vbg (powered up) Analog Core Vbg 100nF Key: 5V0 supply from USB cable Regulated 3V3 Figure 47 : USB Power Setup DVDD (3.3V) Vddio Vddhi Vddcore pd Digital Logic Digital 5V Regulator Vbg Voltage Doubler 100nF Vbase AVDD (3.3V) Vbus Vout Reg3v3 N/C N/C VVL410 Audio Regulator Analog Regulator Vout Aud3v3 220nF Bandgap 5V pd_areg Vbg (powered down) Vout Audio Amp Vid3v3 220nF 5V pd_creg Vbg (powered down) Analog Core Key: Analogue 3V3 supply Digital 3V3 supply Vbg 100nF Figure 48 : Direct drive @3V3 Setup 90/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 Supply Vbus Vddio Vddcore Vreg3v3 Vid3v3 Aud3v3 USB System Supply from USB cable connect to Vreg3v3 connect to Vreg3v3 optionally populate external BJT for added drive generated by internal regulator generated by internal regulator 3.3V-only System 3.3V direct drive 3.3V direct drive 3.3V direct drive BJT not populated internal regulator powered down internal regulator powered down Table 63 : Sensor Voltage Supply summary 11.4 Programmable Pins The FST and QCK pins can be re-configured to follow the values of bits 1 and 2 in the serial interface.register pin_mapping. This is to allow remote control of a electro-mechanical system, maybe two different crop settings, in a remote camera head via the serial interface. cd5410-6410f-3-0.fm 91/105 Commercial in confidence VV5410 & VV6410 Characterisation Details 12. Characterisation Details 12.1 VV5410/VV6410 AC/DC Specification Parameter Image Format Comment 356 x 292 pixels (PAL/CIF) 306 x 244 pixels (NTSC) 180 x 148 pixels (QCIF) 7.5 x 6.9 0.5µm 3 level metal CMOS CIF 81 (minimum exposure period 3µs and maximum exposure 1 period is 33ms) Units - Pixel Size Technology Array Format Exposure control range µm db Supply Voltage Operating Temp. range VOL_max2 VOH_min3 VI_maxL4 VIH_min5 Serial interface frequency range 1. 2. 3. 4. 5. 3.0-6.0 DC +/-10% 0 - 40 0.512 2.054 0.683 2.237 0-100kHz V oC V V V V We assume CIF (30fps) mode, input clock of 16MHz and internal clock divisor of 1. This is worst case reading. Device outputs had significant capacitive loading and supply voltage reduced to 2V7 This is worst case reading. Device outputs had significant capacitive loading and supply voltage reduced to 2V7 This is worst case reading. Device outputs had significant capacitive loading and supply voltage reduced to 2V7 This is worst case reading. Device outputs had significant capacitive loading and supply voltage reduced to 2V7 Table 64 : VV5410/6410 DC specification 12.2 VV5410/VV6410 Optical Characterisation Data Optical Parameter Dark Current Average Sensitivity Fixed Pattern Noise (FPN) Vertical Fixed Pattern Noise (VFPN) Random Noise Sensor SNR Shading (Gross) Min - Typical 46 2.1 1.74 1.2 1.17 c.56 0.9 Max - Units mV/sec V/lux.sec mV mV mV dB mV Table 65 : VV5410/VV6410 Optical Characterisation Data 92/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 12.2.1 Noise Parameters and Dark Current Various noise parameters are measured on the 410 device as follows: • • • • • Fixed Pattern Noise (FPN) Vertical Fixed Pattern Noise (VFPN) Random Noise Fine Shading Gross Shading The parameters will be described in more detail below along with the data produced by the characterisation programme. 12.2.2 Blooming Blooming is a phenomenon that does not affect CMOS sensors in the same way as CCD imagers are afflicted. With a CCD blooming can cause an entire column/columns to flood and saturate. CMOS imagers are however affected by a different type of saturation. If an intense light source, (e.g. Maglite torch), is shone at very close proximity to the image sensor the pixel sampling mechanism will break down and rather than displaying a saturated white light a black image will occur. The 410 pixel architecture uses Correlated Double Sampling (CDS) to help reduce noise in the system. The pixel is read normally first, yielding the true integrated signal information, then the pixel is reset and very quickly read for a second time. This normally yields black information - as the pixel has had no exposure time - that can be subtracted from the signal from the first read. This subtraction will remove much of the noise from the pixel leaving only the useful signal information. In an example where a pixel has saturated in both the first and the second reads due to an intense light source. When the noise cancellation subtraction operation is then performed the result is close to zero signal from the pixel therefore resulting in the displayed black image. We do not perform any test measurements for this phenomenon. 12.2.3 Dark Current This is defined as the rate at which the average pixel voltage increases over time with the device not illuminated. The dark current will be measured at a gain setting of 4 and a clock divisor of 16 at a fixed temperature and will be expressed in mV. 12.2.4 Fixed Pattern Noise The FPN of an image sensor is the average pixel non-temporal noise divided by the average pixel voltage. The illumination source will be white light that has been IR filtered, producing a diffuse uniform illumination at the surface of the sensor package. The FPN will be calculated at coarse exposure settings of 0,10,150,250 and 302 with gain set to 1. 10 frames are grabbed and averaged to produce a temporally independent frame before each calculation. FPN will be expressed in mV. 12.2.5 Vertical Fixed Pattern Noise VFPN describes the spatial noise in an image sensor related to patterns with a vertical orientation. The VFPN is defined as the standard deviation over all columns of the average pixel voltage for each column determined at zero exposure and zero illumination. VFPN will be expressed in mV. 12.2.6 Random Noise Random noise is the temporal noise component within the image. Random noise will be expressed in mV. 12.2.7 Shading This describes how average pixel values per “block” change across the image sensor array. For fine shading calculations the image sensor array is split into 30 pixel by 30 pixel blocks. An average value is then calculated for each block and the averages are then compared across the whole device. The blocks are increased in size to 60 pixels by 60 pixels for the gross shading calculation. Shading will be expressed in mV. cd5410-6410f-3-0.fm 93/105 Commercial in confidence VV5410 & VV6410 Characterisation Details 12.3 VV5410/VV6410 Power Consumption Operating Condition Low power mode current consumption Sleep mode current consumption1 Suspend mode current consumption (with CLKIP disabled) Normal operating mode current consumption2 Current Consumption 5.6mA 18mA 85uA 26.2mA 1. Estimated figures - this parameter was not measured during final characterisation 2. Measured while device is clocked at 16MHz and streaming CIF video at 30fps Table 66 : VV5410/6410 Current consumption in different modes 12.4 Digital Input Pad Pull-up and Pull-down Strengths Pad Type Library pulldown Library pullup Custom pullup Pads suspend scl, sda, oeb resetb Min current 35uA 25uA 66uA Max Current 52uA 42uA 250uA Table 67 : Pad Pull-up/Pull-down Strengths 94/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 13. Pixel Defect Specification 13.1 Pixel Fault Definitions Please find the pixel notation described in Figure 49 below. For the purposes of the test the 3x3 array describes 9 bayer pixels of a common colour, i.e. ALL the pixels will either be Red, Green or Blue. The pixel under test is X. [0] [7] [6] [1] X [5] [2] [3] [4] Figure 49 : Pixel Numbering Notation 13.2 Stuck at White Pixel Fault A pixel is said to be “stuck at white” - it can also be referred to as “hot” - if it is saturated (pixel output at maximum) even with no incident light and exposure set to zero. 13.3 Stuck at Black Pixel Fault A pixel is said to be “stuck at black” - it can also be referred to as “dead” - if the pixel output is zero even if the pixel is fully exposed to incident light. 13.4 Column / Row Faults A line of continuous pixel fails of length > 3 will be described as a row fault in the x-direction and a column fault in the y-direction. If the array contains more than 1 row or column fault and the defective pixels overlap as shown in Figure 50 then this fault is described as a double row or double column fault respectively. The minimum overlap is 1 pixel. A defective pixel is indicated by X and a good pixel by ‘p’. n X X X X ‘p’ ‘p’ ‘p’ n+1 ‘p’ ‘p’ p X X X X Figure 50 : Double Column Fault In Figure 51 there are 2 column faults however there is no overlap between the 2 columns therefore there are 2 single column faults but no double column faults. cd5410-6410f-3-0.fm 95/105 Commercial in confidence VV5410 & VV6410 Pixel Defect Specification n X X X X ‘p’ ‘p’ ‘p’ ‘p’ n+1 ‘p’ ‘p’ p ‘p’ X X X X Figure 51 : Single Column Faults 13.5 Image Array Blemishes The automatic test programme rejects any sensors that contain blemishes referred to as blobs and clusters (please see below for definitions of these terms) as they cannot be successfully defect corrected by ST coprocessor devices. Up to 120 single pixel faults can be corrected and sensors meeting this criteria will PASS this part of the test programme. 13.5.1 Cluster Definition A failing pixel at X with a failing pixel at position [0] or [1] or [2] or [3] or [4] or [5] or [6] or [7] or any combination of these 8 positions except the case where all positions are defective. This is a special case and is described below. In the example in Figure 52 there are additional pixel fails in positions [3] and [7]. [0] [X] [6] [1] X [5] [2] [X] [4] Figure 52 : Cluster Example Blob (special case of cluster):- a failing pixel at position X with failing pixels at position [0],[1],[2],[3],[4],[5],[6] and [7] as in Figure 53 below: [X] [X] [X] [X] X [X] [X] [X] [X] Figure 53 : Blob Example 96/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 Single pixel:- a failing pixel with no immediate failing same colour neighbours. Pixels at position [0],[1],[2],[3],[4],[5],[6] and [7] are all valid pixels. Please see Figure 54 below. [0] [7] [6] [1] X [5] [2] [3] [4] Figure 54 : Isolated pixel fail 13.5.2 Summary Pass Criteria Clusters 0 Blobs 0 Row Fails (inc doubles) 0 Column Fails (inc doubles) 0 Single pixel fails 4.8V Drive for base of external bipolar Incoming power supply 3.3 -> 6V Analog input to Audio Amplifier Analog output of Audio Amplifier (positive) Analog output of Audio Amplifier (negative) Power-on Reset (Bar) Output. DIGITAL VIDEO INTERFACE D[4] D[3] D[2] D[1] D[0] QCK LST/D[5] 27 26 25 24 20 32 28 ODT ODT Tri-stateable data qualification clock. Tri-stateable Line start output May be configured as tri-stateable output data bit 5 D[5]. FST/D[6] 29 ODT Tri-stateable Frame start signal. May be configured as tri-stateable output data bit 6 D[6]. D[7] 31 ODT Tri-stateable Data wire (ms data bit). May be configured as tri-stateable output data bit 6 D[6]. OEB 16 ID↓ Digital output (tri-state) enable. ODT Tri-stateable 5-wire output data bus. - D[4] is the most significant bit. - D[4:0] have programmable drive strengths 2, 4 and 6 mA DIGITAL CONTROL SIGNALS cd5410-6410f-3-0.fm 99/105 Commercial in confidence VV5410 & VV6410 Pinout and pin descriptions Name RESETB Pin Number 21 Type ID↑ System Reset. Active Low. Description May be configured as System Sync. Active Low. SUSPEND 12 ID↑ USB Suspend Mode Control signal. Active High If this feature is not required then the support circuit must pull the pin to ground. The combination of an active high signal and pull up pad was chosen to limit current drawn by the device while in suspend mode. SERIAL INTERFACE SCL SDA 15 14 BI↑ BI↑ Serial bus clock (input only). Serial bus data (bidirectional, open drain). SYSTEM CLOCKS CLKI 30 ID↓ Schmitt Buffered Clock input or LVDS positive Clock input Key A OA BI BI↑ BI↓ Analog Input Analog Output Bidirectional Bidirectional with internal pull-up Bidirectional with internal pull-down D ID↑ ID↓ OD ODT Digital Input Digital input with internal pull-up Digital input with internal pull-down Digital Output Tri-stateable Digital Output Name Pin Type ANALOG SIGNALS Description Vbloom VBLTW VRT 8 7 2 OA OA IA Anti-blooming pixel reset voltage1 Bitline test white level reference 2 Pixel reset voltage3 1. This pin has been removed from the production bonding diagram 2. This pin has been removed from the production bonding diagram 3. This pin has been removed from the production bonding diagram 100/105 cd5410-6410f-3-0.fm Commercial in confidence 1 2 RevNo Revision note 3 4 6 A B C D Pin Locations changed, tolerance added to O/all dims Package now 36 Pin 1.03 0.13 was 1.03 0.08 1.16 dim tolerance revised 5 7 8 ECN No. Date 14/7/99 20/7/99 15/10/99 Notes. 1. Die is optically centred. 2. Refractive index of glass is ~1.52. 3. Distance to optical surface of Die. 4. Pixel area of sensor. 2/8/99 +0.16 2.15 -0.26 +0.30 10.67 -0.13 1.55 0.16 1.16 0.09 (note 3) 15. Package Details (36pin CLCC) A CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 8.13 0.13 1.02 0.13 Commercial in confidence R 40 0.15 Pla ces Pin 6 Pin 5 Pin 1 2.67 2.02 cd5410-6410f-3-0.fm 0.00 0.60 -0.10 VV5410 & VV6410 A A-A (8 : 1) 101/105 VV5410 & VV6410 Recommended VV5410/6410 support circuit 16. Recommended VV5410/6410 support circuit 102/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 17. Evaluation kits (EVK’s) It is highly recommended that an Evaluation Kit (EVK) is used for initial evaluation and design-in of the VV5410/6410. A VV5410/ VV6410 evaluation kit can now be ordered. Please contact STMicroelectronics for details. cd5410-6410f-3-0.fm 103/105 Commercial in confidence VV5410 & VV6410 Ordering details 18. Ordering details Part Number VV5410C036 VV6410C036 STV0657 STV0672 STV0680B-001 STV-5410-R01 STV-6410-R01 STV-USB/CIF-R01 STV-YUV/CIF-R02 STV-DCA/CIF-R01 STV-5410/5500-E01 STV-6410/6500-E01 Description 36pin CLCC packaged, microlensed CIF monochrome sensor 36pin CLCC packaged, microlensed CIF ColourMOS sensor YUV/RGB CoProcessor USB companion CoProcessor Digital stills companion CoProcessor Reference design board for VV6410C036 Reference design board for VV6410C036 Reference design board for VV6410C036 & STV0672 Reference design board for VV6410C036 & STV0657-001 Reference design board for VV6410C036 & STV0680B-001 Sensor only evaluation kit for VV6410C036 & VV6500-C048 Sensor only evaluation kit for VV6410C036 & VV6500-C048 Table 69 : VV6410/VV5410 Ordering Details 104/105 cd5410-6410f-3-0.fm Commercial in confidence CMOS Sensor; Customer Datasheet, Rev 3.0,28 September 2000 cd5410-6410f Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics - All Rights Reserved Imaging Division www.st.com asiapacific.imaging@st.com centraleurope.imaging@st.com france.imaging@st.com japan.imaging@st.com nordic.imaging@st.com southerneurope.imaging@st.com ukeire.imaging@st.com usa.imaging@st.com cd5410-6410f-3-0.fm 105/105 Commercial in confidence