S24022SB

SUMMIT MICROELECTRONICS, Inc. S24042/S24043 3 and 5 Volt Systems Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs RESET FEATURES • Precision Supply Voltage Monitor — Dual reset outputs for complex microcontroller systems — Integrated memory write lockout • Guaranteed RESET (RESET#) assertion to VCC=1V • Power-Fail Accuracy Guaranteed • No External Components • 3 and 5 Volt system versions • Low Power CMOS — Active current less than 3mA — Standby current less than 25µA • Memory Internally Organized 512 X 8 — Two Wire Serial Interface (I2C™) – Bidirectional data transfer protocol – Standard 100KHz and Fast 400KHz • • High Reliability — Endurance: 100,000 erase/write cycles — Data retention: 100 years 8-Pin SOIC Packages OVERVIEW The S24042 and S24043 are power supervisory devices with 4,096 bits of serial E2PROM. They are fabricated using SUMMIT’s advanced CMOS E2PROM technology and are suitable for both 3 and 5 volt systems. The memory is internally organized as 512 x 8. It features the I2C serial interface and software protocol allowing operation on a simple two-wire bus. The S24042 provides a precision VCC sense circuit and two open drain outputs: one (RESET) drives high and the other (RESET#) drives low whenever VCC falls below VTRIP. The S24043 is identical to the S24042 with the exception being RESET is not bonded out on pin 7. BLOCK DIAGRAM VCC 22 5kHz OSCILLATOR RESET PULSE GENERATOR 2 RESET# + – VTRIP RESET CONTROL 7 RESET 1.26V SCL SDA 6 5 MODE DECODE ADDRESS DECODER WRITE CONTROL DATA I/O E2PROM MEMORY ARRAY 4 2011 T-BD 1.0 GND SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com © SUMMIT MICROELECTRONICS, Inc. 2000 2011 2.1 8/2/00 Characteristics subject to change without notice 1 S24042/S24043 PIN CONFIGURATIONS RESET #- RESET# is an active low open drain output. It is driven low whenever VCC is below VTRIP. It is also an input and can be used to debounce a switch input or perform signal conditioning. The pin has an internal pullup and should be left unconnected if the signal is not used in the system. However, when the pin is tied to a system RESET# line an external pull-up resistor should be employed. RESET - RESET is an active high open drain output. It is driven high whenever VCC is below VTRIP. RESET is also an input and can be used to debounce a switch input or perform signal conditioning. The RESET pin does have an internal pull-down and should be left unconnected if the signal is not used in the system. However, when the pin is tied to a system reset line an external pull-down resistor should be employed. NC 1 RESET# 2 NC 3 VSS 4 S24042 8 VCC 7 RESET 6 SCL 5 SDA NC 1 S24043 RESET# 2 NC 3 VSS 4 8 VCC 7 NC 6 SCL 5 SDA 2011 PCon 2.0 ENDURANCE AND DATA RETENTION The S24042/43 is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. APPLICATIONS Reset Controller Description The S24042/43 provides a precision RESET controller that ensures correct system operation during brown-out and power-up/-down conditions. It is configured with two open drain RESET outputs; pin 7 is an active high output and pin 2 is an active low output. During power-up, the RESET outputs remain active until VCC reaches the VTRIP threshold and will continue driving the outputs for approximately 200ms after reaching VTRIP. The RESET outputs will be valid so long as VCC is > 1.0V. During power-down, the RESET outputs will begin driving active when VCC falls below VTRIP. The RESET pins are I/Os; therefore, the S24042/43 can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset timeout after detecting a low to high transition and the RESET# input will initiate a reset timeout after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a reset conditioning circuit. PIN NAMES SDA SCL RESET & RESET# VSS VCC NC PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs. No Connects (NC) the no connect pins may be left floating or tied to ground. They cannot be tied high. Serial Data I/O Serial Clock Input Reset Output Ground Supply Voltage No Connect 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 2 S24042/S24043 VCC = 3.0 0r 5.0 S24042 1 Vcc 2 RESET# 3 SCL 4 Vss SDA 5 SDA RESET 6 SCL 7 RESET 8 8051 Type MCU I 2C Peripheral RESET# SCL SDA 2011 T fig01 2.0 FIGURE 1. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET SCL START Condition STOP Condition SDA In 2011 ILL5 1.0 FIGURE 2. START AND STOP CONDITIONS 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 3 S24042/S24043 SCL from Master Data Output from Transmitter Data Output from Receiver Start Condition 1 8 9 tAA tAA ACKnowledge 2011 ILL6 1.0 FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER CHARACTERISTICS OF THE I2C BUS General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are: a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 1). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy). Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock HIGH time, because changes on the data line while SCL is HIGH will be interpreted as start or stop condition, refer to Figure 10. START and STOP Conditions When both the data and clock lines are HIGH, the bus is said to be not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the “START” condition. A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the “STOP” condition (See Figure 2). DEVICE OPERATION The S24042/43 is a 4,096-bit serial E2PROM. The device supports the I2C bidirectional data transmission protocol. The protocol defines any device that sends data onto the bus as a “transmitter” and any device which receives data as a “receiver.” The device controlling data transmission is called the “master” and the controlled device is called the “slave.” In all cases, the S24042/43 will be a “slave” device, since it never initiates any data transfers. Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKnowledge that it received the eight bits of data (See Figure 3). The S24042/43 will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected, the S24042/43 will respond with an ACKnowledge after the receipt of each subsequent 8-bit word. In the READ mode, the S24042/43 transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected, and no STOP condition is generated by the master, the S24042/43 will continue to transmit data. If an ACKnowledge is not detected, the S24042/43 will terminate further data transmissions and awaits a STOP condition before returning to the standby power mode. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see figure 4). For the S24042/43 this is fixed as 1010[B]. The next two bits are don’t care. The next bit is the high order address bit A8. DEVICE IDENTIFIER DON’T CARE 1 0 1 0 X X A 8 R/W 2011 ILL7 1.1 FIGURE 4. SLAVE ADDRESS BYTE 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 4 S24042/S24043 Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to “1,” a read operation is selected; when set to “0,” a write operation is selected. WRITE OPERATIONS The S24042/43 allows two types of write operations: byte write and page write. The byte write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. Byte WRITE Upon receipt of the slave address and word address, the S24042/43 responds with an ACKnowledge. After receiving the next byte of data, it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the S24042/43 begins the internal write cycle. While the internal write cycle is in progress, the S24042/ 43 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, ACKnowledge and data transfer sequence. Page WRITE The S24042/43 is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more bytes of data. After the receipt of each byte, the S24042/ 43 will respond with an ACKnowledge. The S24042/43 automatically increments the address for subsequent data words. After the receipt of each word, the low order address bits are internally incremented by one. The high order five bits of the address byte remain constant. Should the master transmit more than 16 bytes, prior to generating the STOP condition, the address counter will “roll over,” and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 5 for the address, ACKnowledge and data transfer sequence. Acknowledges Transmitted from 24042/43 to Master Receiver If single byte-write only, Stop bit issued here. Acknowledges Transmitted from 24042/43 to Master Receiver SDA Bus Activity 1010 XXAR 8W A C Word Address K AAAAAAAA 76543210 A C K Data Byte n A C K A Data Byte n+1 C K DDDDDDDD 76543210 Data Byte n+15 C K DDDDDDDD 76543210 A A 8 0 DDDDDDDD 76543210 S T Device Type A R Address Read/Write T 0= Write S T O P Slave Address Master Sends Read Request to Slave Master Writes Word Address to Slave Master Writes Data to Slave Master Writes Data to Slave Master Writes Data to Slave Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver 2011 ILL8 1.0 Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Shading Denotes 24042/43 SDA Output Active FIGURE 5. PAGE/BYTE WRITE MODE 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 5 S24042/S24043 Acknowledge Polling When the S24042/43 is performing an internal WRITE operation, it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an acknowledge is issued, indicating that the internal WRITE cycle is complete. To poll the device, give it a START condition, followed by a slave address for a WRITE operation (See Figure 6). Internal WRITE Cycle In Progress; Begin ACK Polling READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to “1.” There are four different read options: 1. 2. 3. 4. Current Address Byte Read Random Address Byte Read Current Address Sequential Read Random Address Sequential Read Issue Start Issue Slave Address and R/W = 0 Issue Stop Current Address Byte Read The S24042/43 contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the S24042/43 receives the slave address field with the R/W bit set to “1,” it issues an acknowledge and transmits the 8-bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point, the S24042/43 discontinues data transmission. See Figure 7 for the address acknowledge and data transfer sequence. ACK Returned? No Yes (Internal WRITE Cycle is completed) Next operation a WRITE? Yes Issue Byte Address Issue Stop No Proceed with WRITE Await Next Command 2011 ILL9 1.0 FIGURE 6. ACKNOWLEDGE POLLING SDA Bus Activity 1 X XXR W A C K Data Byte 1010 S T Device Type A Address R T 1 DDDDDDDD 76543210 1 S T O P Read/Write 1= Read Slave Address Master sends Read request to Slave Lack of ACK (low) from Master determines last data byte to be read Slave sends Data to Master Slave Transmitter to Master Receiver Master Transmitter to Slave Receiver Shading Denotes 24042/43 SDA Output Active 2011 ILL 10 1.0 FIGURE 7. CURRENT ADDRESS BYTE READ MODE 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 6 S24042/S24043 Random Address Byte Read Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE) followed by the address of the word it is to read. This procedure sets the internal address counter of the S24042/43 to the desired address. After the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the R/W bit set to READ. The S24042/43 will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. At this point, the master does not acknowledge the transmission but does generate the stop condition. The S24042/43 discontinues data transmission and reverts to its standby power mode. See Figure 8 for the address, acknowledge and data transfer sequence. SDA Bus Activity 1010 S T Device Type A Address R T A XX R 8W A C K Word Address A C K XXXR W A C K Data Byte A 8 0 A AA A AA AA 765 4 32 10 1010 S T Device A Type Address R T 1 D DD DD DD D 7 65 43 21 0 1 S T O P Read/Write 0= Write Read/Write 1= Read Slave Address Master sends Read request to Slave Master Writes Word Address to Slave Slave Address Master Requests Data from Slave Lack of ACK (low) from Master determines last data byte to be read Slave sends Data to Master Master Transmitter to Slave Receiver Shading Denotes 24042/43 SDA Output Active Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver 2011 ILL11 1.0 FIGURE 8. RANDOM ADDRESS BYTE READ MODE 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 7 S24042/S24043 Sequential READ Sequential READs can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge, indicating that it requires additional data from the S24042/43. The S24042/43 continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an ACKnowledge, and issues a STOP conditions. During a sequential read operation, the internal address counter is automatically incremented with each acknowledge signal. For read operations, all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address, the address counter will ‘roll-over’ and the memory will continue to output data. See Figure 9 for the address, acknowledge and data transfer sequence. Acknowledges from 24042/43 Acknowledge from Master Receiver Lack of Acknowledge from Master Receiver SDA Bus Activity 1010 S T Device A Type R Address T XX AR W 8 A C Word Address K AAAAAAAA 76543210 A C K A XX R 8W A C K A First Data Byte C K DD DD DD DD 76 54 32 10 Last Data Byte A 8 0 1010 S T Device A Type R Address T 1 DD DD DD DD 76 54 32 10 1 S T O P Read/Write 0= Write Read/Write 1= Read Slave Address Master sends Read request to Slave Master Writes Word Address to Slave Slave Address Master Requests Data from Slave Slave sends Data to Master Lack of ACK (low) determines last data byte to be read Slave sends Data to Master Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Master Transmitter to Slave Receiver 2011 T fig09 2.0 Shading Denotes 24042/43 SDA Output Active FIGURE 9. SEQUENTIAL READ OPERATION (starting with a Random Address READ) 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 8 S24042/S24043 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ............................................................................................................................... -40°C to +85°C Storage Temperature ..................................................................................................................................... -65°C to +125°C Soldering Temperature (less than 10 seconds) ................................................................................................................... 300°C Supply Voltage ............................................................................................................................................................. 0 to 6.5V Voltage on Any Pin ....................................................................................................................................... -0.3V to VCC+0.3V ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. RECOMMENDED OPERATING CONDITIONS Characteristic VCC Operating Temperature Range Min 2.7V –40°C Max 5.5V 85°C 2011 PGM T6 1.0 DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol ICC ISB ILI ILO VIL VIH VOL Parameter Supply Current (CMOS) Standby Current (CMOS) Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Conditions SCL = CMOS Levels @ 100KHz SDA = Open All other inputs = GND or VCC SCL = SDA = VCC All other inputs = GND VIN = 0 To VCC VOUT = 0 To VCC SCL, SDA, RESET SCL, SDA IOL = 3mA SDA 0.3xVCC 0.7xVCC 0.4 VCC =5.5V VCC =3.3V VCC =5.5V VCC =3.3V Min Max 3 2 50 25 10 10 V V V 2011 PGM T1 1.0 Units mA mA µA µA µA µA AC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol Parameter SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock to Output Data Out Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Spike Width @ SCL, SDA Inputs Write Cycle Time Noise Suppression Time Constant SCL Low to SDA Data Out Valid SCL Low to SDA Data Out Change Before New Transmission Conditions 2.7V to 4.5V Min 0 4.7 4.0 4.7 4.7 4.0 4.7 0.3 0.3 1000 300 250 0 100 10 3.5 Max 100 4.5V to 5.5V Min Max 400 1.3 0.6 1.3 0.6 0.6 0.6 0.2 0.2 300 300 100 0 100 10 0.9 Units KHz µs µs µs µs µs µs µs µs ns ns ns ns ns ms fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR 2011 PGM T2 1.0 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 9 S24042/S24043 CAPACITANCE TA = 25°C, f = 100KHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max 5 8 Units pF pF 2011 PGM T3 1.0 tR tF tH IGH tLOW tSU:STO SCL tSU:SDA tHD:SDA tHD:DAT tSU:DAT tBUF SDA In tDH tAA SDA Out 2011 ILL 13 1.0 FIGURE 10. BUS TIMING 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 10 S24042/S24043 tGLITCH VTRIP VRVALID tRPD tPURST tPURST VCC RESET# tRPD RESET S24042 only 2011 T fig11 2.0 FIGURE 11. RESET OUTPUT TIMING RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS TA = -40°C to +85°C S24042/43-2.7 Symbol VTRIP tPURST tRPD VRVALID tGLITCH VOLRS VOHRS Reset Trip Point Power-Up Reset Timeout VTRIP to RESET Output Delay RESET# Output Valid Glitch Reject Pulse Width RESET# Output Low Voltage IOL= 1mA RESET Output High Voltage IOH = 800 µA VCC-.75 1 30 0.4 Parameter Min 2.55 130 Max 2.7 270 5 S24042/43–A Min 4.25 130 Max 4.5 270 5 1 30 0.4 VCC-.75 S24042/43–B Min 4.5 130 Max 4.75 270 5 1 V 30 0.4 VCC-.75 ns V V 2011 PGM T6 1.1 Unit V ms µs 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 11 S24042/S24043 Frequently the reset controller will be deployed on a PC board that provides a peripheral function to a system. Examples might be modem or network cards in a PC or a PCMCIA card in a laptop. In instances like this the peripheral card may have a requirement for a clean reset function to insure proper operation. The system may or may not provide a reset pulse of sufficient duration to clear the peripheral or to protect data stored in a nonvolatile memory. The I/O capability of the RESET pins can provide a solution. The system’s reset signal to the peripheral can be fed into the S24042/43 and it in turn can clean up the signal and provide a known entity to the peripheral’s circuits. The figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration than tPURST. The same reset output affect can be attained by using the active high reset input. RESET# Input RESET# Output RESET Output t PURST 2011 T fig12 2.0 When planning your resistor pull-up and pull-down values, use the following chart to help determine min. resistances. Worst Case RESET Sink/Source Capabilities at Various VCC Levels Parameter RESET# Output Voltage Symbol VOL Condition VCC = 1.0V, IOL=100µA VCC = 1.2V, IOL=100µA VCC = 3.0V, IOL=500µA VCC = 3.6V, IOL=500µA VCC = 4.5V, IOL=750µA VCC = 1.0V, IOL=100µA Min Typ Max 0.3 0.3 0.3 0.3 0.3 0.4 0.4 0.4 0.4 0.4 Units V V V V V V V V V V V V V V V 2011 PGM T5 1.0 RESET# Output Voltage VOL VCC = 1.2V, IOL=150µA VCC = 3.0V, IOL=750µA VCC = 3.6V, IOL=1mA VCC = 4.5V, IOL=1mA VCC = 1.0V, IOH=400µA VCC-0.75 VCC-0.75 VCC-0.5 VCC-0.5 VCC-0.5 RESET Output Voltage VOH VCC = 1.2V, IOH=800µA VCC = 3.0V, IOH=800µA VCC = 3.6V, IOH=800µA VCC = 4.5V, IOH=800µA 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 12 S24042/S24043 8 Pin SOIC (Type S) Package JEDEC (150 mil body width) .050 (1.27) TYP. .050 (1.270) TYP. 8 Places .157 (4.00) .150 (3.80) .275 (6.99) TYP. 1 .196 (5.00) .189 (4.80) .030 (.762) TYP. 8 Places .061 (1.75) .053 (1.35) FOOTPRINT .020 (.50) x45° .010 (.25) .0192 (.49) .0138 (.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .035 (.90) .016 (.40) .244 (6.20) .228 (5.80) 8pn JEDEC SOIC ILL.2 2011 2.1 8/2/00 13 SUMMIT MICROELECTRONICS, Inc. S24042/S24043 ORDERING INFORMATION S24022 Base Part Number S24022 = Reset Active High & Low S24023 = Reset Active Low Package S = 8 Lead 150mil SOIC S A T Tape & Reel Option Blank = Tube T = Tape & Reel Operating Voltage Range A = 4.5V to 5.5V VTRIP min. @ 4.25V B = 4.5V to 5.5V VTRIP min. @ 4.50V 2.7 = 2.7V to 5.5V VTRIP min. @ 2.55V 2011 Tree 2.0 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc. I2C is a trademark of Philips Corporation. 2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. 14