SMH4814SR05

SMH4814 Preliminary Information 1 (See Last Page) Dual Feed Active-ORing Programmable Hot Swap Controller FEATURES AND APPLICATIONS Eliminates Passive ORing Diodes for Reduced Power Consumption High Noise Immunity on All Logic Inputs Soft Starts Main Power Supply on Card Insertion or System Power Up with Slew Rate Control Programmable Differential Current Sense Programmable Inrush Current Limiting Master Enable to Allow System Control of Power-Up or -Down Programmable Independent Enabling of up to 4 DC/DC Converters Programmable Circuit Breaker Level and Mode Programmable Quick-Trip™ Value, Current Limiting, Duty Cycle Times, Over-Current Filter Programmable Host Voltage Fault Monitoring Programmable UV/OV Filter and Hysteresis Programmable Fault Mode: Latched or Duty Cycle Internal Shunt Regulator Allows for a Wide Supply Range INTRODUCTION The SMH4814 is an integrated power controller designed to control the hot-swapping of plug-in cards in a distributed power environment. The SMH4814 drives external power MOSFET switches that connect the supply to the load while reducing in-rush current and providing over-current protection. When the source and drain voltages of the external MOSFETs are within specification the SMH4814 asserts the four PUP logic outputs in a programmable cascade sequence to enable the DC/DC converters. The SMH4814 also monitors two independent –48V feeds. The redundant power supplies allow for high availability and reliability. The traditional method of supplying power from these feeds is via ORing power diodes, which consume a significant amount of power. The SMH4814 allows low-RDSON FETs to be used in place of ORing diodes to reduce power consumption. The SMH4814 determines when at least one of the –48V feeds is within an acceptable voltage range and switches on the appropriate FET path while providing slew rate control. The SMH4814 continuously monitors the incoming feeds and switches to the most negative feed as necessary. The SMH4814 is programmed and controlled using the I2C bus as required in ATCATM applications. • • Applications Telecom Hot-Swap Card - AdvancedTCATM Network Processors Power-on Ethernet, IEEE 802.3af SIMPLIFIED APPLICATIONS DRAWING –48V Ret. I2C RD VIN+ V12 Pin Detect SDA SCL FBB FBC PD1 UV OV FBD FBA PUPA PUPB PUPC DRAIN SENSE PUPD VOUT+ DC-to-DC Converter A ON/OFF VINVOUT- SMH4814 CBSENSE FEEDA FEEDB VGATEA VGATEB VGATE_HS VSS Pin Detect RA PD0 A d va n c e d T C A RS RB Primary Secondary TM –48V A –48V B Figure 1. The SMH4814 Controller hot-swaps and cascade sequences up to 4 DC/DC Converters and actively controls the A and B –48V feeds eliminating the need for ORing diodes and the associated voltage drop. Note: This is an applications example only. Some pins, components and values are not shown. © SUMMIT Microelectronics, Inc. 2005 • 1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897 The Summit Web Site can be accessed by “right” or “left” mouse clicking on the link: http://www.summitmicro.com/ 2080 2.0 07/21/05 1 SMH4814 Preliminary Information GENERAL DESCRIPTION The SMH4814 integrated power controller operates within a wide supply range, typically –32 to –72 volts, and generates the signals necessary to drive isolatedoutput DC/DC converters. The device accepts two independent –48V feeds via input pins FEEDA and FEEDB. The VGATEA pin controls the flow of power from FEEDA to the load. The VGATEB pin controls the flow of power from FEEDB to the load. The SMH4814 continuously monitors the voltage on FEEDA and FEEDB. The supply arbitration block in Figure 2 selects which pin drives power to the device based on the voltage level on each pin and the acceptable voltage range. Once the FEEDA or FEEDB pin is selected the SMH4814 asserts the corresponding VGATE pin. The assertion of this pin turns on the external low-RDSON FETs to supply power to the load. Start-up Procedure The general start-up procedure is as follows: 1. A physical connection must be made with the chassis to discharge any electrostatic voltage potentials when a typical add-in board is inserted into the powered backplane. 2. The board then contacts the long pins on the backplane that provide power and ground. 3. As soon as power is applied the device starts up, but it does not immediately apply power to the output load. 4. Under-voltage and over-voltage circuits inside the controller verify that the input voltage is within a user-specified range. 5. The SMH4814 senses the PD1 and PD0 pin detection signals to indicate the card is seated properly. These requirements must be met for a Pin Detect Delay period of tPDD. Once this time has elapsed the hot-swap controller enables VGATE_HS to turn on the external power MOSFET switch. The VGATE_HS output is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. During the controlled turn-on period the VDS of the MOSFET is monitored by the DRAIN SENSE input. When DRAIN SENSE drops below 2.5V, and VGATE_HS rises above V12 – VGT, the SMH4814 asserts the PUPA through PUPD power good outputs to enable the DC/DC controllers. Steady-state operation is maintained as long as all conditions are normal. Any of the following events may cause the device to disable the DC/DC controllers by shutting down the power MOSFETs: An under-voltage or over-voltage condition on the host power supply. A failure of the power MOSFET sensed via the DRAIN SENSE pin. The PD1/PD0 pin detect signals becoming invalid. The master enable (EN/TS) falls below 2.5V. Any of the FB inputs driven low by events on the secondary side of the DC/DC controllers. The occurrence of an overcurrent. The SMH4814 may be configured so that after any of these events occurs the VGATE output shuts off, and either latches into an off state or recycles power after a cooling down period, tCYC. Powering V12 The SMH4814 contains an internal shunt regulator on the V12 pin that prevents the voltage from exceeding 12V. It is necessary to use a dropping resistor (RD) between the host power supply and the V12 pin in order to limit current into the device and prevent possible damage. The dropping resistor allows the device to operate across a wide range of system supply voltages, typically –32 V to –72V, and also helps protect the device against common-mode power surges. Refer to the Applications Section for help on calculating the RD resistance value. Summit Microelectronics, Inc 2080 2.0 07/21/05 2 SMH4814 Preliminary Information INTERNAL FUNCTIONAL BLOCK DIAGRAM V12 Voltage Regulator and Reference Generator PUPA Polarity PUPA 5V_CAP CBSENSE DRAIN_SENSE SLEW VGATE_HS FBA CB Sense and Gate Control PUPB Polarity PUPB E2 Memory Configuration, Status, and Command Registers Time Slot and PUP Control FBB PUPC Polarity PUPC FBC SCL SDA I2C Interface Virtual Address A2, A1 PUPD Polarity PUPD Programmable Fault Conditions FBD FEEDA Supply Arbitration 2.5V Ref FEEDB GATEA GATEB ENTS + PO Filter PD0 PD1 UV Prog Ref Prog Hyst + Glitch Filter OV Prog Ref Prog Hyst + - UV/OV Filter FAULT# Fault Latch RESET# Glitch Filter Duty Cycle Timer Figure 2. Block Diagram Summit Microelectronics, Inc 2080 2.0 07/21/05 3 SMH4814 Preliminary Information PIN DESCRIPTION Pin No. QFN 1,2 Pin Type I Name PD0, PD1 Description The PD pins are active high, logic level inputs. Protection diodes allow them to be overdriven when used in conjunction with a series limiting resistor. The PD pins have an internal pull-down current sink of 10uA typical. The RESET# pin is used to clear latched fault conditions. When this pin is asserted, the VGATEX and PUPX outputs are immediately disabled. Refer to the section on Circuit Breaker Operation for more information. The RESET# pin has an internal pull-up current source to 5V_CAP of 10uA typical. SCL is the serial clock input. SDA is the bidirectional serial data I/O port. The PUPX outputs are programmable active high/low open drain converter enable pins. They can be used in one of 4 programmable sequence positions to switch a load or enable a DC/DC converter after a programmable delay, tPGDn. The voltage on these pins cannot exceed 12V relative to VSS. FAULT# is an open-drain, active-low output that indicates the fault status of the device. The device’s Status Register may be polled to determine more detailed information about the fault condition. This is connected to the negative side of the supply. The circuit breaker sense input is used to detect over-current conditions across an external, low value sense resistor (RS) tied in series with the Power MOSFET. A voltage drop of greater than VCB (programmable level) across the resistor for longer than tCBD trips the circuit breaker. A programmable Quick-Trip™ sense point is also available. The UV pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. VGATE_HS is enabled when the UV input > Vuv and disabled when UV < Vuv-Vuvhys. An optional programmable filter delay is also available on the UV input. The OV pin is used as an over-voltage supply monitor, typically in conjunction with an external resistor ladder. VGATE_HS is disabled when OV > Vov and enabled when OV < Vov-Vovhys. A filter delay is also available on the OV input. The Enable/Temperature Sense input is the master enable input. If EN/TS is less than 2.5V, all VGATE outputs are disabled. A capacitor connected to this pin controls the VGATE_HS Slew Rate. Connect to the -48V 'B' feed using a series 100k resistor. The voltage on this pin is compared with the voltage on the FEEDA pin internally by the supply arbitration logic to determine which voltage will be used. 3 I RESET# 4 5 6, 7, 8, 9 10 I I/O SCL SDA PUPA, PUPB, PUPC, PUPD FAULT# O O 11 12 PWR I VSS CBSENSE 13 I UV 14 I OV 15 16 17 I I I EN/TS SLEW_CNTL FEEDB Summit Microelectronics, Inc 2080 2.0 07/21/05 4 SMH4814 Preliminary Information PIN DESCRIPTION (CONTINUED) Pin No. QFN 18 Pin Type I Name FEEDA Description Connect to the -48V 'A' feed using a series 100k resistor. The voltage on this pin is compared with the voltage on the FEEDB pin internally by the supply arbitration logic to determine which voltage will be used. The DRAIN SENSE input monitors the voltage at the drain of the external power MOSFET switch with respect to VSS. An internal 10µA source pulls the DRAIN SENSE signal towards the 5V_CAP level. DRAIN SENSE must be held below 2.5V to enable the PUPX outputs. External capacitor input used to filter the device’s internal operating supply. Also a hold Capacitor to sequence down and to filter any power glitches. The VGATE_HS output activates an external power MOSFET switch. This signal controls inrush current by modulating the gate of the Hot Swap MOSFET device. It supplies a programmable current output which allows easy adjustment of the MOSFET turn-on slew rate. This pin controls the gate of the active FET on FEEDB. This pin controls the gate of the active FET on FEEDA This is the positive supply input. An internal shunt regulator limits the voltage on this pin to approximately 12V with respect to VSS. A resistor must be placed in series with the V12 pin to limit the regulator current (RD in the application schematics). Active-high, logic level input that can be used to indicate when the converter controlled by PUPD is fully powered. A hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an optoisolator. See Figures 5 and 6. Active-high, logic level input that can be used to indicate when the converter controlled by PUPC is fully powered. A hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an optoisolator. See Figures 5 and 6. Active-high, logic level input that can be used to indicate when the converter controlled by PUPB is fully powered. A hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an optoisolator. See Figures 5 and 6. Active-high, logic level input that can be used to indicate when the converter controlled by PUPA is fully powered. A hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an optoisolator. See Figures 5 and 6. 19 I DRAIN SENSE 5V_CAP VGATE_HS 20 21 O O 22 23 24 O O PWR VGATEB VGATEA V12 25 I FBD 26 I FBC 27 I FBB 28 I FBA Summit Microelectronics, Inc 2080 2.0 07/21/05 5 SMH4814 Preliminary Information PACKAGE AND PIN CONFIGURATION VGATEA 23 VGATEB 22 FBA FBB FBC FBD 25 28 27 26 PD0 PD1 RESET# SCL SDA PUPA PUPB 1 2 3 4 5 6 10 11 12 13 14 8 9 7 24 V12 21 20 19 18 17 16 15 VGATE_HS 5V_CAP DRAIN SENSE FEEDA FEEDB SLEW_CNTL EN/TS PUPC PUPD FAULT# VSS Figure 3A - 28 Pin QFN FBC FBB FBA PD0 PD1 RESET# SCL SDA PUPA PUPB PUPC PUPD FAULT# VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 FBD V12 VGATEA VGATEB VGATE_HS 5V_CAP DRAIN SENSE FEEDA FEEDB SLEW_CNTL EN/TS OV UV CBSENSE Figure 3B - 28 Pin SOIC Summit Microelectronics, Inc 2080 2.0 07/21/05 CBSENSE OV UV 6 SMH4814 Preliminary Information ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................ –55°C to 125°C Power Supply Current (IDD) ............................ 15 mA Storage Temperature ...................... –65°C to 150°C Lead Solder Temperature (10 seconds) ......... 300°C Terminal Voltage with Respect to VSS: 5V_CAP............................................. -0.3 to +7V V12, SDA, SCL, UV, OV, CBSENSE, , EN/TS, FAULT#, ......................................... –0.3 to +15V VGATE_HS, VGATEA, VGATEB PUPA, PUPB, PUPC, and PUPD ..................... -0.3 to V12+0.7V PD1, PD0, FBA, FBB, FBC, FBD, FEEDA, FEEDB, RESET#, DRAIN SENSE, SLEW_CNTL . -0.3 to 5V_CAP+0.7V Open Drain Output Short Circuit Current ...... 100mA Junction Temperature ..................................... 150°C ESD Rating per JEDEC ................................. 2000V Latch-Up testing per JEDEC .................. ±100mA RECOMMENDED OPERATING CONDITIONS Temperature Range (Industrial) ......... -40°C to 85°C (Commercial) .......... -5°C to 70°C Supply Voltage (V12) (IDD = 3 mA) ............11V to 13V Thermal Resistance (θJA) 28-pin QFN ........ 79°C/W Thermal Resistance (θJA) 28-pin SOIC ...... 80°C/W Moisture Classification Level 1 (MSL 1) per J-STD-020 Reliability Characteristics: Data Retention ................................... 100 Years Endurance ..................................100,000 Cycles Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. DC OPERATING CHARACTERISTICS Over recommended operating conditions, unless otherwise noted. All voltages are relative to VSS. Symbol V12 I12 VGATEHI VGATELO VSENSE ISENSE VENTS VENTSHYST VIH VIL VOL IIL IIL (PD) IIH (RESET#) VGT Notes: Parameter Supply Voltage Supply Current VGATEA, VGATEB, VGATE_HS High Voltage VGATEA, VGATEB, VGATE_HS Low Voltage Drain Sense Threshold Drain Sense Current EN/TS Threshold EN/TS Hysteresis RESET#, PD1, PD0, SCL, SDA, FBA, FBB, FBC, FBD FAULT#, PUPA, PUPB, PUPC, PUPD (1) Conditions I12 = 4mA Min. 11 2 V12 – VGT Typ. 12 Max. 13 13 V12 0.1 Units V mA V V V µA V mV V V V µA µA µA IGATE = 1mA VSENSE = VSS 2.45 9 2.45 3 –0.1 IOL = 3mA 0 2.50 10 2.50 10 2.55 11 2.55 5 2 0.4 1 SCL, SDA, CBSENSE, EN/TS, FBA, FBB, VIL = VSS FBC, FBD PD1, PD0 RESET# VGATE_HS Threshold 1 - This value is set by the RD resistor (see page 22, Dropper Resistor Selection). VIL = VSS VIH = 5V_CAP 1.5 10 10 2.5 4 V Summit Microelectronics, Inc 2080 2.0 07/21/05 7 SMH4814 Preliminary Information DC OPERATING CHARACTERISTICS (Continued) Over recommended operating conditions, unless otherwise noted. All voltages are relative to VSS. DC Programmable Functions (Note 2) Symbol VUV VUVHYS VOV VOVHYS VCB VCBMAX VCR VQCB IVGHS_MAX Parameter Under-Voltage Threshold Under-Voltage Hysteresis Over-Voltage Threshold Over-Voltage Hysteresis Circuit Breaker Threshold Circuit Breaker Threshold MAX Current Regulation Level Programmable Quick Trip Circuit Breaker Threshold Voltage VGATE_HS Maximum Current Conditions Default 2.864V Default 160mV Default 3.072V Default 160mV Default 50mV Default 256mV Default VCB+25% Default 100mV Default 72µA VGATE = 5V Min. -5 -5 -5 -5 -5 -5 -5 -5 –5 Typ. VUV VUVHYS VOV VOVHYS VCB VCBMAX VCR VQCB IVGHS_MAX Max. +5 +5 +5 +5 +5 +5 +5 +5 +5 Units % % % % % % % % % IVGATEA/B Programmable IVGATEA, IVGATEB Default 50µA –25 IVGATEA/B 25 % IFEED_SEL Programmable FEED current of the selected feed (A or B) Default 18µA –5 IFEED_SEL 5 % IFEED_UNSEL Programmable FEED current of the unselected feed (A or B) Default 26µA –5 IFEED_UNSEL 5 % Notes: 2 - Default values listed; refer to the Configuration Registers description for the range of values allowed. Summit Microelectronics, Inc 2080 2.0 07/21/05 8 SMH4814 Preliminary Information AC OPERATING CHARACTERISTICS Over recommended operating conditions, unless otherwise noted. All voltages are relative to VSS. Symbol tQTSD Parameter Quick Trip Shutdown Conditions Fig 10, 10% overdrive to start of VGATE_HS turn-off Min. Typ. 200 Max. Units ns AC Programmable Functions (Note 2) Symbol tCBD tPGD tCYC tPUOVF tPDD tSTT tGLITCH tPCR Notes: Parameter Conditions Min. -15 -15 –15 –15 –15 -15 -15 –15 Typ. tCBD tPGD tCYC tPUOVF tPDD tSTT tGLITCH tPCR Max. +15 +15 +15 +15 +15 +15 +15 +15 Units % % % % % % % % Programmable Over-Current Glitch Filter Default 40µs (2) Programmable Power Good Delay Default 64ms (2) Circuit Breaker Cycle Mode Cycle Time Default 5.4s (2) Programmable Under/Over-Voltage Filter Default 64ms (2) Programmable Pin Detect Delay Programmable Sequence Termination Timer Glitch Filter Programmable Current Regulation Default 64ms (2) Default 64ms (2) Default 40µs (2) Default 64ms (2) 2 - - Default values listed; refer to the Configuration Registers description for the range of values allowed. Summit Microelectronics, Inc 2080 2.0 07/21/05 9 SMH4814 Preliminary Information I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100/400kHz Over recommended operating conditions, unless otherwise noted. All voltages are relative to VSS. See Figure 4 Timing Diagram. 100kHz 400kHz Symbol Description Conditions Min Typ Max Min Typ Max Units fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock Edge to Data Valid Data Output Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Filter SCL and SDA Write Cycle Time Noise suppression Memory Array SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change Note 1/ Note 1/ Before New Transmission - Note 1/ 0 4.7 4.0 4.7 4.7 4.0 4.7 0.2 0.2 100 0 1.3 0.6 1.3 0.6 0.6 0.6 400 KHz µs µs µs µs µs µs 3.5 0.2 0.2 0.9 µs µs 1000 300 250 0 100 5 150 0 100 1000 300 ns ns ns ns ns 5 ms Note: 1/ - Guaranteed by Design. TIMING DIAGRAMS tR SCL t SU:SDA SDA ( IN) tF tHD:SDA tHIGH tW R (For W rite Operation O nly) tLOW tSU:DAT tSU:STO tBUF t HD:DAT tAA SDA ( OUT) tDH Figure 4 . Basic I2C serial interface timing diagram for the Bus Interface and Memory timing. The table above lists the AC timing parameters. One bit of data is transferred during each clock pulse. Note that data must remain stable when the clock is high. Summit Microelectronics, Inc 2080 2.0 07/21/05 10 SMH4814 Preliminary Information TIMING DIAGRAMS (CONTINUED) 0 PUPA FBA