SMM150

SMM150 Preliminary Information 1 (See Last Page) Single-Channel Supply Voltage Marginer/Monitor FEATURES • Capable of margining supplies with trim inputs using either positive or negative trim pin control • Wide Margin range from 0.3V to VDD using internal reference • 10-bit ADC readout of supply voltage over I2C bus • Margining Controlled Via: I2C Command Input Pins (MUP, MDN) • Two programmable general purpose sensor inputs (COMP1/2) – UV/OV with FAULT Output • Programmable glitch filter (COMP1/2) • Programmable internal VREF, 0.5V or 1.25V • Operates from 2.7V to 5.5V supply • General Purpose 256-Byte EEPROM with Write Protect • I2C 2-wire serial bus for programming configuration and monitoring status • 28 lead QFN • 20 ball Ultra CSPTM (Chip-Scale) package INTRODUCTION The SMM150 is a highly accurate power supply voltage supervisor and environmental monitor with provisions for voltage margining of the monitored supply. The part includes an internal voltage reference to accurately monitor and margin the supply to within ±1%. The SMM150 has the capability to margin over a wide range from 0.3V to VDD using the internal reference and can read the value of the supply over the I2C bus using an on-chip 10-bit ADC. The monitor and margin levels are set using the I2C serial bus. The SMM150 initiates margining via the I2C bus or by using the MUP or MDN inputs. Once the pre-programmed margin target voltage is reached, the SMM150 holds the converter at this voltage until receiving an I2C command or de-asserting the margin input pin. When the SMM150 is not margining, the TRIM output pin is held in a high impedance state allowing the converter to operate at its nominal set point. Two general purpose input pins are provided for sensing under or overvoltage conditions. A programmable glitch filter associated with these inputs allows the user to ignore spurious noise signals. A FAULT# pin is asserted once either input set point is exceeded. Using the I2C interface, a host system can communicate with the SMM150 status register and utilize 256-bytes of nonvolatile memory. Applications • In-system test and control of Point-of-Load (POL) Power Supplies for Multi-voltage Processors, DSPs and ASICs • Routers, Servers, Storage Area Networks SIMPLIFIED APPLICATIONS DRAWING 2.7V-5.5V VDD VDD_CAP COMP1 V1 GND Margin Commands Status Outputs MUP MDN FAULT# READY COMP2 SMM150 SDA SCL TRIM CAPM A0 A1 A2 WP VM TRIM VOUT+ SEN+ I2C Interface DC-DC Converter Figure 1 – Applications using the SMM150 Controller to control the Voltage Margining of a DC/DC Converter. Note: This is an applications example only. Some components and values are not shown. © SUMMIT Microelectronics, Inc. 2005 • 1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897 2075 2.6 05/13/05 www.summitmicro.com 1 SMM150 Preliminary Information GENERAL DESCRIPTION The SMM150 is capable of margining the DC output voltage of LDOs or DC/DC converters that use a trim/adjust pin. The Margin function is programmable over a standard 2-wire I2C serial data interface and is used to set the margin low/high DC output voltages. In margining mode the user communicates with the SMM150 via the I2C serial data bus to select the desired values for margining. This allows the part to margin the supplies up or down to these set values either through asserting the MUP and MDN pins or by writing to the margin register directly. The margin high and margin low voltage settings can range from 0.3V to VDD around the converter’s nominal output voltage setting depending on the specified margin range of the DC-DC converter and/or system components, usually ±10%. When the SMM150 receives the command to margin, the TRIM output will begin adjusting the supply to the selected margin voltage. This is accomplished by incrementing (or decrementing) an internal counter based on the digital comparison between the voltage margin target value and that read by the ADC from the VM input. This operation is repeated until the 2 values are equal, after which the SMM150 holds the TRIM output pin at the voltage required to maintain the margin setting. An I2C command or de-assertion of the MUP/MDN pin will return the TRIM output pin to a high impedance state thus allowing the converter to return to its nominal operating voltage. The SMM150 has two additional input pins and one additional output pin. The input pins, COMP1 and COMP2, are high impedance inputs, each connected to a comparator and compared against the internal reference (VREF, 0.5V or 1.25V). Each comparator can be independently programmed to monitor for UV or OV. When either of the COMP1 or COMP2 inputs are in fault the open-drain FAULT# output will be pulled low. A configuration option exists to disable the FAULT# output during margining. Programming of the SMM150 is performed over the industry standard I2C 2-wire serial data interface. A status register is available to read the state of the part and a Write Protect (WP) pin is available to prevent writing to the configuration registers and EE memory. Summit Microelectronics, Inc 2075 2.6 05/13/05 2 SMM150 Preliminary Information INTERNAL BLOCK DIAGRAM READY FAULT# VDD VDD_CAP GND VREF VREF = 1.25V or 0.5V COMP1 OV/UV Output Control Glitch Filter OV/UV VREF COMP2 50kΩ Up/Dn MUP MDN Margin Target Digital Comparator Halt Control Logic 8-bit DAC SW1 TRIM 50kΩ Clock A0 A1 A2 SCL SDA WP I2C Interface 10Bit ADC MUX SW2 VM EE Configuration Registers & Memory CAPM Figure 2 – SMM150 Controller Internal Block Diagram. PACKAGE AND PIN CONFIGURATION 28 Pad QFN Top View 20 Ball Ultra CSPTM Bottom View SDA NC NC MDN MUP VDD_CAP NC Pin 1 SCL MDN VDD_CAP VDD Pin 1 28 27 26 25 24 23 22 A1 21 20 A2 SDA A3 TRIM A4 COMP1 SCL A2 NC A1 READY A0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND SMM150 or NC 19 18 17 16 15 VDD TRIM COMP1 NC NC NC NC A2 B1 A1 B2 READY B3 MUP B4 NC C1 A0 C2 WP C3 FAULT# C4 NC D1 GND D2 E2 D3 E3 D4 VM CAP_M COMP2 WP NC CAP_M FAULT# COMP2 NC VM E1 E4 Summit Microelectronics, Inc 2075 2.6 05/13/05 3 SMM150 Preliminary Information PIN DESCRIPTIONS QFN Pad Number 28 1 2 4 6 8 10 20 14 21 23 7 24 25 19 12 Ultra CSPTM Ball Number B2 A1 B1 C1 D1 D2 E2 B3 E4 A4 A3 E1 C3 A2 B4 E3 Pin Type I/O I I I I I CAP O I PWR PWR GND I I I I Pin Name SDA SCL A2 A1 A0 WP CAPM TRIM VM VDD VDD_CAP GND MUP MDN COMP1 COMP2 I2C Bi-directional data line I2C clock input. Pin Description The address pins are biased either to VDD, GND or left floating. This allows for a total of 21 distinct device addresses. When communicating with the SMM150 over the 2-wire bus these pins provide a mechanism for assigning a unique bus address. Programmable Write Protect active high/low input. When asserted, writes to the configuration registers and general purpose EE are not allowed. The WP input is internally tied to VDD with a 50KΩ resistor. External capacitor input used to filter the VM input, 0.2µF. Output voltage used to control and/or margin converter voltages. Connect to the converter trim input. Voltage monitor input. Connect to the DC-DC converter positive sense line or its’ +Vout pin. Power supply of the part. External capacitor input used to filter the internal VDD supply rail. Ground of the part. The SMM150 ground pin should be connected to the ground of the device under control or to a star point ground. PCB layout should take into consideration ground drops. Margin up command input. Asserted high. The MUP input is internally tied to VDD with a 50KΩ resistor. Margin down command input. Asserted high. The MDN input is internally tied to VDD with a 50KΩ resistor. COMP1 and COMP2 are high impedance inputs, each connected internally to a comparator and compared against the internally programmable VREF voltage. Each comparator can be independently programmed to monitor for UV or OV. The monitor level is set externally with a resistive voltage divider. When either of the COMP1 or COMP2 inputs are in fault the opendrain FAULT# output will be pulled low. A configuration option exists to disable the FAULT# output while the device is margining. Programmable active high/low open drain output indicates that VM is at its set point. When programmed as an active high output, READY can also be used as an input. When pulled low, it will latch the state of the comparator inputs. No Connect. The bottom side metal plate (Pad 29) can be connected to GND or left floating. 11 D3 O FAULT# 5 3, 9, 13, 15-18, 22, 26, 27, 29 C2 I/O READY C4, D4 NC NC Summit Microelectronics, Inc 2075 2.6 05/13/05 4 SMM150 Preliminary Information Temperature Under Bias ...................... -55°C to 125°C Storage Temperature QFN ................... -65°C to 150°C Terminal Voltage with Respect to GND: VDD Supply Voltage ..........................-0.3V to 6.0V All Others ................................-0.3V to VDD + 0.7V FAULT#…………………………….… GND to 15.0V Output Short Circuit Current ............................... 100mA Reflow Solder Temperature (10 secs)….………....240°C Junction Temperature.........................…….....…...150°C ESD Rating per JEDEC……………………..……..2000V Latch-Up testing per JEDEC………..……......…±100mA Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Temperature Range (Industrial) .......... –40°C to +85°C (Commercial).............. 0°C to +70°C VDD Supply Voltage.................................. 2.7V to 5.5V Inputs.........................................................GND to VDD Package Thermal Resistance (θJA) 28 Pad QFN…………….…………………….…80oC/W 20 Ball Ultra CSPTM………..………….…….…TBDoC/W Moisture Classification Level 1 (MSL 1) per J-STD- 020 RELIABILITY CHARACTERISTICS Data Retention……………………………..…..100 Years Endurance……………………….……….100,000 Cycles DC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min. Typ. Max Unit VDD VM IDD ITRIM VTRIM VADOC VIH VIL VOL VAIH VAIL IAIT OV/UV VHYST RPull-Up Supply Voltage Positive Sense Voltage Power Supply Current from VDD TRIM output current through 100Ω to 1.0V TRIM output voltage range Margin Range Input High Voltage SDA,SCL,WP,MUP,MDN Input Low Voltage SDA,SCL,WP,MUP,MDN Open Drain Output FAULT#, READY Address Input High Voltage, A2, A1, A0 Address Input Low Voltage, A2, A1, A0 Address Input Tristate Maximum Leakage – High Z Monitor Voltage Range COMP1/2 DC Hysteresis Input Pull-Up Resistors VM pin TRIM pin floating TRIM Sourcing Max Current TRIM Sinking Max Current ITRIM ±1.5mA Depends on Trim range of DCDC Converter VDD = 2.7V VDD = 5.0V VDD = 2.7V VDD = 5.0V ISINK = 1mA VDD = 2.7V, Rpullup≤300kΩ VDD = 5.0V, Rpullup≤300kΩ VDD = 2.7V, Rpulldown≤300kΩ VDD = 5.0V, Rpulldown≤300kΩ VDD = 2.7V VDD = 5.0V COMP1 and COMP2 pins COMP1 and COMP2 pins, VTH-VTL (see Note 1) See Pin Descriptions 0.9xVDD 0.7xVDD 2.7 0.3 3 1.5 -1.5 GND 0.3 0.9xVDD 0.7xVDD 2.5 VDD VDD VDD 0.1xVDD 0.3xVDD 0.2 VDD VDD 0.1xVDD 0.3xVDD +1.4 +1.6 VDD 10 50 3.3 5.5 VDD V V mA mA mA V V V V V V V µA V mV kΩ -1.8 -2.0 0 Note 1 – The Base DC Hysteresis voltage is measured with a 1.25V external voltage source. The resulting value is determined by subtracting Threshold Low from Threshold High, VTH-VTL while monitoring the FAULT# pin state. Base DC Hysteresis is measured with a 1.25V input. Actual DC Hysteresis is derived from the equation: (VIN/VREF)(Base Hysteresis). For example, if VIN=2.5V and VREF=1.25V then Actual DC Hysteresis= (2.5V/1.25V)(0.003V)=6mV. Summit Microelectronics, Inc 2075 2.6 05/13/05 5 SMM150 Preliminary Information DC OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min. Typ. Max Unit VREF=1.25V 1.24 1.25 1.26 VREF VREF Internal Reference V VREF=0.5V 0.496 0.500 0.504 MARGACC Margin Accuracy -1.0 ±0.75 +1.0 % AC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min. Typ. Max Unit Update period for ADC Monitor sampling/conversion conversion and DAC tADC_DAC 1.8 ms period update tMARG_I/D Margin single bit increment or decrement time TMARG_UPDATE = (X)(1.8ms) where: X=step number of possible 256 and 1 step=5mV 1.8 0 15 ms µs µs µs µs ms ms ms ms tGLITCH Programmable glitch filter times 40 120 2.5 5 tMARGIN Programmable Margin Delay Times Note 1 – See Figure 4 10 17.5 Summit Microelectronics, Inc 2075 2.6 05/13/05 6 SMM150 Preliminary Information I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100kHz Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 3 Timing Diagram. Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR Description SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock Edge to Data Valid Data Output Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Filter SCL and SDA Write Cycle Time Conditions Min 0 4.7 4.0 Typ Max 100 Units KHz µs µs µs µs µs µs Before New Transmission - Note 1/ 4.7 4.7 4.0 4.7 SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change Note 1/ Note 1/ 0.2 0.2 3.5 µs µs 1000 300 250 0 ns ns ns ns Noise suppression 100 5 ns ms Note: 1/ - Guaranteed by Design. TIMING DIAGRAMS tR SCL tSU:SDA SDA ( IN) tF t HD:SDA tHIGH t W R (For W rite O peration Only) t LOW tSU:DAT tSU:STO tBUF tHD:DAT tAA SDA ( OUT) t DH Figure 3. Basic I2C Serial Interface Timing Summit Microelectronics, Inc 2075 2.6 05/13/05 7 SMM150 Preliminary Information APPLICATIONS INFORMATION DEVICE OPERATION POWER SUPPLY The SMM150 can be powered by a 2.7V to 5.5V input to the VDD pin (Figure 1). Care should be exercised that noise from the DC/DC converter is filtered from the SMM150 VDD pin. See figure 6 for suggestions. VOLTAGE REFERENCE The SMM150 uses an internal voltage reference, VREF with a user programmable level of 0.5V or 1.25V. Total accuracy of VREF is ±0.8% over temperature and supply variations. For DC/DC converters that have output voltages below 1.25V, set the internal VREF to 0.5V. MODES OF OPERATION The SMM150 has two basic modes of operation: UV and OV monitoring mode and supply margining mode. A detailed description of each mode and feature follows. A flow diagram is shown in Figure 5. MARGIN MODE The SMM150 can control margining of a DC/DC converter that has a trim pin or any regulator having access to its feedback node. The TRIM pin on the SMM150 is connected to the trim input pin on the power supply converter. A sense line from the converter’s point-of-load connects to the VM input. The margin function begins upon an I2C command or assertion of the MUP/MDN pins. The TRIM pin is driven by a DAC whose input is incremented or decremented every 200µS based on the digital DC/DC Supply Margin N/H/L comparison of the margin target value and the actual converter output voltage. The voltage on the TRIM output will continue increasing (decreasing) until the converter’s output voltage equals the target margin voltage. This voltage adjustment allows the SMM150 to control the margined output voltage of the power supply converter to within ±1.0% in an open-loop manner. The converter is held at the margin voltage until the SMM150 receives an I2C command or the respective MUP/MDN pin is de-asserted. When not margining, the TRIM pin on the SMM150 is in a high impedance state. The voltage on the TRIM pin is buffered and applied to the ADC at the beginning of a margin cycle to ensure the converter is margined from its nominal setpoint. This allows a smooth transition from the converter’s nominal voltage to the SMM150 controlling that margin voltage to the margin target setting. After margining high, low or nominal, issuing a margin Off command will cause the trim pin to go high impedance. The part margin time from Off to High or Off to Low is specified as a typical according to the equation: TMARG_UPDATE = (X)(1.8ms) where: X=step number of possible 256 and 1 step=5mV The Active Margin Command Delay Time using the MUP and MDN pins is shown in Figure 4 GND Turn on Time TMARGIN_UPDATE SMM150 Total Margin Delay Time MPU/D/EN tMARGIN - Internal Programmable Active Margin Delay Time tADC_DAC ADC/DAC tADC_DAC ADC/DAC Sample/ Sample/ Conversion time Conversion time 1.8ms 1.8ms Figure 4 – Margin Delay Time Summit Microelectronics, Inc 2075 2.6 05/13/05 8 SMM150 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) MARGINING OPERATION NO POWER OK? YES INPUT VTRIM TO ADC DUMP ADC INTO DAC DAC DRIVES BRICK (TRIM OUTPUT LO-Z) INPUT VOUT TO ADC ADC EQUAL TARGET? NO YES INCREMENT/ DECREMENT DAC 1. HOLD DAC 2. CLEAR STATUS REGISTER 3. WAIT FOR NEXT COMMAND Figure 5 - SMM150 Margin Flow Chart Summit Microelectronics, Inc 2075 2.6 05/13/05 9 SMM150 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) When measuring the delay time external to the device, ADC sample time and Update Trim time (≅ 4ms) must be added to the internally programmed delay time as shown: Spec Actual measurement 2.5 ms 6.5 ms 5 ms 9 ms 10 ms 14 ms 17.5 ms 22 ms MONITOR The SMM150 monitors the COMP1 and COMP2 pins. COMP1 and COMP2 are high impedance inputs, each connected internally to a comparator and compared against the programmable internal reference voltage. Each comparator can be independently programmed to monitor for either UV or OV. The monitor level is set externally with a resistive voltage divider. The COMP pins can be connected to Vin, Vout or any voltage that needs to be monitored. The internal comparators COMP1/2 are compared to VREF, so the voltage dividers are set above or below the programmed VREF level depending on whether monitoring UV or OV. As an example, with VREF set to 1.25V, to monitor an OV of 1.7V on COMP1 and a UV of 1.3V on COMP2, the voltage divider resistors are: For OV, RUpper = 1.37k, 1% RLower = 3.83k, 1%. For UV, RUpper = 1.02k, 1% RLower = 25.5k, 1%. The part can be programmed to trigger the FAULT# pin when either COMPx comparator has exceeded the UV or OV range. The READY and FAULT# outputs of the SMM150 are active as long as the triggering limit remains in a fault condition. The READY pin is programmable active high/low open drain output indicates that VM is at its’ set point. When programmed as an active high output, READY can also be used as an input. When pulled low, it will latch the state of the comparator inputs. When either of the COMP1 or COMP2 inputs are in fault, the opendrain FAULT# output will be pulled low. A configuration option exists to disable the FAULT# output while the device is in margining mode. STATUS REGISTER A status register exists for I2C polling of the status of the COMP1 and COMP2 inputs. Two bits in this status register reflect the current state of the inputs (1 = fault, 0 = no fault). Two additional bits show the state of the inputs latched by one of two events programmed in the configuration. The first event option is the FAULT# output going active. The second event option is the READY pin going low. The READY pin is an I/O. As an output, the READY output pin goes active when the DC controlled voltages are at their set point. As an input programmed to active high, it can be pulled low externally and latch the state of the COMP inputs. This second event option allows the state of the COMP inputs on multiple devices to be latched at the same time while a host monitors their FAULT# outputs. MARGINING The SMM150 has two additional control voltage settings: margin high and margin low. The margin high and margin low settings can be as much as ±10% of the nominal setting depending on the manufacturer. The margin high and margin low voltage settings can range from 0.3V to VDD around the converters’ nominal output voltage setting depending on the specified margin range of the DC-DC converter. These settings are stored in the configuration registers and are loaded into the control voltage setting by margin commands issued via the I2C bus. The margin command registers contain two bits that decode the commands to margin high or margin low. Once the SMM150 receives the command to margin the supply voltage, it begins adjusting the supply voltage to move toward the desired setting. When this voltage setting is reached, a bit is set in the margin status registers and the READY signal becomes active. Note: Configuration writes or reads of registers 00HEX to 03HEX should not be performed while the SMM150 is margining. FAULTS When either of the COMP1 or COMP2 inputs are in fault, the open-drain FAULT# output will be pulled low. A configuration option exists to disable the FAULT# output while the device is margining. If “Fault Output Disabled while Margining” is selected, Faults are disabled for all margining except when margining to the ‘Off’ and ‘Nominal’ states. Also, the programmable feature ‘Fault Holds Off and Shutdown Control’ is enabled only for the Nominal margin state. Summit Microelectronics, Inc 2075 2.6 05/13/05 10 SMM150 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) Fault Latched by a Fault Condition: The “Fault Latched by a Fault Condition” programmable option is triggered only on the leading edge of a Fault. That is, a latched fault can be cleared while the Fault yet exists. Fault Latched by Ready I/O Pin: Fault Latched by Ready I/O pin functions on the margin transitions from Off to Hi/Low/Nominal or from Nominal to Hi/Low or Hi/Low to Nominal but not from Hi/Low/Nominal to Off. WRITE PROTECTION Write protection for the SMM150 is located in a volatile register where the power-on state is defaulted to write protect. There are separate write protect modes for the configuration registers and memory. In order to remove write protection, the code 55HEX is written to the write protection register. +VIN - 2.7V to 5.5V READY MDN MUP Vdd FAULT# R3 20 U3 Vdd 1 2 D1 DIODE J1 1 3 5 7 9 Gnd SCL Gnd3 SDA Rsrv5 MR +10V Rsrv8 +5V Rsrv10 2 4 6 8 10 1 28 8 6 4 2 7 SCL SDA WP A0 A1 A2 GND J2 1 2 25 24 C1 0.01uF C2 0.1uF C3 10uF C8 0.1uF 21 11 5 7 8 11 9 C9 0.01uF U2 +Vin +Vin Enable +Vin Gnd Gnd Other codes will enable write protection. For example, writing 59HEX will allow writes to the configuration register but not to the memory, while writing 35HEX will allow writes to the memory but not to the configuration registers. The SMM150 also features a Write Protect pin (WP input) which, when asserted, prevents writing to the configuration registers and EE memory. In addition to these two forms of write protection there is a configuration register lock bit which, once programmed, does not allow the configuration registers to be changed. A2, A1, A0 The address bits A[2:0] can be hard wired High or Low or may be left open (High-Z) to allow for a total of 21 distinct device addresses. When floating, the inputs can tolerate the amount of leakage as described by the specification IAIT. An external 100k pull-up or pull down resistor is sufficient to set a High or Low logic level. DC-DC Converter VOUT = 1.5V +Vout +Vout +Vout Sense Trim 1 2 4 3 10 READY VDD Programming Supply COMP2 12 14 C10 0.1uF R4 2.5k 10 C4 0.02uF C6 0.01uF R5 1.37K 1% R7 1.02K 1% SMM150 VM TRIM 20 I2C SMX3200 Connector CAP_M VDD_CAP NC NC NC NC NC NC NC NC NC NC R6 3.83K 1% R8 C7 0.01uF 25.5K 1% 3 9 13 15 16 17 18 22 26 27 23 C5 1uF Figure 6 – Typical applications schematic which shows the SMM150 controlling a 3.3V in/1.5V out DC/DC converter. Care should be taken to filter DC/DC converter noise from the SMM150 VDD supply pin. This is accomplished with optional components R3, C1, C2, C3 and C10. This example, using a 1.25V VREF, also shows the COMP1/2 pins monitoring the DC/DC converter VOUT set to an OV of 1.7V on COMP1 and a UV of 1.3V on COMP2, the voltage divider resistors are: For OV, R5 = 1.37k, 1% R6 = 3.83k, 1%, For UV, R7= 1.02k, 1% R8 = 25.5k, 1%. The jumper J2 can be used to supply the SMM150 VDD voltage from the SMX3200 programmer when the device is programmed with board power off and the controlled supply unloaded. 5 6 MDN MUP FAULT# COMP1 19 Summit Microelectronics, Inc 2075 2.6 05/13/05 11 SMM150 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) Maximizing Accuracy Maximum margining accuracy is obtained by placing a resistor between the SMM150 TRIM output and the TRIM input of the converter. From the manufacturer’s data sheet obtain the value of the internal voltage reference and equivalent TRIM input series resistance. Figure 7 below displays the internal trimming circuit for a typical isolated DC-DC converter. In this example, the converter uses positive trimming, i.e., an increase in voltage at the TRIM pin causes an increase in output voltage. V+ VREF +S R1 DC-DC Converter V-S L O A D SMM150 TRIM Pin RTRIM TRIM R2 VREF Figure 7 - Simplified TRIM circuit of an isolated DC-DC converter connects to SMM150 TRIM output For this example RTRIM is found: The next example applies to most non-isolated DC-DC converters, LDO’s and in-system designed converters using monolithic PWM controllers. Figure 8 is a simplified schematic showing the resistor divider network used to close the loop from the output to the circuit’s feedback node. These type circuits employ negative trimming, meaning any decrease in voltage into the feedback node cause an increase in output voltage.  (VREF ×k ) -0.3  R 2×    (VREF -0.3)  RTRIM = ( k×VREF -0.3) 1(VREF -0.3) Where: VM arg( Low) k= VNom 0.3 = TRIM output saturation voltage Vnom = Nominal (non-trimmed output voltage) RTRIM = k= R1× (VREF -0.3) VNom× ( k -1) VM arg( High) VNom 0.3 = TRIM output saturation voltage Vnom = Nominal (non-trimmed output voltage) VOUT SMM150 TRIM Pin RTRIM R1 To FB node (VREF) R2 Figure 8 - Simplified TRIM circuit of a non-isolated DC-DC converter connects to SMM150 TRIM output Summit Microelectronics, Inc 2075 2.6 05/13/05 12 SMM150 Preliminary Information DEVELOPMENT HARDWARE & SOFTWARE The end user can obtain the Summit SMX3200 programming system for device prototype development. The SMX3200 system consists of a programming Dongle, cable and WindowsTM GUI software. It can be ordered on the website or from a local representative. The latest revisions of all software and an application brief describing the SMX3200 is available from the website (www.summitmicro.com). The SMX3200 programming Dongle/cable directly between a PC’s parallel port and application. The device is then configured via an intuitive graphical user interface drop-down menus. interfaces the target on-screen employing The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMM150 via the programming Dongle and cable. An example of the connection interface is shown in Figure 9. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. D1 Positive Supply Jumper 1N4148 VDD Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector. Pin 10, Reserved Pin 8, Reserved Pin 6, MR# Pin 4, SDA Pin 2, SCL Pin 9, 5V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND SMM150 WP SDA SCL 10 8 6 4 2 9 7 5 3 1 C1 0.1µF GND Common Ground Figure 9– SMX3200 Programmer I2C serial bus connections to program the SMM150. The SMM150 has a Write Protect pin (WP input) which when, asserted, prevents writing to the configuration registers and EE memory. In addition, there is a configuration register lock bit, which, once programmed, does not allow the configuration registers to be changed. Summit Microelectronics, Inc 2075 2.6 05/13/05 13 SMM150 Preliminary Information I2C PROGRAMMING INFORMATION SERIAL INTERFACE Access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standard 2-wire serial interface (I2C). SDA is a bi-directional data line and SCL is a clock input. Data is clocked in on the rising edge of SCL and clocked out on the falling edge of SCL. All data transfers begin with the MSB. During data transfers SDA must remain stable while SCL is high. Data is transferred in 8-bit packets with an intervening clock period in which an Acknowledge is provided by the device receiving data. The SCL high period (tHIGH) is used for generating Start and Stop conditions that precede and end most transactions on the serial bus. A high-to-low transition of SDA while SCL is high is considered a Start condition while a low-to-high transition of SDA while SCL is high is considered a Stop condition. The interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. The address byte is comprised of a 4-bit device type identifier (slave address) and a unique (three-state) 3-bit bus address. The remaining bit indicates either a read or a write operation. Refer to Table 1 for a description of the address bytes used by the SMM150. Refer to Table 2 for an example of the unique address handling of the SMM150. The device type identifier for the memory array, the configuration registers and the command and status registers are accessible with the same slave address. It can be set using the address pins as described in table 2. The bus address bits A[2:0] are hard wired only through address pins 2, 4 and 6 (A2, A1 and A0) or may be left open (Z) to allow for a total of 21 distinct device addresses. The bus address accessed in the address byte of the serial data stream must match the setting on the SMM150 address pins. WRITE Writing to the memory or a configuration register is illustrated in Figures 10, 11, 12, 14, 15 and 17. A Start condition followed by the address byte is provided by the host; the SMM150 responds with an Acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMM150 responds with an acknowledge; the host then clocks in one byte of data. For memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. After the last byte is clocked in and the host receives an Acknowledge, a Stop condition must be issued to initiate the nonvolatile write operation. READ The address pointer for the configuration registers, memory, command and status registers and ADC registers must be set before data can be read from the SMM150. This is accomplished by issuing a dummy write command, which is simply a write command that is not followed by a Stop condition. The dummy write command sets the address from which data is read. After the dummy write command is issued, a Start command followed by the address byte is sent from the host. The host then waits for an Acknowledge and then begins clocking data out of the slave device. The first byte read is data from the address pointer set during the dummy write command. Additional bytes can be clocked out of consecutive addresses with the host providing an Acknowledge after each byte. After the data is read from the desired registers, the read operation is terminated by the host holding SDA high during the Acknowledge clock cycle and then issuing a Stop condition. Refer to Figures 13, 15 and 18 for an illustration of the read sequence. WRITE PROTECTION The SMM150 powers up into a write protected mode. Writing a code to the volatile write protection register (write only) can disable the write protection. The write protection register is located at address 38HEX. Writing to the write protection register is shown in Figure 10. Writing 0101BIN to bits [7:4] of the write protection register allow writes to the general-purpose memory while writing 0101BIN to bits [3:0] allow writes to the configuration registers. The write protection can be reenabled by writing other codes (not 0101BIN) to the write protection register. Summit Microelectronics, Inc 2075 2.6 05/13/05 14 SMM150 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) CONFIGURATION REGISTERS The majority of the configuration registers are grouped with the general-purpose memory. Writing and reading the configuration registers is shown in Figures 11, 12 and 13. See Application Note 46 for a complete description. Note: Configuration writes or reads of registers 00 to 03HEX should not be performed while the SMM150 is margining. GENERAL-PURPOSE MEMORY The 256-byte general-purpose memory is located at any slave address. The bus address bits are hard wired by the address pins A2, A1 and A0. They can be tied low, high or left floating, (Z). Memory writes and reads are shown in Figures 14, 15 and 16. Slave Address Bus Address COMMAND AND STATUS REGISTERS Writes and reads of the command and status registers are shown in Figures 17 and 18. GRAPHICAL USER INTERFACE (GUI) Device configuration utilizing the Windows based SMM150 graphical user interface (GUI) is highly recommended. The software is available from the Summit website (www.summitmicro.com). Using the GUI in conjunction with this datasheet simplifies the process of device prototyping and the interaction of the various functional blocks. A programming Dongle (SMX3200) is available from Summit to communicate with the SMM150. The Dongle connects directly to the parallel port of a PC and programs the device through a cable using the I2C bus protocol. See Figure 5 and the SMX3200 Data Sheet. Register Type Configuration Registers are located in 00 HEX thru 05HEX and 30 HEX thru 3EHEX General-Purpose Memory is located in 40 HEX thru FF HEX 10XX A2 A1 A0 Table 1 - Address bytes used by the SMM150. Slave Address programmed as 10XX A2 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Z Z Z Z Z Z Z Pins A[2:0] A1 0 0 0 1 1 1 Z 0 0 0 1 1 1 Z 0 0 0 1 1 1 Z A0 0 1 Z 0 1 Z X 0 1 Z 0 1 Z X 0 1 Z 0 1 Z X Slave Address 1000 1000 1000 1000 1000 1000 1000 1001 1001 1001 1001 1001 1001 1001 1010 1010 1010 1010 1010 1010 1010 Bus Address 000 001 010 100 101 110 011 000 001 010 100 101 110 011 000 001 010 100 101 110 011 Table 2 – Example device addresses allowed by the SMM150. Summit Microelectronics, Inc 2075 2.6 05/13/05 15 SMM150 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) Master S T A R T 1 0 S A 1 S A 0 Bus Address A 2 A 1 A 0 Configuration Register Address = 38HEX W A C K 0 0 1 1 1 0 0 0 A C K 0 1 0 Data = 55HEX 1 0 1 0 1 A C K 5HEX Unlocks General Purpose EE 5HEX Unlocks Configuration Registers S T O P Slave 3HEX Write Protection Register Address 8HEX Figure 10 – Write Protection Register Write S T A R T 1 Slave 0 S A 1 S A 0 S T O P D 2 D 1 D 0 A C K Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data D 4 D 3 Figure 11 – Configuration Register Byte Write S T A R T 1 Slave 0 S A 1 S A 0 Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K Master D 7 Slave D 6 D 5 Data (2) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (16) D 4 D 3 D 2 D 1 D 0 A C K S T O P Figure 12 – Configuration Register Page Write Summit Microelectronics, Inc 2075 2.6 05/13/05 16 SMM150 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) S T A R T 1 Slave 0 S A 1 S A 0 S T A R T C 1 C 0 A C K S A 3 S A 2 S A 1 S A 0 Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Configuration Register Address C 5 C 4 C 3 C 2 Bus Address A 2 A 1 A 0 W R A C K Master D 7 Slave D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (n) D 4 D 3 D 2 D 1 D 0 N A C K S T O P Figure 13 - Configuration Register Read S T A R T 1 Slave 0 S A 1 S A 0 S T O P D 2 D 1 D 0 A C K Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data D 4 D 3 Figure 14 – General Purpose Memory Byte Write S T A R T 1 Slave 0 S A 1 S A 0 Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K Master D 7 Slave D 6 D 5 Data (2) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (16) D 4 D 3 D 2 D 1 D 0 A C K S T O P Figure 15 - General Purpose Memory Page Write Summit Microelectronics, Inc 2075 2.6 05/13/05 17 SMM150 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) S T A R T 1 Slave 0 S A 1 S A 0 S T A R T C 1 C 0 A C K S A 3 S A 2 S A 1 S A 0 Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 Bus Address A 2 A 1 A 0 R A C K Master D 7 Slave D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (n) D 4 D 3 D 2 D 1 D 0 N A C K S T O P Figure 16 - General Purpose Memory Read S T A R T 1 Slave 0 S A 1 S A 0 S T O P D 2 D 1 D 0 A C K Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Command and Status Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data D 4 D 3 Figure 17 – Command and Status Register Write S T A R T 1 Slave 0 S A 1 S A 0 S T A R T C 1 C 0 A C K S A 3 S A 2 S A 1 S A 0 Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Command and Status Register Address W C 5 C 4 C 3 C 2 Bus Address A 2 A 1 A 0 R A C K Master D 7 Slave D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (n) D 4 D 3 D 2 D 1 D 0 N A C K S T O P Figure 18 - Command and Status Register Read Summit Microelectronics, Inc 2075 2.6 05/13/05 18 SMM150 Preliminary Information DEFAULT CONFIGURATION REGISTER SETTINGS – SMM150NC-356 Register R00 R01 R02 R03 R04 R05 RC1 Contents D5 71 9A 48 E0 28 Function Glitch filter delay time set to 120µs. Nominal setting is 1.802V. Margin high setting is 2.002V. Margin low setting is 1.602V. COMP1 is UV sensor, COMP2 is OV sensor, Fault output disabled when margining, Fault does not hold off or shutdown, Fault latched by Ready I/O Pin. Max converter Settling Time is 2.5ms, Margin I2C command enabled, MUP/MDN pins disabled, WP is active low. VREF set to 1.25V The default device ordering number is SMM150NC-356, is programmed as described above and tested over the commercial temperature range. See Application Note 46 for a complete description of the Configuration Register settings and corresponding Windows GUI control. Summit Microelectronics, Inc 2075 2.6 05/13/05 19 SMM150 Preliminary Information PACKAGE OUTLINES 28 Pad QFN Summit Microelectronics, Inc 2075 2.6 05/13/05 20 SMM150 Preliminary Information PACKAGE OUTLINES (CONTINUED) 20 Ball Ultra CSPTM Summit Microelectronics, Inc 2075 2.6 05/13/05 21 SMM150 Preliminary Information PART MARKING – QFN PACKAGE 28 Pad QFN Summit Part Number 20 Ball Ultra CSPTM SUMMIT SMM150N SS X is the sequential letter per wafer (i.e. A for the first wafer, B for the second wafer, C for the third wafer, etc.) Ball A1 Identifier Annn L AYYWW Pin 1 Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) SMM150EV XSSYWW Summit Part Number 100% Sn, RoHS compliant, Green Date Code Y = Single digit year (4=2004, 5=2005, etc) Date Code (YYWW) Lot tracking code (Summit use) 100% Sn, RoHS compliant, Green Drawing not to scale Part Number suffix (Contains Customer specific ordering requirements) Product Tracking Code (Summit use) Drawing not to scale ORDERING INFORMATION Summit SMM150 N V C nnn Part Number Package Temp Range C=Commercial N=28 Pad QFN E=20 Ball Ultra CSPTM Blank=Industrial V is the Lead-Free Attribute for the CSP (E Package), L is for the QFN (N package) Customer specific requirements are contained in the suffix such as Hex code, Hex code revision, etc. Part Number Suffix (see page 19) NOTICE NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 2.6 - This document supersedes all previous versions. Please check the Summit Microelectronics, Inc. web site at www.summitmicro.com for data sheet updates. © Copyright 2005 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE ANALOG FOR A DIGITAL WORLD™ TM I2C is a trademark of Philips Corporation, Ultra CSP is a registered name of FlipChip International, LLC. Summit Microelectronics, Inc 2075 2.6 05/13/05 22