SMM605FR04

SMM605 Six-Channel Supply Voltage Marginer and Active DC Output Controller (ADOCTM) FEATURES & APPLICATIONS • Extremely accurate (±0.1% Typ.) Active DC Output Control (ADOCTM) Preliminary Information1 (See Last Page) INTRODUCTION The SMM605 actively controls the output voltage level of up to six DC/DC converters that use a ‘Trim’ or ‘VADJ/FB’ pin to adjust the output. An Active DC Output Control (ADOCTM) feature is used during normal operation to maintain extremely accurate settings of supply voltages and, during system test, to control margining of the supplies using the industry standard I2C 2-wire data bus commands. Total accuracy with a ±0.1% external reference is ±0.2%, and ±0.5% using the internal reference. The device can margin supplies with either positive or negative trim pin control within a range of 0.35V to VDD. The SMM605 supply can range from 2.7V to 5.5V or 6V to 14V to accommodate any intermediate bus supply. The voltage settings (margin high/low and nominal) are programmed into nonvolatile memory. The I2C bus is used to enable margin high, margin low, ADOC or normal operation. When margining, the SMM605 will check the voltage output of the converter and make adjustments to the trim pin via a feedback loop to bring the voltage to the margin setting. A margining status register is set to indicate that the system is ready for test. • Six channel control of DC/DC converters • ADOC Automatically adjusts supply output voltage level under all DC load conditions • Capable of margining supplies with trim inputs using either positive or negative trim pin control • Wide Margin/ADOC range from 0.35V to VDD • Uses either an internal or external VREF • Operates from any intermediate bus supply from 8V to 15V and from 2.7V to 5.5V • Programmable START and READY pins • General Purpose 4k EEPROM with Write Protect • I2C 2-wire serial bus for programming configuration and monitoring status. • 48 lead TQFP package Applications • Monitor/Control Distributed and POL Supplies • Multi-voltage Processors, DSPs, ASICs used in Telecom, CompactPCI or server systems SIMPLIFIED APPLICATIONS DRAWING 12VIN (+6V to +14V Range) 3.3VIN (+2.7V to +5.5V Range) 12VIN VDD CAPA TRIM_CAPA DC/DC Converter C, E VIN DC/DC Converter A Vout TRIM 12V 3.3V SDA I2C BUS SCL A2 VDD_CAP 2.5VIN TRIMA 2 of 6 DC-DC Converters shown VMA CAPB SMM605 DC/DC Converter D, F VIN DC/DC Converter B Vout TRIM TRIM_CAPB µP/ ASIC 1.2VIN External or Internal REFERENCE VREF_CNTL TRIMB START READY RST MR VMB HEALTHY RESET READY POWER GOOD Figure 1 – Applications Schematic using the SMM605 Controller to actively control and margin the output levels of up to six DC/DC Converters. Note: This is an applications example only. Some pins, components and values are not shown. © SUMMIT Microelectronics, Inc. 2003 • 1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897 2064 1.1 9/16/03 www.summitmicro.com 1 SMM605 Preliminary Information Figure 2 – Example Power Supply Margining using the SMM605. The waveform on the left is margin low to high from 1.6V to 2.0V and the waveform on the right is margin high to nominal from 2.0V to 1.8V. The ADOC function guarantees the output level to be within ±0.2% maximum with a ±0.1% external reference. The bottom waveform is the READY signal indicating margin is complete. GENERAL DESCRIPTION The SMM605 is capable of controlling the DC output of up to six DC/DC Modules, switching regulators or LDOs that use a trim/adjust pin and automatically change the level using a unique Active DC Output Control (ADOCTM). The ADOC function is programmable over a standard 2-wire I2C serial data interface and can be used to set the nominal DC output voltage as well as the margin high and low settings. The part actively controls the programmed set levels to maintain tight control over load variations and voltage drops at the point of load. The margin range will vary depending on the supply manufacturer and model but the normal range is 10% adjustment around the nominal output setting. However, the SMM605 has the capability to margin from 0.35V to VDD. The user can set the desired voltage settings (nominal, margin high and margin low) into the EE memory array for the device. Then, volatile registers are used to select one of these settings. These registers are accessed over the I2C bus. In normal operation, Active DC Output Control is set to adjust the nominal output voltage of the converter. Typical converter accuracy ratings range from ±2% to ±5% of their output voltage. Using the Active DC Output Control feature of the SMM605 can increase the accuracy to ±0.1% (±0.2% Max.). This high accuracy control of the converter output voltage is extremely important in low voltage applications where deviations in power supply voltage can result in lower system performance. Active DC Output Control can also be used for margining a supply during system test or may be turned off by de-selecting the function in the Control Register. The margin high and margin low voltage settings can range from 0.35V to VDD around the converters’ nominal output voltage setting depending on the specified margin range of the DC-DC converter. When the SMM605 receives the command to margin, the Active DC Output Control will adjust the supply to the selected margin voltage. Once the supply has reached its margined set point, the Ready bit in the status register will set and the READY pin will go active. If Active DC Control is disabled, a margined supply can return to its nominal voltage by writing to the margin command register. In order to obtain maximum accuracy, the SMM605 requires an external voltage reference. An external reference with ±0.1% accuracy will enable an overall ±0.2% accuracy for the device. A configuration option also exists so that an internal voltage reference can be used, but with less accuracy. Total accuracy using the internal reference is ±0.5%. The SMM605 has additional filter pins to filter unwanted switching regulator noise. They are VDD_CAP and FILT_CAP. The SMM605 can be powered from either the 12VIN supply pin (6V to 14V range) via an internal regulator or the VDD supply pin (+2.7 to 5.5V range), see Figure 3. Programming of the SMM605 is performed over the industry standard I2C 2-wire serial data interface. A status register is available to read the state of the part and a Write Protect bit is available to prevent writing to the configuration registers and EE memory. Summit Microelectronics, Inc 2064 1.1 09/16/03 2 SMM605 Preliminary Information INTERNAL FUNCTIONAL BLOCK DIAGRAM 12VIN VDD VDD_CAP VREF_CNTL Level Shift Vout 3.6V or 5.5V Regulator V+ V- Power Supply Arbitrator Trim Drive Trim Drive Trim Drive TRIMA TRIM_CAPA O utput Control 1:6 MUX Trim Drive Trim Drive Trim Drive TRIMF TRIM_CAPF START READY A2 SDA SCL CONTROL LOGIC Input Voltage Sensing and Signal Conditioning 6:1 MUX VMA EE Memory FILT_CAP VMF Figure 3 –SMM605 Internal Functional Block Diagram. Summit Microelectronics, Inc 2064 1.1 09/16/03 3 SMM605 Preliminary Information PIN DESCRIPTIONS Pin Number1 Pin Type Pin Name VMA VMB VMC IN VMD VME VMF TRIMA TRIMB TRIMC OUT TRIMD TRIME TRIMF TRIM_CAPA TRIM_CAPB TRIM_CAPC I/O TRIM_CAPD TRIM_CAPE TRIM_CAPF IN PWR 47 46 5,6,12,13 PWR GND VDD GND VDD_CAP 12VIN External capacitor input used to filter the internal supply rail. 12V power supply input internally regulated to 3.6 or 5.5V. Input range is 6V to 14V using the 3.6V internal regulator setting and 10V to 14V using the 5.5V internal regulator setting. 2.7V to 5.5V Power supply of the part. Ground of the part. External sample and hold capacitor input used to set the voltage on the TRIM pins. Output voltage used to margin and/or trim converter voltages. Connect to the converter Trim input or to the VADJ or FB pin of an adjustable output switching regulator or LDO through a resistor. Pin Description 41 36 31 26 21 16 44 39 34 29 24 19 45 40 35 30 25 20 48 Voltage monitor pin. Connect to the DC-DC converter + sense line or +Vout pin. Summit Microelectronics, Inc 2064 1.1 09/16/03 4 SMM605 Preliminary Information PIN DESCRIPTIONS (Cont.) Pin Number 15 14 1 2 3 Pin Type IN IN I/O IN IN Pin Name FILT_CAP VREF_CNTL SDA SCL A2 Pin Description External capacitor input used to filter VMX inputs. . This provides an RC filter where R = 1kΩ. Voltage reference input used for DC output control and margining. Bi-directional I2C data line. I2C clock line. The address pin is biased either to VDD_CAP or GND. When communicating with the SMM605 over the 2-wire bus A2 provides a mechanism for assigning a unique bus address. Programmable active high/low input. The START input is used solely for enabling Active Control and/or margining. Programmable active high/low open drain output signals indicating when all programmed power supplies have reached their preprogrammed setpoints. Leave the NC pins floating. 4 7 IN OUT NC START READY No Connect PACKAGE AND PIN CONFIGURATION 48 LEAD TQFP TRIM_CAPA TRIM_CAPB VDD_CAP TRIMB TRIMA 12VIN VDD VMA NC 38 48 47 46 45 44 43 NC 42 NC 41 40 39 SDA SCL A2 START GND GND READY NC NC NC NC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 37 36 35 34 33 32 31 30 29 28 27 26 25 NC VMB TRIM_CAPC TRIMC NC NC VMC TRIM_CAPD TRIMD NC NC VMD TRIM_CAPE VREF_CNTL TRIM_CAPF FILT_CAP TRIMF Summit Microelectronics, Inc 2064 1.1 09/16/03 TRIME GND VMF VME NC NC NC NC 5 SMM605 Preliminary Information ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ...................... -55°C to 125°C Storage Temperature............................ -65°C to 150°C Terminal Voltage with Respect to GND: VDD Supply Voltage ..........................-0.3V to 6.0V 12VIN Supply Voltage......................-0.3V to 15.0V All Others ................................-0.3V to VDD + 0.7V Output Short Circuit Current ............................... 100mA Lead Solder Temperature (10 secs)……………….300°C Junction Temperature.......................…….....…...150°C ESD Rating per JEDEC……………………..…..2000V Latch-Up testing per JEDEC………..……....…±100mA Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. RECOMMENDED OPERATING CONDITIONS Temperature Range (Industrial)...........–40°C to +85°C (Commercial) ............–5°C to +70°C VDD Supply Voltage .................................. 2.7V to 5.5V 12VIN Supply Voltage (1) ........................ 6.0V to 14.0V VIN ............................................................ GND to VDD VOUT ...................................................... GND to 15.0V Package Thermal Resistance (θJA) 48 Lead TQFP……………………………….…80oC/W Moisture Classification Level 1 (MSL 1) per J-STD- 020 Note 1 – Range depends on internal regulator set to 3.6V or 5.5V, see 12VIN specification below. DC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Parameter Notes Min Typ Max Symbol 2.7 5.5 VDD Supply Voltage 12VIN IDD I12VIN Supply Voltage Power Supply Current from VDD Power Supply Current from 12VIN Internally regulated to 5.5V Internally regulated to 3.6V Unit V V V mA mA 10 6 3 3 14 14 5 5 All TRIM pins floating, 12VIN floating All TRIM pins floating, VDD floating TRIM Sourcing Maximum Current TRIM Sinking Maximum Current Depends on Trim range of DC-DC Converter VDD = 2.7V VDD = 5.0V VDD = 2.7V VDD = 5.0V ISINK = 1mA Note – Total ISINK from all PUPx pins should not exceed 3mA or ADOCACC specification will be affected TRIM characteristics ITRIM TRIM output current through 100Ω to 1.0V Margin Control and ADOC Range Input High Voltage (FS, PWR_ON/OFF, MR#, SDA, SCL) Input Low Voltage (FS, PWR_ON/OFF, MR#, SDA, SCL) Programmable Open Drain Outputs (RST, HEALTHY, FAULT, PUPx) Output Low Current 1.5 1.5 VREF_CNTL/ 4 mA mA VDD VDD VDD 0.1xVDD 0.3xVDD 0.4 1.0 V V V V V V mA 6 VTRIM All other input and output characteristics VIH VIL VOL IOL 0.9xVDD 0.7xVDD -0.1 -0.1 0 0 Summit Microelectronics, Inc 2064 1.1 09/16/03 SMM605 Preliminary Information DC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ. Max VSENSE VMonitor VREF VREF TC VREF ACC External VREF ADOCACC Positive Sense Voltage Monitor Threshold Step Size Internal 1.25VREF Output Voltage Internal VREF Temperature Coefficient Internal VREF Accuracy External VREF Voltage Range ADOC/Margin Accuracy External VREF=1.25V, ±0.1%, Internal VREF=1.25V –40°C to +85°C –5°C to +70°C VM pins VM pins 1.24 -0.25 -0.15 -0.4 0.5 -0.2 -0.5 +0.35 5 1.25 1.26 +0.25 +0.15 +0.4 VDD_CAP VDD_CAP Unit V mV V % % % V % % ±0.1 ±0.3 +0.2 +0.5 AC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) See Figure 3, 4 and 5 Timing diagrams. Symbol tDC_CONTROL Tsettling TMARGIN Description Active DC Control sampling period Settling Time Margin Time from Nominal to ±5% Conditions Update period for Active DC Control of channels A–F + 10% change in voltage with 0.1% ripple Slow Margin, TRIM_CAP=1µF Fast Margin, TRIM_CAP=1µF Min Typ 1.7 100 100 1 Max Unit ms ms ms ms Summit Microelectronics, Inc 2064 1.1 09/16/03 7 SMM605 Preliminary Information I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100/400kHz Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 4 Timing Diagram. Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR Description SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock Edge to Data Valid Data Output Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Filter SCL and SDA Write Cycle Time Conditions Min 0 4.7 4.0 Before New Transmission - Note 1/ 100kHz Typ Max 100 Min 0 1.3 0.6 1.3 0.6 0.6 0.6 3.5 0.2 0.2 1000 300 250 0 150 0 100 5 400kHz Typ Max 400 Units KHz µs µs µs µs µs µs 0.9 µs µs 1000 300 ns ns ns ns 100 5 ns ms 4.7 4.7 4.0 4.7 SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change Note 1/ Note 1/ 0.2 0.2 Noise suppression Note: 1/ - Guaranteed by Design. TIMING DIAGRAMS tR SCL tSU:SDA SDA ( IN) tF t HD:SDA tHIGH t W R (For W rite O peration Only) t LOW tSU:DAT tSU:STO tBUF tHD:DAT tAA SDA ( OUT) t DH Figure 4 - Basic I2C Serial Interface Timing Summit Microelectronics, Inc 2064 1.1 09/16/03 8 SMM605 Preliminary Information APPLICATIONS INFORMATION DEVICE OPERATION POWER SUPPLY The SMM605 can be powered by either an 6V to 14V input through the 12VIN pin or by a 2.7V to 5.5V input through the VDD pin (Figure 5). The 12VIN pin feeds an internal programmable regulator that internally generates either 5.5V or 3.6V. The internal regulator must be set to 3.6V if using an 8V supply. A voltage arbitration circuit allows the device to be powered by the highest voltage from either the regulator output or the VDD input. This voltage arbitration circuit continuously checks for these voltages to determine which will power the SMM605. The resultant internal power supply rail is connected to the VDD_CAP pin that allows both filtering and hold-up of the internal power supply. VOLTAGE REFERENCE The SMM605 can operate using either an internal or external voltage reference, VREF. The internal VREF is set to 1.25V. Total accuracy with a ±0.1% external reference is ±0.2% and ±0.5% using the internal reference. MODES OF OPERATION The SMM605 has two basic modes of operation: supply margining mode and Active DC Output Control (ADOCTM). A detailed description of each mode and feature follows. ACTIVE DC OUTPUT CONTROL (ADOC) The SMM605 can actively control the DC output voltage of bricks or DC/DC converters that have a trim pin during monitoring and margining mode. The converter may be an off-the shelf compact device, or may be a “roll your own” circuit on the application board. In either case, the SMM605 dramatically improves voltage accuracy (down to ±0.2%) by implementing closed-loop ADOC active control. This utilizes the DC-DC’s “trim” pin as shown in Figure 7, or an equivalent output voltage feedback adjustment “VADJ” or “FB” node in a user’s custom circuit, Figure 8. Each of the TRIMX pins on the SMM605 is connected to the trim input pins on the power supply converters. A sense line from the channel’s point-of-load connects to the corresponding VMX input. The ADOC function cycles through all six channels (A-F) every 1.7ms making slight adjustments to the voltage on the associated TRIMX output pins based on the voltage inputs on the VMX pins. These voltage adjustments allow the SMM605 to control the output voltage of power supply converters to within ±0.2% when using a ±0.1% external voltage reference. The voltage on the TRIM_CAPX pins is buffered and applied to the TRIMX pin. The voltage adjustments on the TRIMX pins cause a slight ripple of less than 1mV on the power supply voltage. The amplitude of this ripple is a function of the TRIM_CAPX capacitor and the trim gain of the converter. Calculation of the TRIM_CAPX capacitor to achieve a desired minimum ripple is detailed in Application Note 37. The pulse of current can be increased to a 10X pulse of current until the power supply voltages are at their nominal settings by selecting the programmable Fast Convergence option. As the name implies, this option decreases the time required to bring a supply voltage from the converter’s nominal output voltage to the Active DC Output Control nominal voltage setting. The device can be programmed to either enable or disable the Active DC Control function. When disabled or not active, the TRIMX pins on the SMM605 are high impedance inputs. The voltage on the TRIMX pins are buffered and applied to the TRIM_CAPX pins charging the capacitor. This allows a smooth transition from the converter’s nominal voltage to the SMM605 controlling that voltage to the Active DC Control nominal setting. MONITORING The SMM605 monitors the VMX pins. The READY pin is programmable active high/low open drain output indicates that all VMX pins are at their set point. Summit Microelectronics, Inc 2064 1.1 09/16/03 9 SMM605 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) MARGINING The SMM605 has two additional Active DC Output Control voltage settings: margin high and margin low. The margin high and margin low settings can be as much as ±10% of the nominal setting depending on the manufacturer. The SMM605 range can be as large as 0.35V to VDD. These settings are stored in the configuration registers and are loaded into the Active DC Output Control voltage setting by margin commands issued via the I2C bus. The device must be enabled for Active DC Output Control in order to enable margining. The margin command registers contain two bits that decode the commands to margin high, margin low, or control to the nominal setting. Once the SMM605 receives the command to margin the supply voltage, it begins adjusting the supply voltage to move toward the desired setting. When this voltage setting is reached, a bit is set in the margin status registers and the READY signal becomes active. (Figure 2, 5 and 6) Note: Configuration writes or reads of registers 00HEX to 03HEX should not be performed while the SMM605 is margining. WRITE PROTECTION Write protection for the SMM605 is located in a volatile register where the power-on state is defaulted to write protect. There are separate write protect modes for the configuration registers and memory. In order to remove write protection, the code 55HEX is written to the write protection register. Other codes will enable write protection. For example, writing 59HEX will allow writes to the configuration register but not to the memory, while writing 35HEX will allow writes to the memory but not to the configuration registers. In addition, there is a configuration register lock bit which, once programmed, does not allow the configuration registers to be changed. Figure 5 - Margin High Waveforms Time/Horizontal division = 200mS Ch 1 (1V/Div) = 3.3V DC-DC converter output (Yellow trace) Ch 2 (500mV/Div) = 2.5VDC-DC converter output (Blue trace) Ch 3 (500mV/Div) = 1.8V DC-DC converter output (Purple trace) Ch 4 (500mV/Div) = 1.5V DC-DC converter output (Green trace) Figure 6 - Margin Low Waveforms Time/Horizontal division = 400mS Ch 1 (1V/Div) = 3.3V DC-DC converter output (Yellow trace) Ch 2 (500mV/Div) = 2.5V DC-DC converter output (Blue trace) Ch 3 (500mV/Div) = 1.8V DC-DC converter output (Purple trace) Ch 4 (500mV/Div) = 1.5V DC-DC converter output (Green trace) Summit Microelectronics, Inc 2064 1.1 09/16/03 10 SMM605 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) VDD (+2.7V to +5.5V) +12VIN (+6V to +14V) The SMM605 and the DC-DC Converter Can Operate with either 12V or VDD If 12V is used, VDD can be left floating If VDD is used, 12V can be left floating C8 0.1uF Supply J2 If the SMM605 internal VREF is used, the VREF_CNTL pin becomes an output J1 U4 5 LM4121 VOut Gnd Ref VIn EN Vdd 4 3 C3 0.01uF C2 0.1uF C4 0.1uF C7 0.01uF R4 10K R3 10K R2 10K R1 10K START READY 4 7 START READY U1 46 48 47 14 Ext VRef 1 C6 0.1uF VDD VDD_CAP 12VIN VREF_CNTL C6 1uF TRIM_CAPX TRIMX VMX 2 VOUT U2 7 8 11 9 C5 0.02uF +Vin +Vin Enable +Vin Gnd Gnd DC-DC Converter +Vout +Vout +Vout Sense Trim 1 2 4 3 10 D1 DIODE 2 1 SCL SDA A2 GND GND GND GND SMM605 FILT_CAP 15 0.1uF C1 1 3 5 7 9 Gnd SCL Gnd3 SDA Rsrv5 MR +10V Rsrv8 +5V Rsrv10 2 4 6 8 10 J1 5 6 12 13 SMX3200 I2C Programming Connector 10 pin Header 3 DC-DC ENABLE Figure 7 – SMM605 Applications schematic. The accuracy of the external (U4) or internal reference sets the accuracy of the ADOC function. Total accuracy with a ±0.1% external reference is ±0.2% and ±0.5% with the internal reference. The 12V supply can go as low as 6V if the internal regulator is set to 3.6V. Summit Microelectronics, Inc 2064 1.1 09/16/03 5 6 11 SMM605 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) +12VIN(+6V to 14V) C3 0.1uF VTRIMlow=0.3V, VOSENSE=0.8V The current through R3 is ITRIM=(0.8-0.3)/RTRIM (ITRIM)(R4) > 15% of VOUT RTRIMmax should be no greater then the calculated value C4 0.1uF C5 0.01uF R5 10K 46 48 47 14 R4 10K U1 START READY 4 7 START READY For Example, If Vout=3.3V, R4=63.4K 15% of Vout=0.5V C1 should be as close ITRIM=8uA to the SMM105 as RTRIM=62.5K so Rtrim should be possible next value down from 62.5K C1 1uF TRIM_CAPX TRIMX VMX R3 RTRIM LT3707 Switching Regulator +Vin +Vout VDD VDD_CAP 12VIN VREF_CNTL VOUT R4 RSET1 R2 10K R1 10K 2 1 3 SCL SDA A2 SMM605 FILT_CAP 15 GND GND GND GND Gnd D1 DIODE C6 0.01uF 1 3 5 7 9 J1 2 4 6 8 10 PGOOD C2 0.02uF U2 START VOSENSE R5 20k The SMM605 START pin must be inactive during power-up so SMX3200 I2C Programming that the TRIM pin is high impedence. Once power is nominal, the START pin can be active to start margin and ADOC Connector 10 pin Header functions R1 and R2 need only be placed once on the I2C bus Figure 8 – SMM605 Applications schematic for an adjustable switching regulator (Full regulator circuit not shown). Gnd SCL Gnd3 SDA Rsrv5 MR +10V Rsrv8 +5V Rsrv10 Summit Microelectronics, Inc 5 6 12 13 2064 1.1 09/16/03 12 SMM605 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) Figure 9 – SMM605 Applications schematic. Summit Microelectronics, Inc 2064 1.1 09/16/03 13 SMM605 Preliminary Information DEVELOPMENT HARDWARE & SOFTWARE The end user can obtain the Summit SMX3200 programming system for device prototype development. The SMX3200 system consists of a programming Dongle, cable and WindowsTM GUI software. It can be ordered on the website or from a local representative. The latest revisions of all software and an application brief describing the SMX3200 is available from the website (www.summitmicro.com). The SMX3200 programming Dongle/cable directly between a PC’s parallel port and application. The device is then configured via an intuitive graphical user interface drop-down menus. interfaces the target on-screen employing The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMM605 via the programming Dongle and cable. An example of the connection interface is shown in Figure 10. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. D1 Positive Supply VDD_CAP 1N4148 Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector. Pin 10, Reserved Pin 8, Reserved Pin 6, MR# Pin 4, SDA Pin 2, SCL Pin 9, 5V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND SMM605 SDA SCL 10 8 6 4 2 9 7 5 3 1 0.1 F GND Common Ground Figure 10– SMX3200 Programmer I2C serial bus connections to program the SMM605. The SMM605 has a Write Protect pin (WP# input) which when, asserted, prevents writing to the configuration registers and EE memory. In addition, there is a configuration register lock bit which, once programmed, does not allow the configuration registers to be changed. Summit Microelectronics, Inc 2064 1.1 09/16/03 14 SMM605 Preliminary Information I2C PROGRAMMING INFORMATION SERIAL INTERFACE Access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standard 2-wire serial interface (I2C). SDA is a bi-directional data line and SCL is a clock input. Data is clocked in on the rising edge of SCL and clocked out on the falling edge of SCL. All data transfers begin with the MSB. During data transfers SDA must remain stable while SCL is high. Data is transferred in 8-bit packets with an intervening clock period in which an Acknowledge is provided by the device receiving data. The SCL high period (tHIGH) is used for generating Start and Stop conditions that precede and end most transactions on the serial bus. A high-to-low transition of SDA while SCL is high is considered a Start condition while a low-to-high transition of SDA while SCL is high is considered a Stop condition. The interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. The address byte is comprised of a 4-bit device type identifier (slave address) and a 3-bit bus address. The remaining bit indicates either a read or a write operation. Refer to Table 1 for a description of the address bytes used by the SMM605. The device type identifier for the memory array is generally set to 1010BIN following the industry standard for a typical nonvolatile memory. There is an option to change the identifier to 1011BIN allowing it to be used on a bus that may be occupied by other memory devices. The configuration registers are grouped with the memory array and thus use 1010BIN or 1011BIN as the device type identifier. The command and status registers are accessible with the separate device type identifier of 1001BIN. The bus address bits A[1:0] are programmed into the configuration registers. Bus address bit A[2] can be programmed as either 0 or biased by the A2 pin. The bus address accessed in the address byte of the serial data stream must match the setting in the SMM605 and on the A2 pin. Any access to the SMM605 on the I2C bus will temporarily halt the monitoring function. The SMM605 halts the monitor function from when it acknowledges the address byte until a valid stop is received. WRITE Writing to the memory or a configuration register is illustrated in Figures 11, 12, 13, 17 and 18. A Start condition followed by the address byte is provided by the host; the SMM605 responds with an Acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMM605 responds with an acknowledge; the host then clocks in on byte of data. For memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. After the last byte is clocked in and the host receives an Acknowledge, a Stop condition must be issued to initiate the nonvolatile write operation. READ The address pointer for the configuration registers, memory, command and status registers must be set before data can be read from the SMM605. This is accomplished by issuing a dummy write command, which is simply a write command that is not followed by a Stop condition. The dummy write command sets the address from which data is read. After the dummy write command is issued, a Start command followed by the address byte is sent from the host. The host then waits for an Acknowledge and then begins clocking data out of the slave device. The first byte read is data from the address pointer set during the dummy write command. Additional bytes can be clocked out of consecutive addresses with the host providing an Acknowledge after each byte. After the data is read from the desired registers, the read operation is terminated by the host holding SDA high during the Acknowledge clock cycle and then issuing a Stop condition. Refer to Figures 14, 16, 19 and 21 for an illustration of the read sequence. Summit Microelectronics, Inc 2064 1.1 09/16/03 15 SMM605 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) WRITE PROTECTION The SMM605 powers up into a write protected mode. Writing a code to the volatile write protection register can disable the write protection. The write protection register is located at address 87HEX of slave address 1001BIN. Writing 0101BIN to bits [7:4] of the write protection register allow writes to the general-purpose memory while writing 0101BIN to bits [3:0] allow writes to the configuration registers. The write protection can reenable by writing other codes (not 0101BIN) to the write protection register. Writing to the write protection register is shown in Figure 11. CONFIGURATION REGISTERS The majority of the configuration registers are grouped with the general-purpose memory located at either slave address 1010BIN or 1011BIN. The bus address bits, A[1:0], used to differentiate the general-purpose memory from the configuration registers are set to 11BIN. Bus address bit A[2] can be programmed as either 0 or biased by the A2 pin. Two additional configuration registers are located at addresses 83HEX and 84HEX of slave address 1001BIN. Writing and reading the configuration registers is shown in Figures 14 and 16. Note: Configuration writes or reads of registers 00HEX to 0FHEX should not be performed while the SMM605 is margining. GENERAL-PURPOSE MEMORY The 4k-bit general-purpose memory is located at either slave address 1010BIN or 1011BIN. The bus address bits, A[1:0], used to differentiate the generalpurpose memory from the configuration registers are set to 00BIN for the first 2k-bits and 01BIN for the second 2k-bits. Bus address bit A[2] can be programmed as either 0 or biased by the A2 pin. The word address must be set each time the memory is accessed. Memory writes and reads are shown in Figures 17, 18 and 19. COMMAND AND STATUS REGISTERS The command and status registers are located at slave address 1001BIN. Writes and reads of the command and status registers are shown in Figures 20 and 21. GRAPHICAL USER INTERFACE (GUI) Device configuration utilizing the Windows based SMM605 graphical user interface (GUI) is highly recommended. The software is available from the Summit website (www.summitmicro.com). Using the GUI in conjunction with this datasheet and application note 40 simplifies the process of device prototyping and the interaction of the various functional blocks. A programming Dongle (SMX3200) is available from Summit to communicate with the SMM605. The Dongle connects directly to the parallel port of a PC and programs the device through a cable using the I2C bus protocol. Slave Address 1001BIN Bus Address A2 A1 A0 Register Type Write Protection Register, Command and Status Registers, Two Configuration Registers 1st 2-k Bits of General-Purpose Memory 2nd 2-k Bits of General-Purpose Memory Configuration Registers 1010BIN or 1011BIN A2 0 0 A2 0 1 A2 1 1 Table 1 - Address bytes used by the SMM605. Summit Microelectronics, Inc 2064 1.1 09/16/03 16 SMM605 Preliminary Information S T A R T 1 Slave 0 0 1 S T O P 1 0 1 A C K 5 HEX U nlocks General Purpose EE 5 HEX U nlocks Configuration Registers M aster Bus Address A 2 A 1 A 0 Configuration Register Address = 87 HEX Data = 55 HEX W A C K 1 0 0 0 0 1 1 1 A C K 0 1 0 1 0 8 H EX W rite Protection Register Address 7 HEX Figure 11 – Write Protection Register Write S T A R T 1 Slave 0 1 S A 0 S T O P D 2 D 1 D 0 A C K Master Bus Address A 2 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data D 4 D 3 1 1 Figure 12 – Configuration Register Byte Write S T A R T 1 Slave 0 1 S A 0 Master Bus Address A 2 C 7 A C K C 6 Configuration Register Address C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K 1 1 W Master D 7 Slave D 6 D 5 Data (2) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (16) D 4 D 3 D 2 D 1 D 0 A C K S T O P Figure 13 – Configuration Register Page Write Summit Microelectronics, Inc 2064 1.1 09/16/03 17 SMM605 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) S T A R T 1 Slave 0 1 S A 0 S T A R T C 1 C 0 A C K 1 0 1 S A 0 Master Bus Address A 2 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 Bus Address A 2 1 1 1 1 R A C K Master D 7 Slave D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (n) D 4 D 3 D 2 D 1 D 0 N A C K S T O P Figure 14 - Configuration Register Read S T A R T 1 Slave 0 0 1 Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data D 4 D 3 D 2 D 1 D 0 A C K S T O P Figure 15 - Configuration Register with Slave Address 1001BIN Write S T A R T 1 Slave 0 0 1 S T A R T C 1 C 0 A C K 1 0 0 1 Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 Bus Address A 2 A 1 A 0 R A C K Master D 7 Slave D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (n) D 4 D 3 D 2 D 1 D 0 N A C K S T O P Figure 16 - Configuration Register with Slave Address 1001BIN Read Summit Microelectronics, Inc 2064 1.1 09/16/03 18 SMM605 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) S T A R T 1 Slave 0 1 S A 0 S T O P D 2 D 1 D 0 A C K Master Bus Address A 2 0 / 1 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data D 4 D 3 0 Figure 17 – General Purpose Memory Byte Write S T A R T 1 Slave 0 1 S A 0 Master Bus Address A 2 0 / 1 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K 0 Master D 7 Slave D 6 D 5 Data (2) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (16) D 4 D 3 D 2 D 1 D 0 A C K S T O P Figure 18 - General Purpose Memory Page Write S T A R T 1 Slave 0 1 S A 0 S T A R T C 1 C 0 A C K 1 0 1 S A 0 Master Bus Address A 2 0 / 1 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 Bus Address A 2 0 / 1 0 0 R A C K Master D 7 Slave D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (n) D 4 D 3 D 2 D 1 D 0 N A C K S T O P Figure 19 - General Purpose Memory Read Summit Microelectronics, Inc 2064 1.1 09/16/03 19 SMM605 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) S T A R T 1 Slave 0 0 1 S T O P D 2 D 1 D 0 A C K Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Command and Status Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data D 4 D 3 Figure 20 – Command and Status Register Write S T A R T 1 Slave 0 0 1 S T A R T C 1 C 0 A C K 1 0 0 1 Master Bus Address A 2 A 1 A 0 C 7 A C K C 6 Command and Status Register Address W C 5 C 4 C 3 C 2 Bus Address A 2 A 1 A 0 R A C K Master D 7 Slave D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (n) D 4 D 3 D 2 D 1 D 0 N A C K S T O P Figure 21 - Command and Status Register Read Summit Microelectronics, Inc 2064 1.1 09/16/03 20 SMM605 Preliminary Information DEFAULT CONFIGURATION REGISTER SETTINGS – SMM605F-186 Register R00 R01 R02 R03 R04 R05 R06 R07 R08 R09 R0A R0B R0C R0D R0E R0F RC1 Contents 0D 84 0E 00 0E 80 0E C7 0F 55 0B 27 3F 3F 04 01 Register R18 R19 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R3A R3B R3C R3D R3E Contents 34 00 0D 64 0D DA 0E 46 0E A2 0F 20 0F D9 00 12 12 Register R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R4A R4B R83 R84 R86 R87 Contents 0D AB 0E 2D 0E C7 0E F1 0F 92 0B 70 05 00 12 F6 The default device ordering number is SMM605N-186, is programmed as described above and tested over the commercial temperature range. Application Note 40 contains a complete description of the Windows GUI and the default settings of each of the 48 individual Configuration Registers. Summit Microelectronics, Inc 2064 1.1 09/16/03 21 SMM605 Preliminary Information PACKAGE 48 PIN TQ FP PACKAGE 0.354 (9.00) 0.276 (7.00) BSC (A) BSC (B) Inches (Millimeters) 0.02 (0.5) BSC 0.007 - 0.011 (0.17 - 0.27) DETAIL "A" (B) (A) Ref Jedec M S-026 0.037 - 0.041 0.95 - 1.05 Pin 1 Indicator 0.039 (1.00) Ref 0.047 MAX. (1.2) 0 o M in to 7 o M ax A B 0.002 - 0.006 (0.05-0.15) 0.018 - 0.030 (0.45 - 0.75) DETAIL "B" Summit Microelectronics, Inc 2064 1.1 09/16/03 22 SMM605 Preliminary Information PART MARKING SUMMIT SMM605F Annn Pin 1 Summit Part Number xx Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) AYYWW Date Code (YYWW) Lot tracking code (Summit use) Part Number suffix (Contains Customer specific ordering requirements) Drawing not to scale Product Tracking Code (Summit use) ORDERING INFORMATION SMM605 Summit Part Number F nnn Part Number Suffix (see page 23) Specific requirements are contained in the suffix such as Commercial or Industrial Temp Range, Hex code, Hex code revision, etc. Package F=48 Lead TQFP NOTICE NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 1.1 - This document supersedes all previous versions. Please check the Summit Microelectronics Inc. web site at www.summitmicro.com for data sheet updates. © Copyright 2003 SUMMIT MICROELECTRONICS, Inc. ADOC TM Power Management for Communications™ is a trademark of Summit Microelectronics, Inc., I2C is a trademark of Philips Corporation. Summit Microelectronics, Inc 2064 1.1 09/16/03 23