SMS1242

SUMMIT MICROELECTRONICS , I nc. SMS1242 2.5V, 3V, 3.3V & 5V Dual Voltage, Dual Reset Microprocessor Supervisory Circuits FEATURES • Supply voltage monitor - Nominal VRST of 2.45V, 2.65V, 2.95V, 4.45V, 4.55V or 4.65V - RESET# Outputs Guaranteed true at VCC = 1V - 150ms Reset Delay Time • Second voltage monitor - VSENSE Input - 1.25V threshold ±1% • Manual Reset Input • Includes 16k-bits nonvolatile memory - Industry standard 2-wire serial interface OVERVIEW The SMS1242 microprocessor supervisory circuit reduces the complexity and number of components required to monitor the supply voltage in +5V, +3V and +2.5V systems. The SMS1242 will significantly improve system reliability and accuracy when compared to implementing the same functions with discrete components. The SMS1242 provides reset output during power-up, power-down, and brown-out conditions. It has a 1.25V threshold input detector for power-fail warning, low battery detection, or monitoring a secondary power supply. The part also integrates a separate active low manual reset input. It also has 16k-bits of nonvolatile memory accessible over an industry standard 2-wire serial interface. FUNCTIONAL BLOCK DIAGRAM VCC 8 SCL SDA 6 5 NONVOLATILE MEMORY ARRAY VSENSE 3 + – 7 MR# 2 RESET1# + – VTRIP RESET GENERATOR 1 RESET2# 1.25V 4 GND 2038 BD 2.0 © SUMMIT MICROELECTRONICS, Inc. 2000 • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com 2038 2.0 6/8/00 Characteristics subject to change without notice 1 SMS1242 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias –55°C to 125°C Storage Temperature –65°C to 150°C Terminal Voltage (With Respect to Ground)–0.3V to 6V Lead Solder Temperature (10 secs) 300°C *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operation sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Symbol VCC ICC Parameter Operating supply voltage Conditions Min. 1 Typ. Max. 5.5 Units V µA µA mA V V V V V V mV 3.6V < VCC < 5.5V Supply current 3.6V > VCC Memory access (SMS1243 only) Device option A Device option B VRST Reset threshold Device option C Device option D Device option E Device option F VHYST tRST VOL IMR tMR VIL VIH VSNS VCC VRST Hysterisis Reset pulse width RESET1# output low voltage MR# pullup current MR# pulse width MR# input threshold MR# input threshold VSENSE input threshold RESET2# output low voltage VCC = VRST min., VSENSE falling ISINK = 1.2mA, VCC = VRST min. ISINK = 200µA, VCC = 1.2V 0.7 × VCC 1.20 50 ISINK = 1.2mA, VCC = VRST min. ISINK = 200µA, VCC = 1.2V 100 4.375 4.625 4.425 2.425 2.625 2.925 25 25 50 50 3 4.425 4.675 4.475 2.450 2.650 2.950 50 150 4.475 4.725 4.525 2.475 2.675 2.975 200 0.3 0.3 ms V V µA ns 100 0.6 V V 1.25 1.30 0.3 0.4 V V V 2038 Elect Table 2.0 SUMMIT MICROELECTRONICS, Inc. 2038 2.0 6/8/00 2 SMS1242 PIN NAMES Pin Signal Function PIN CONFIGURATION 8-Pin SOIC 1 Active low output with weak pullup. Driven low by: VSENSE below threshold; or VCC below threshold while RESET1# MR# is below threshold. Remains low for 150ms after VSENSE, or VCC and MR#, is above threshold. RESET2# VSENSE GND Same as Reset1#, except open drain connection Threshold detector input for the Resets Ground RESET1# RESET2# VSENSE GND 1 2 3 4 8 7 6 5 VCC MR# SCL SDA 2 3 4 5 6 7 8 2038 T PCon 2.0 SDA/GND SMS1243 Data I/O, or ground SCL/GND SMS1243 Data Clock, or ground MR# VCC Manual input for Resets Supply voltage 2038 Pin Table 2.0 VCC VRST VRST tRST RESET# MR# VIL tMR VIH tRST tRST VSENSE Figure 1. Reset Waveforms VSNS 2038 T Fig01 2.0 2038 2.0 6/8/00 SUMMIT MICROELECTRONICS, Inc. 3 SMS1242 4.5 4.4 GLITCH AMPLITUDE (V) 4.3 4.2 4.1 4.0 3.9 3.8 0 1 2 3 4 5 6 7 8 9 10 2038 Fig02 2.0 PULSE WIDTH (ms) Figure 2. Supply Voltage Noise Rejection, VRST =4.55V, TA = 25ºC VRST V CC 2V 1.25V 0V V SE NS E 0V VCC 0V RESET# 0V RESET# 500ms/Div. Figure 3. RESET Output vs. Supply Figure 4. RESET Output vs. VSENSE SUMMIT MICROELECTRONICS, Inc. 2038 2.0 6/8/00 4 SMS1242 DEVICE OPERATION The SMS1242 provides a precision reset function for a microcontroller or microprocessor during power-up, power-down and brown-out conditions. The device will monitor two independent voltage supplies and will generate a reset condition when either supply is invalid. It is configured with two outputs, both driven by the same conditions. They are open drain and will track each other but the outputs are not internally tied together. Because RESET1# and RESET2# are essentially open drain outputs (RESET1# has a weak internal pullup, RESET2# does not) they can be independently driven low by external signals. This can be very useful in a dual processor system or in a combined processor/ASIC system where, either for system operation or system test, the processors or ASICs must be independently held in reset without resetting the other portion of the system. SUPPLY MONITOR (Assume VSENSE > VSNS) During power-up the SMS1242 monitors the supply voltage. The RESET1# and RESET2# outputs are guaranteed to be driven low once VCC reaches 1V. As VCC rises RESET1# and RESET2# remain asserted until VCC reaches the VRST threshold. As VCC passes through VRST an internal timer is started to continue driving the outputs for an additional 150ms (nominal). If a power-fail or brown-out condition occurs (VCC < VRST) RESET1# and RESET2# will be asserted. They will remain active so long as VCC is below VRST. Because the internal timer will be continuously reset so long as VCC is below VRST, a brownout condition that interrupts a previously initiated reset pulse causes an additional reset delay from the time the VCC passes back through VRST. During power down conditions, once VCC drops below VRST, RESET1# and RESET2# are guaranteed to be asserted for VCC ≥ 1V. VSENSE MONITOR (Assume VCC is >VRST) The SMS1242 continuously monitors the VSENSE input. The RESET1# and RESET2# outputs will be driven low so long as VSENSE is < VSNS. As VSENSE passes through VSNS an internal timer is started to continue driving the outputs for an additional 150ms (nom.). If a power-fail condition occurs (VSENSE falls below VSNS) RESET1# and RESET2# will be asserted. They will remain active so long as VSENSE is below VSNS. Because the internal timer will be continuously reset so long as VSENSE is below VSNS, a brownout condition that interrupts a previously initiated reset pulse causes an additional reset delay from the time VSENSE becomes greater than VSNS. MANUAL RESET The manual reset input allows RESET1# and RESET2# to be activated by a pushbutton switch. The switch is effectively debounced by the 100ms minimum tRST (RESET pulse width). MR# can also be driven by an external logic input that meets the 50ns minimum pulse width required. Unregulated +12V DC DC to DC Converter 3.3V Out 3.3V MCU VCC VSENSE MCU #1 RESET1# MR# VCC RESET1# SMS1242 SMS1242 Test Point #1 MR# RESET2# ASIC or MCU #2 1.8V RESET2# VSENSE Low Voltage High Speed ASIC Test Point #2 2038 ILL7.0 2038 ILL8.0 Figure 5. Typical Multi-MCU Implementation 2038 2.0 6/8/00 Figure 6. Typical Dual Voltage Implementation 5 SUMMIT MICROELECTRONICS, Inc. SMS1242 Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR Parameter SCL clock frequency Clock low period Clock high period Bus free time Start condition setup time Start condition hold time Stop condition setup time Clock edge to valid output Data Out hold time SCL and SDA rise time SCL and SDA fall time Data In setup time Data In hold time Noise filter SCL and SDA Write cycle time Conditions Min. 0 4.7 4.0 Max. 100 Units kHz µs µs µs µs µs µs Before new transmission 4.7 4.7 4.0 4.7 SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change 0.3 0.3 3.5 µs µs 1000 300 250 0 Noise suppresion 100 5 ns ns ns ns ns ms 2038 Table01 2.0 tR tF tHIGH tLOW SCL tSU:SDA tHD:DAT tSU:DAT tSU:STO tHD:SDA tBUF SDA In tAA tDH SDA Out 2038 Fig07 2.0 Figure 7. Memory Timing SUMMIT MICROELECTRONICS, Inc. 2038 2.0 6/8/00 6 SMS1242 MEMORY OPERATION The SMS1242 memory is configured as a 2k × 8 array. Data is read and written via an industry standard two-wire interface. The bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are a serial data line (SDA) and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor located somewhere on the bus Input Data Protocol The protocol defines any device that sends data onto the bus as a “transmitter” and any device that receives data as a “receiver.” The device controlling data transmission is called the “master” and the controlled device is called the “slave.” In all cases the SMS1242 will be a “slave” device since it never initiates a data transfer. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time, because changes on the data line while SCL is high will be interpreted as start or stop condition. START and STOP Conditions When both the data and clock lines are high the bus is said to be not busy. A high-to-low transition on the data line while the clock is high is defined as the “START” condition. A low-to-high transition on the data line while the clock is high is defined as the “STOP” condition. Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line low to ACKnowledge that it received the eight bits of data. The SMS1242 will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected, the SMS1242 will respond with an ACKnowledge after the receipt of each subsequent 8-bit word. In the READ mode the SMS1242 transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected and no STOP condition is generated by the master, the SMS1242 will continue to transmit data. If an ACKnowledge is not detected the SMS1242 will terminate further data transmissions and await a STOP condition before returning to the standby power mode. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier. For the SMS1242 this is fixed as 1010BIN. The next three bits are the Most Significant Bits of the data address. They are supplied for write operations, and are "don't care" for read operations. Read/Write Bit The last bit of the data stream defines the operation to be performed. A “1” indicates a read operation; and a “0,” a write operation. Device Identifier 1 0 1 0 MS Address Bits R / W A10 A9 A8 1/0 2038 Table02 2.0 WRITE OPERATIONS The SMS1242 allows two types of write operations: byte write and page write. A byte write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. Byte Write Upon receipt of the word address the SMS1242 responds with an ACKnowledge. After receiving the next byte of data it responds with another ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the SMS1242 begins the internal write cycle. While the internal write cycle is in progress the SMS1242 inputs are disabled and the device will not respond to any requests from the master. Page Write The SMS1242 is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word the master can transmit up to 15 more bytes of data. After the receipt of each byte the SMS1242 will respond with an ACKnowledge. The SMS1242 automatically increments the address for subsequent data words. After the receipt of each word, the low order address bits are internally incremented by one. The high order bits of the address byte remain constant. 2038 2.0 6/8/00 SUMMIT MICROELECTRONICS, Inc. 7 SMS1242 MEMORY OPERATION (Continued) Should the master transmit more than 16 bytes, prior to generating the STOP condition, the address counter will “roll over” and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 8 for the address, ACKnowledge and data transfer sequence. Acknowledge Polling When the SMS1242 is performing an internal WRITE operation it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an acknowledge is issued, indicating that the internal WRITE cycle is complete. See the flow diagram for the proper sequence of operations for polling. READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to “1.” There are two different read options: 1. Current Address Byte Read 2. Random Address Byte Read Current Address Read The SMS1242 contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read Proceed With Write Await Next Command 2038 Flow01 2.0 Write Cycle In Progress Issue Start Issue Stop Issue Slave Address and R/W = 0 ACK Returned Yes No Next Operation a Write? Yes Issue Address No Issue Stop Master SDA Slave S T A R T R A 1AA/ 09 8W A C K S T A R T R / XX X W A C K Typical Write Operation AA A A A A A A 76 5 4 3 2 1 0 A C K DDDDDDDD 76543210 A C K DD 76 DD 10 A C K S T O P Typical Read Operation A C K DDDDDDDD 76543210 DDDDDDDD 76543210 A C K DD 76 DD 10 Master SDA Slave S T O P 2038 T Fig08 2.0 Figure 8. Memory Operation SUMMIT MICROELECTRONICS, Inc. 2038 2.0 6/8/00 8 SMS1242 or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the SMS1242 receives the slave address field with the R/W bit set to “1” it issues an acknowledge and transmits the 8-bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point, the SMS1242 discontinues data transmission. Random Address Read Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE), followed by the address of the word it is to read. This procedure sets the internal address counter of the SMS1242 to the desired address. After the word address acknowledge is received by the master it immediately reissues a start condition followed by another slave address field with the R/W bit set to READ. The SMS1242 will respond with an acknowledge and then transmit the 8data bits stored at the addressed location. At this point, the master does not acknowledge the transmission but does generate the stop condition. The SMS1242 discontinues data transmission and reverts to its standby power mode. Sequential READ Sequential reads can be initiated as either a current address READ or a random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge, indicating that it requires additional data from the SMS1242. The SMS1242 continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an ACKnowledge, and issues a STOP condition. During a sequential read operation, the internal address counter is automatically incremented with each ACKnowledge signal. For read operations, all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address, the address counter will roll-over, and the memory will continue to output data. 2038 2.0 6/8/00 SUMMIT MICROELECTRONICS, Inc. 9 SMS1242 ORDERING INFORMATION SMS1242 Base Part Number S A Option See Option Table Package S = SOIC Operating Temperature Range Part Number SMS1242S-A SMS1242S-B SMS1242S-C SMS1242S-D SMS1242S-E SMS1242S-F SMS1242S-* Operating Voltage VRST 4.425 4.475 4.676 VSNS Lead Count & Package Style 1V to 5.5V 4.450 2.650 2.950 PROG * 1.25V –40ºC to 85ºC 8 Pin SOIC 2038 Option Table 2.0 Table 3. Order Options SUMMIT MICROELECTRONICS, Inc. 2038 2.0 6/8/00 10 SMS1242 PACKAGE 8 Pin SOIC (Type S) Package JEDEC (150 mil body width) .050 (1.27) TYP. .050 (1.270) TYP. 8 Places .157 (4.00) .150 (3.80) .275 (6.99) TYP. 1 .196 (5.00) .189 (4.80) .030 (.762) TYP. 8 Places FOOTPRINT .061 (1.75) .053 (1.35) .020 (.50) x45° .010 (.25) .0192 (.49) .0138 (.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .035 (.90) .016 (.40) .244 (6.20) .228 (5.80) 8pn JEDEC SOIC ILL.2 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc. 2038 2.0 6/8/00 SUMMIT MICROELECTRONICS, Inc. 11