SMS24

SUMMIT MICROELECTRONICS, Inc. Highly Programmble Voltage Supervisory Circuit SMS24 FEATURES l User Programmable Device Configuration l Guaranteed Reset Valid to VCC = 1V l Immune to Short Negative VCC Transients l Six Unique Pin Configurations l User Programmable Feature Options: w Reset Threshold Voltages w Reset Pulse Widths w Programmable Watchdog Timeouts w Programmable Over- or Under-Voltage Sensing l High Reliability w Endurance: 100,000 erase/write cycles w Data retention: 100 years INTRODUCTION The SMS24 is a configurable and in-system programmable second generation 8 pin supervisory circuit. This single device is adaptable to provide the optimum functionality for a given system or sub-system. User programmable functions available — reset pulse width, watchdog delays, and voltage monitor thresholds — eliminate external components and allow standardization to enhance system reliability. Additionally, 4K bits of general purpose EEPROM is available on all configurations. The SMS24 is available in six pin configurations, and is compatible with all Summit programmable devices and other I2C components. Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Summit Microelectronics. DEVICE TYPES Function Device Code 001 010 011 100 101 110 Reset# ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ Reset ✔ Watchdog ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ Software WDI ✔ ✔ ✔ ✔ ✔ WDI Pin Write Protect Pin 2nd Voltage Monitor Manual Reset Input NV Memory ✔ ✔ ✔ ✔ ✔ ✔ 2048 DTTable 2.1 NC RESET# NC GND Device Code 001 VCC RESET SCL SDA NC RESET# NC GND Device Code 010 VCC WP SCL SDA WDI RESET# NC GND Device Code 011 VCC RESET SCL SDA RESET#2 RESET#1 VSENSE GND Device Code 100 VCC MR# SCL SDA VLOW# RESET# VSENSE GND Device Code 101 VCC RESET SCL SDA VLOW# RESET# VSENSE GND Device Code 110 VCC WDI SCL SDA 2046 DT 1.0 ©SUMMIT MICROELECTRONICS, Inc., 2001 • 300 Orchard City Dr., Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • FAX 408-378-6586 • www.summitmicro.com Characteristics subject to change without notice 2048 2.4. 3/1/01 1 SMS24 FUNCTIONAL BLOCK DIAGRAMS VCC 8 SCL SDA 6 5 NONVOLATILE MEMORY ARRAY WRITE CONTROL 2 PROGRAMMABLE RESET PULSE GENERATOR RESET# VTRIP + – RESET CONTROL 7 1.25V PROGRAMMABLE WATCHDOG TIMER RESET 4 GND 2046 BD001 2.1 Block Diagram Device Code 001 VCC 8 SCL SDA 6 5 NONVOLATILE MEMORY ARRAY WRITE CONTROL 7 WP 2 PROGRAMMABLE RESET PULSE GENERATOR RESET# VTRIP + – RESET CONTROL 1.25V PROGRAMMABLE WATCHDOG TIMER 4 GND 2046 BD010 2.1 Block Diagram Device Code 010 2 2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. SMS24 VCC 8 SCL SDA 6 5 NONVOLATILE MEMORY ARRAY WRITE CONTROL 2 PROGRAMMABLE RESET PULSE GENERATOR RESET# VTRIP + – RESET CONTROL 7 1.25V WDI 1 PROGRAMMABLE WATCHDOG TIMER RESET 4 GND 2046 BD011 1.0 Block Diagram Device Code 011 VCC 8 SCL SDA 6 5 NONVOLATILE MEMORY ARRAY WRITE CONTROL 2 PROGRAMMABLE RESET PULSE GENERATOR RESET#1 1 RESET#2 VTRIP + – RESET CONTROL 1.25V VSENSE 3 + – PROGRAMMABLE WATCHDOG TIMER 4 GND 2046 BD100 1.1 7 MR# Block Diagram Device Code 100 SUMMIT MICROELECTRONICS, Inc. 2048 2.4. 3/1/01 3 SMS24 VCC 8 SCL SDA 6 5 NONVOLATILE MEMORY ARRAY WRITE CONTROL 2 PROGRAMMABLE RESET PULSE GENERATOR RESET# VTRIP + – RESET CONTROL 7 1.25V PROGRAMMABLE WATCHDOG TIMER 1 VSENSE 3 + – UV RESET VLOW# OV 4 GND 2046 BD101 1.0 Block Diagram Device Code 101 VCC 8 SCL SDA 6 5 NONVOLATILE MEMORY ARRAY WRITE CONTROL 2 PROGRAMMABLE RESET PULSE GENERATOR RESET# VTRIP + – RESET CONTROL 1.25V PROGRAMMABLE WATCHDOG TIMER 7 WDI 1 VSENSE 3 + – UV VLOW# OV 4 GND 2046 BD110 1.0 Block Diagram Device Code 110 4 2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. SMS24 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ....................... -55°C to 125°C Storage Temperature ............................ -65°C to 150°C Lead Solder Temperature (10 secs) ................... 300 °C Terminal Voltage with Respect to GND: VCC ................................. -0.3V to 6.0V All Others ........................ -0.3V to 6.0V *COMMENT Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. DC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions; Voltages are relative to GND) Symbol VCC Parameter Operating supply voltage Conditions Valid RESET# output Memory operaton 3.6V < VCC < 5.5V ICC Supply current 2.7V < VCC < 3.6V Memory access RR4 RR3 RR2 RR1 RR0 0 VPRST Programmable reset threshold 0 0 0 1 VT VOL IMR VlL VIH VSENSE input threshold RESET#1, RESET#2, VLOW#: output voltage MR# pullup current Noise rejection on VCC Delay threshold crossing to RESET out 0.7 × VCC ISINK = 1.2mA, VCC = VPRST min. ISINK = 200mA, VCC = 1.2V 100 0.3 × VCC 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2.075 2.55 2.8 4.25 4.5 1.23 2.15 2.65 2.9 4.375 4.625 1.25 2.25 2.7 3.0 4.5 4.75 1.27 0.3 0.3 V V V V V V V V µA V V 2046 DCElect Table 2.0 Min. 1 2.7 Typ. Max. 5.5 5.5 50 20 3 Units V V µA µA µA ENDURANCE AND DATA RETENTION RECOMMENDED OPERATING CONDITIONS Temperature Voltage –40ºC to 85ºC. 2.7V to 5.5V The SMS24 is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. SUMMIT MICROELECTRONICS, Inc. 2048 2.4. 3/1/01 5 SMS24 PIN DESCRIPTIONS RESET# This signal is an active-low open drain I/O. Whenever the voltage on VCC is below the programmed threshold voltage the RESET# pin will be driven low. After VCC passes through the threshold (in a positive direction) the RESET# output will continue to be driven for the programmed timeout period (tPTO). In most configurations RESET# is also an input. Whenever it is driven low it will activate the reset timer. The RESET# output will then be driven low by the device for the programmed period. If the input pulse is of shorter duration than tPTO, RESET# will continue to be driven. If it is longer than tPTO, RESET# will be released and follow the input back high. RESET This signal is an active-high open drain I/O. Whenever the voltage on VCC is below the programmed threshold voltage the RESET pin will be driven high. After VCC passes through the threshold (in a positive direction) the RESET output will continue to be driven for the programmed timeout period. In all configurations using RESET it is also an input. Whenever it is driven high it will activate the reset timer. The RESET output will then be driven high by the device for the programmed period. If the input pulse is of shorter duration than tPTO, RESET will continue to be driven. If it is longer than tPTO, RESET will be released and follow the input back low. RESET#1 & RESET#2 These signals are active-low open drain outputs (not I/Os). These outputs are only available to Device Code 100, and are both set to a low state by any one of three events: VCC below trip level, VSENSE < 1.25V, or MR# strobed low. MR# Manual Reset input is an active low input. Whenever it is taken low it will generate a reset time-out. VSENSE This is a second voltage sense input connected to its own comparator that has reference of 1.25V. The comparator can be programmed to activate the VLOW# output either for an over-voltage or under-voltage condition. VLOW# This is an active-low open-drain output that can be wireORed with the RESET# output or tied directly to an interrupt input. WDI This is the Watchdog Interrupt input. Whenever a transition occurs on WDI the watchdog timer will be cleared. If the device does not receive an interrupt before tWDTO the device will drive the reset output(s). The period tWDTO is programmable for four basic values. It can also be placed into an idle mode, facilitating system debug, and allowing a system time to configure itself after a power-on. WP This is an auxilliary Write lockout input pin. When held high no writes will occur. SCL The serial interface clock input. SDA The serial interface data I/O. 6 2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. SMS24 DEVICE OPERATION REGISTERS Configuration Register The configuration Register, located at address 00, is illustrated in Table 1. The Configuration Bits (6, 5, & 4) select the basic Device Code, and are referred to as Con2, Con1, and Con0. Bit 7 is the Lock Bit, and when set to 1 locks the contents of the register. Note: The Threshold Trim* Bits are set at the factory. Before modifying them you must read the contents and save the value so that it can be written back into the device. After configuring them Bit 7 should be set to a 1 to prevent inadvertent modification. Table 1. Configuration Register MSB 7 LOCK 6 Con2 0 0 x 0 1 1 1 0 1 5 Con1 Valid Device Codes 0 1 1 0 0 1 1 0 1 0 1 0 Threshold Trim 4 Con0 3 T3 2 T2 1 T1 LSB 0 T0 * Configuration Register Open Configuration Locked (non-volatile) 2046 Table01 2.0 Programming Registers Once the device has been configured it is a simple matter of writing to the two Programming Registers to prepare the device for operation. Table 2. Programming Register 0 MSB 7 6 RT1 5 RT0 2.15V à 2.65V à 2.90V à 4.375V à 4.625V à 4 RR4 0 0 0 0 1 ß 25ms ß 50ms ß 100ms ß 200ms 3 RR3 0 0 0 1 0 2 RR2 Reset Threshold Bits 0 0 1 0 0 1 RR1 0 1 0 0 0 LSB 0 RR0 1 0 0 0 0 Reset Threshold Volts x Reset Timeout Bits 0 0 1 1 SUMMIT MICROELECTRONICS, Inc. Reset Timeout Seconds 0 1 0 1 2046 Table02 2.0 2048 2.4. 3/1/01 7 SMS24 Table 3. Programming Register 1 MSB 7 6 LOCK 5 OV 4 Add 3 DT 2 WD2 0 0 1 1 1 1 1 WD1 0 1 0 0 1 1 LSB 0 WD0 x 1 0 1 0 1 Watchdog Timeout Seconds OFF or Idle Mode à 0.4s à 0.8s à 1.6s à 3.2s à x x x x 0 1 0 1 0 1 6.4s à 0 1 Watchdog Timeout Bits Device Type Address 1010 Device Type Address 1011 Responds to Address Pin Bias Ignores Address Pin Bias x x VSENSE Triggers > Threshold (1.25V) VSENSE Triggers < Threshold (1.25V) x PR Registers Open for Writing PR Registers Writing Lockout 2048 Table03 2.0 MEMORY OPERATION The SMS24 memory is configured as a 2K x 8 array. Data is received and transmitted via an industry standard twowire interface. The bus was designed for two-way, twoline serial communication between different integrated circuits. The two lines are a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus START and STOP Conditions When both the data and clock lines are high, the bus is said to be not busy. A high-to-low transition on the data line, while the clock is high is defined as the “START” condition. A low-to-high transition on the data line while the clock is high is defined as the “STOP” condition. START Condition SCL STOP Condition Input Data Protocol Configuring and programming the SMS24 is done using the 2-wire serial interface. The device type address for this operation is 1001BIN. The protocol defines any device that sends data onto the bus as a “transmitter” and any device that receives data as a “re ceiver.” The device controlling data transmission is called the “master” and the controlled device is called the “slave.” In all cases the SMS24 will be a “slave” device, since it never initiates any data transfers. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time because changes on the data line while SCL is high will be interpreted as a start or a stop condition. 8 SDA In 2046 Fig01 2.0 Figure 1. START and STOP Conditions Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line low to ACKnowledge that it received the eight bits of data. SUMMIT MICROELECTRONICS, Inc. 2048 2.4. 3/1/01 SMS24 S T A R Device Type Bus T Address Address Write Configuration Register S T O P 1001 R XXX/ W A C K 0 0 00 00 11 A C K L OCCCT T T T C2 1 0 3 2 1 0 K A C K Master SDA SMS24 S T A R Device Type Bus T Address Address Program Register 0 S T O P 1001 R XXX/ W A C K 0 0 00 00 00 A C K RRRRRRR XTTRRRRR 1043210 A C K Master SDA SMS24 S T A R Device Type Bus T Address Address Program Register 1 S T O P 1001 R XXX/ W A C K 0000 00 01 A C K L WWW X OOADDD D C VDT K 210 A C K 2046 Fig02 2.0 Figure 2. Programming the SMS24 The SMS24 will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected the SMS24 will respond with an ACKnowledge after the receipt of each subsequent 8-bit word. In the READ mode the SMS24 transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected, and if no STOP condition is generated by the master, the SMS24 will continue to transmit data. If an ACKnowledge is not detected the SMS24 will terminate further data transmissions and await a STOP condition before returning to the standby power mode. four bits of the slave address are the device type identifier. For the SMS24 this is be 1010BIN or 1011BIN depending upon the DT bit of PR1. The configuration and Program Registers have a device type address of 1001. The next three bits are the high order address bits. The last bit of the data stream defines the operation to be performed. When set to “1” a read operation is selected. When set to “0” a write operation is selected. WRITE OPERATIONS The SMS24 allows two types of write operations: byte write and page write. A byte write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant SUMMIT MICROELECTRONICS, Inc. 2048 2.4. 3/1/01 9 SMS24 Table 4. Device Addressing Device Identifier Bits Memory Address A10 A9 A8 Read à Write à x 1 1 1 0 0 0 1 1 0 0 1 1 x x R/W 1 0 x acknowledge is issued, indicating that the internal WRITE cycle is complete. See the flow diagram for the proper sequence of operations for polling. Write Cycle In Progress ß Default Memory Device ß Alternate Memory Device ß Configuration Register Device 2046 Table04 2.0 Issue Start Issue Stop Issue Slave Address and R/W = 0 Byte Write After the slave address is sent an ACKnowledge is generated and then the balance of the address is transmitted. Upon receipt of the word address the SMS24 responds with an ACKnowledge. After receiving the next byte of data it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the SMS24 begins the internal write cycle. While the internal write cycle is in progress the SMS24 inputs are disabled and the device will not respond to any requests from the master. ACK Returned Yes No Next Operation a Write? Yes Issue Address No Issue Stop Page Write The SMS24 is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more bytes of data. After the receipt of each byte the SMS24 will respond with an ACKnowledge. The SMS24 automatically increments the address for subsequent data words. After the receipt of each word the low order address bits are internally incremented by one. The high order bits of the address byte remain constant. Should the master transmit more than 16 bytes, prior to generating the STOP condition, the address counter will rollover, and the previously written data will be overwritten. As with the byte-write operation all inputs are disabled during the internal write cycle. Proceed With Write Await Next Command 2046 Flow01 1.0 Flow Diagram READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to “1.” There are two different read options: 1. Current Address Byte Read, or 2. Random Address Byte Read Current Address Read The SMS24 contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and incre- Acknowledge Polling When the SMS24 is performing an internal WRITE operation it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an 10 2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. SMS24 ment the current address pointer. When the SMS24 receives the slave address field with the R/W bit set to “1” it issues an acknowledge and transmits the 8-bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point the SMS24 discontinues data transmission. Sequential READ Sequential reads can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge, indicating that it requires additional data from the SMS24. The SMS24 continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an ACKnowledge, and issues a STOP condition. During a sequential read operation the internal address counter is automatically incremented with each ACKnowledge signal. For read operations all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address the address counter will rollover and the memory will continue to output data. Random Address Read Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMS24 to the desired address. After the word address acknowlthe R/W bit set to READ. The SMS24 will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. At this point the master does not acknowledge the transmission but does generate the stop condition. The SMS24 discontinues data transmission and reverts to its standby power mode. SUMMIT MICROELECTRONICS, Inc. 2048 2.4. 3/1/01 11 SMS24 IN-SYSTEM PROGRAMMING THE SMS24 The need for an in-system programming interface for a supervisory circuit is necessitated by the rapid change to both board designs (feature upgrades to a common design core) and the ICs resident on the boards. The SMS24 provides an ideal solution for maintaining currency with the change in boards and their power supplies as they shift from generation to generation. Notes: If the device appears to be ignoring attempts to be programmed ensure the supplied VCC is above the programmed threshold. If VCC is below the reset threshold all attempts to write to the device will be ignored. If you are writing to the memory array and ‘readbacks’ show occasional rows not being written check the watchdog timer. Either disable the watchdog or insure WDI is being strobed (high to low) at intervals less than the programmed watchdog time out period. Figure 3 is a block diagram illustration of the SMS24 configured as device code 110. The comments in bold italics indicate the programmable options for this code Supporting the SMS24 is a programming module, the SMX3199-A. The hardware is a small printed circuit card that interfaces to a standard PC parallel printer port. A target programming cable is connected from this to the user’s card. The software provides an intuitive configuration screen and also a memory test verification screen (examples of the screens are shown). Theory of Operation The SMS24 can be designed-in with the simple addition of an inexpensive 9-pin 0.100” centerline header. Summit supports this configuration with the SMX3199-A programmer, and in the future will support this interface with the SMX3200. Depending upon the end use of the interface, prototyping vs. field support, the header can be placed anywhere on the board or as a right angle header at the back edge of the card (the side pointing outwards from a card cage). The basic interface circuit is shown in Figure 3. In order to clearly illustrate the examples, all additional traces and series resistors are either bold or outlined in a dashed box. Board WDI in 100kΩ 10kΩ 1kΩ VLOW# Board RST# Board VSENSEIN 1kΩ RST# VCC 10kΩ 1kΩ WDI WDI SCL SDA VSENSE SCL GND SDA Device code 110 Board Serial Bus 2046 Fig03 2.0 Figure 3. Basic Interface Circuit 12 2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. SMS24 VCC 8 SCL SDA 6 5 NONVOLATILE MEMORY ARRAY Programmable Device Type Identifier 1010 1011 WRITE CONTROL Programmable Reset Pulse 25ms 50ms 100ms 200ms 2 RESET# PROGRAMMABLE RESET PULSE GENERATOR Programmable Threshold 4.63V 4.37V 2.90V 2.65V 2.15V VTRIP + – RESET CONTROL 1.25V PROGRAMMABLE WATCHDOG TIMER Programmable Watchdog Timer Off 0.4s 0.8s 1.6s 3.2s 7 WDI 1 VLOW# VSENSE 3 + – UV OV 4 GND Programmable VLOW Trigger Overvoltage Undervoltage 2046 Fig04 2.0 Figure 4. Programmable Options for Device Code 110 Figure 5. Configuration Screen SUMMIT MICROELECTRONICS, Inc. 2048 2.4. 3/1/01 Figure 6. Memory Test Screen 13 SMS24 Table 5. Memory AC Operating Characteristics Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR Parameter SCL clock frequency Clock low period Clock high period Bus free time Start condition setup time Start condition hold time Stop condition setup time Clock edge to valid output Data Out hold time SCL and SDA rise time SCL and SDA fall time Data In setup time Data In hold time Noise filter SCL and SDA Write cycle time Noise suppression 250 0 100 5 SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change Before new transmission Conditions Min. 0 4.7 4.0 4.7 4.7 4.0 4.7 0.3 0.3 1000 300 3.5 Max. 100 Units kHz µs µs µs µs µs µs µs µs ns ns ns ns ns ms tR tF tHIGH tLOW SCL tSU:STA tHD:DAT tSU:DAT tSU:STO tHD:STA tBUF SDA In tAA tDH SDA Out 2046 Fig07 2.0 Figure 7. Memory Operating Characteristics 14 2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. SMS24 tGLITCH VPRST VCC 1V tPTO tRPD tPTO RESET# VCC / RESET# Timing Diagram