AP0332CG

– Ordering Information VDD (max) -320V RO(ON) (max) 700Ω LETE – OBSO IO(OFF) (max) -1.0nA Order Number/Package SO-16 AP0332CG Die AP0332ND AP0332 8 P-Channel Latchable Power MOSFET Array IO(ON) (min) -15mA *Average current per channel, measured with all eight channels connected in parallel. Features Low drain to source leakage Interfaces directly to TTL and CMOS logic 8 independent channels Low crosstalk between channels Low power dissipation Freedom from secondary breakdown Serial data input On-chip decoder, latch with set and write disable circuitry General Description The Supertex AP0332 is an 8 P-Channel 320V common source power MOSFET array with a CMOS 8 bit addressable latch. The outputs are guaranteed to have very low leakage current. The outputs are addressed by logic inputs A0, A1, and A2. The addressed and unaddressed output can be turned on or off by the data, set, and write disable inputs. The AP0332 is ideally suited for low leakage/high impedance measurements, providing excellent accuracy as well as resolution for automatic bare board test equipment and other applications. 9 Applications High impedance/low leakage measurements for bare board testers High voltage piezoelectric transducer drivers High voltage electroluminescent panel drivers High voltage electrostatic array drivers General multi-channel driver arrays Q7 Set Data 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Pin Configuration VDD Q6 Q5 Q4 Q3 Q2 Q1 Q0 Absolute Maximum Ratings1 Off-state output voltage, VOO Logic supply voltage, VDD Logic input levels, all inputs Operating and storage temperature range Soldering temperature 2 Channel-to-channel crosstalk Notes: 1. All voltages are referenced to VSS. 2. Distance of 1.6mm from case for 10 seconds. Write Dis A0 -320V A1 A2 VSS -0.5V to +15V -0.5V to VDD -55°C to +150°C 300°C 10mV/V top view SO-16 Note: See Package Outline section for dimensions. 9-5 AP0332 Electrical Characteristics (@ 25°C and V DC Characteristics Symbol IO(OFF) IO(ON) RO(ON) ∆RO(ON) IDDQ VIL VIH IIN Parameter Off-State Output Current On-State Output Current On-State Output Resistance Change in RO(ON) with High Temperature Quiescent Logic Supply Current Input Low Voltage Input High Voltage Input Current DD = 12V unless otherwise specified) Typ Max -8.0 Unit nA mA 700 0.8 0.05 16.5 3.5 Ω %/°C µA V V 1.0 µA Conditions VO = max. rating, 8 outputs connected in parallel VO = 25V IO = -10mA IO = -10mA Min -15 12 Note: 1. All voltages are referenced to VSS. AC Characteristics Symbol tD(ON) tD(OFF) tr tf tPHL, tPLH tPHL, tPLH tPHL, tPLH tW tW tW tS tH CIN Parameter Turn-On Delay Time Turn-Off Delay Time Rise Time Fall Time LETE – OBSO – Min Typ 800 800 200 200 87 87 107 50 100 40 50 75 5.0 7.5 100 200 75 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns pF Fig. 1* 1a 1b 10 11 2 3 9 4 8 5 6 7 Conditions Propagation Delay Time from Write Disable to Output Propagation Delay Time from Set to Output Propagation Delay Time from Address to Output Minimum Pulse Width – Data Minimum Pulse Width – Address Minimum Pulse Width – Set Setup Time – Data to Write Disable Hold Time – Data to Write Disable Input capacitance – Any Input VO = 25V, IO = -10mA *Refer to circled numbers on Timing Diagram (Figure 1). Note: 1. All voltages are referenced to VSS. 9-6 AP0332 Recommended Operating Conditions (For maximum reliability, nominal operating conditons should be selected so that operation is always within the following ranges.) Symbol VDD VO VIH VIL TA Parameter Logic supply voltage Output Voltage referenced to VDD Input High Voltage Input Low Voltage Operating Free-Air Temperature 12V 12V VDD Min 10.0 0 VDD - 2 0 0 Max 13.2 -320 VDD 2.0 70 Unit V V V V °C Note: 1. All voltages are referenced to VSS. Mode Selection Data H L H L H L H L LETE – OBSO – Write Disable L H L H Set L L H H Addressed Output Off On Holdspriv. Off On Off Unaddressed Outputs Holdspriv. Holdspriv. Off Off 9 Timing Diagram A0, A1, A2 tW 8 Write Disable Data tW Set Q0 ON Q0 OFF Q7 ON Q7 OFF 1b td(OFF) tR 10 tP 3 tf 11 tP 9 td(ON) 1a tP 2 5 tW 4 tS 6 tH 7 Figure 1 9-7 AP0332 Functional Block Diagram Data Write Disable ETE – OBSOL – VDD (+) S Latch Q7 Latch Q6 Latch A0 Latch A1 3:8 Decoder Latch A2 Latch Q5 Q4 Q3 Q2 Latch Q1 Latch Q0 Set VSS (–) 9-8