LR645_07

LR645 High Input Voltage SMPS Start-up / Linear Regulator Features ► ► ► ► ► ► Accepts inputs from 15V to 450V Output currents up to 3.0mA continuous, 30mA peak Supply current typically 50µA Line regulation typically 0.1mV/V Output can be trimmed from 8.0V to 12V Output current can be increased to 150mA with external FET General Description The Supertex LR645 is a high input voltage, low output current linear regulator. It has a 3-terminal fixed output voltage version available in TO-92, TO-220 and SOT-89 packages, as well as an adjustable voltage version available in an 8lead SOIC package. The 3-terminal version functions like any other low voltage 3-terminal regulator except it allows the use of much higher input voltages. When used in a SMPS startup circuit, it eliminates the need for large power resistors. In this application, current is drawn from the high voltage line only during start-up. Only leakage current flows after start-up, thereby reducing the continuous power dissipation to a few milliwatts. The adjustable voltage version allows trimming of the output voltage from 8.0V to 12V. This version can also be connected to an external depletion mode MOSFET for increased output current. When used in conjunction with Supertex depletion mode MOSFET DN2540N5, an output current of up to 150mA is achieved. Applications ► Off-line SMPS startup circuits (pulse loads) ► Low power off-line regulators ► Regulators for noisy inputs Caution! The LR645 does NOT provide galvanic isolation. When operated from an AC line, potentially lethal voltages can be present on the IC. Adequate means of protecting the end user from such voltages must be provided by the circuit developer. Block Diagram VIN LR645 VOUT TRIM – + GATE GND LR645 Ordering Information Device Package Option TO-92 LR645N3 TO-243AA LR645N8 TO-220 LR645N5 8-Lead SOIC LR645LG 1 2 3 Pin Configurations 1 8 TAB LR645 LR645N3-G LR645N8-G LR645N5-G LR645LG-G 8-Lead SOIC TAB -G indicates package is RoHS compliant (‘Green’) TO-243AA (SOT-89) Thermal Characteristics Package SOIC TO-92 TO-220 TO-243AA Power Dissipation @TA = 25OC 0.31W 0.74W 1.8W 1.6W O 1 3 2 1 2 3 θJC C/W O θJA C/W TO-92 TO-243AA TO-220 8-Lead SO TO-220 TO-92 156 125 8.3 15 400* 170 70 78* +VIN 1 1 1 1 GND 2 2, TAB 2, TAB 3 VOUT 3 3 3 4 TRIM 5 GATE 7 * Mounted on FR4 board; 25mm x 25mm x 1.57mm Significant PD increase possible on ceramic substrate Absolute Maximum Ratings Parameter Input voltage Output voltage Operating and storage temperature Soldering temperature Value 450V 15.5V -55°C to +150OC 300OC Package Markings Y YWW LR645 LLLL YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging 8-Lead SOIC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. LR6 = 2-week alpha date code TO-243AA Electrical Characteristics (Test conditions unless otherwise specified: TA = 25°C; VIN = 15 to 450V, COUT = 0.01µF) Symbol VOUT ΔVOUT VIN IINQ IOFF Parameter Output voltage Output voltage over temperature1 Line regulation Load regulation Operating input voltage range Input quiescent current VIN off-state leakage current Min 9.3 9.0 15 - Typ 10 10 40 150 50 0.1 Max 10.7 11.5 200 400 450 150 10 Units V V mV mV V µA µA Conditions No load TJ = - 40°C ≤ to + 125°C, No load VIN = 15V to 400V, No load VIN = 50V, IOUT = 0 to 3.0mA --No Load VAUX ≥ VOUT +1V applied to VOUT pin 2 LR645 Symbol IAUX ΔVOUT/ ΔVIN en IPEAK VAUX Parameter Input current to VOUT Ripple rejection ratio1 Noise voltage1 Output peak current2 External voltage applied to VOUT Min 50 Typ 60 25 30 Max 200 13.2 Units µA dB µV mA V Conditions VAUX ≥ VOUT +1V applied to VOUT pin 120Hz, No Load 0.01 to 100KHz COUT = 10µF, VIN = 400V --- 8-lead, adjustable output voltage version only: Test conditions unless otherwise specified: TA = 25°C; VIN = 15 to 450V, COUT = 0.01µF VOUT ΔVOUT Output regulation trim range1 Load regulation at 8V trim 1 8 - 200 100 12 400 400 V mV mV No load VIN = 15V, IOUT = 0 to 1.0mA VIN = 50V, IOUT = 0 to 3.0mA Load regulation at 12V trim1 Notes: 1. Guaranteed by design, not tested in production. 2. Pulse test duration < 1.0msec, Duty cycle < 2% LR645: SMPS Start-Up Circuit One of the main applications for the LR645 is a start-up circuit for off-line switch-mode power supplies (SMPS), as shown in Figure1. A minimum output capacitance of 0.01µF is recommended for stability. The wide operating input voltage range of the LR645 allows the SMPS to operate and start-up from rectified AC or a DC voltage of 15V to 450V without adjustment. During start-up, the LR645 powers the VCC line of the PWM IC with a nominal output voltage of 10V. The auxiliary voltage connected through a diode to the VOUT pin of the LR645 will start to increase. When the auxiliary voltage becomes larger than the output voltage the LR645 turns OFF its internal high voltage input line and output voltage, allowing the auxiliary voltage to power the VCC line of the PWM IC. The input current drawn by the LR645 from the high voltage line after start-up will therefore only be leakage current of the internal MOSFET switch, which is typically 0.1µA. The 3-terminal version shown in Figure 1 has load regulation guaranteed from 0 to 3.0mA at a fixed nominal output voltage of 10V. Applications requiring higher output current and/or a different output voltage can use the 8 pin adjustable version. Figure 1: SMPS Start-Up Circuit + + 5.0V – VAUX = 12V 15V to 450V VIN VCC LR6 CIN – PWM IC COUT GND 3 LR645 LR645: High Current SMPS Start-Up Circuit The 8 lead version of the LR645 has connections for an external depletion-mode MOSFET for higher output current and external resistors for adjustable output voltage. As shown in Figure 2, the output current is increased to 150mA by using the Supertex 400V depletion-mode MOSFET DN2540. The maximum operating input voltage will be limited by the drainto-source breakdown voltage of the external MOSFET, but cannot exceed the 450V rating of the LR645. The output voltage can be adjusted from 8V to 12V with 2external resistors, R1 and R2. The ratio of R2/R1 determines the output voltage. R2 is connected between the VOUT and TRIM pins. R1 is connected between TRIM and GND pins. Figure 5 is a curve showing output voltage versus resistor ratio R2/R1. The optimum range for R1 + R2 is 200KΩ to 300KΩ. This minimizes loading and optimizes accuracy of the output voltage. Figure 5 uses an R1 + R2 of 250KΩ. Figure 2: High Current SMPS Start-Up Circuit + DN2540 + 5.0V – GATE 15V to 400V CIN GND – Note: When used with the DN25, +VIN is not connected on the LR6. VAUX = 12V VOUT VCC R2 TRIM R1 LR645 PWM IC COUT LR645: Off Line Linear Regulator Circuits requiring low voltages to operate logic and analog circuits benefit from the LR645. The conventional use of step down transformers can be eliminated, thereby saving space and cost. Some examples of these applications are: proximity controlled light switches, street lamp controls, and low voltage power supplies for appliances such as washing machines, dishwashers, and refrigerators. The wide operating input voltage range of 15V to 450V as well as the ripple rejection ratio of 50dB minimum allows the use of a small, high voltage input capacitor. The input AC line can be either full-wave or half-wave rectified. A minimum output capacitance of 0.01µF is recommended for output stability. Figure 3 shows the LR645 as a pre-regulator to a precisionregulator for high precision regulation. Higher output current is also possible by using an external depletion-mode MOSFET DN2540N5 as shown in Figure 4. Power Dissipation Considerations The LR645 is a true linear regulator. Its power dissipation istherefore a function of input voltage and output load current. Forexample, if the LR645 is providing a continuous load current of 3mAat 10V while its input voltage is 400V, total dissipation in the LR645 will be: PDISS= (VIN - VOUT) x (IOUT + IMAX QUIESCENT) = (400V - 10V) x (3.0mA + 150µA) = 1.23 Watts The 1.23 watts is for continuous operation. This is within the dissipation capabilities of the TO-220 and SOT-89 packages. See the thermal characteristics chart on page 2 for deratings. For SMPS start-up applications, the output current is usually required only during start-up. This duration depends upon the auxiliary supply output capacitor and COUT, but is typically a few hundred milliseconds. All package types of the LR645 have been characterized for use with a COUT of at least 10µF, and an AC line of 277V. Figure 3: Cascading for Precision LR6 AC Line 24V to 277V CIN 1.0µF COUT 0.1µF Max 875 ACSA 5.000V ± 0.002V @ 0 to 3mA 4 LR645 Figure 4: High Current Regulation DN2540N5 AC Line 24V to 277V GATE LR645LG CIN VOUT 5.0V REG COUT 5.0V + 0 to 150mA – GND Figure 5: Typical Output Voltage vs Resistor Ratio 12 Output Voltage (V) 10 R1 + R2 = 250KΩ 8 2.5 3.0 3.5 4.0 Resistor Ratio (R2/R1) 5 LR645 8-Lead SOIC (Narrow Body) Package Outline (LG/TG) 4.9x3.9mm body, 1.75mm height (max), 1.27mm pitch D 8 E E1 Note 1 (Index Area D/2 x E1/2) L θ1 L2 Gauge Plane 1 L1 θ Seating Plane Top View A Note 1 View B View B h h A A2 Seating Plane A1 e b Side View A View A-A Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) NOM MAX A 1.35 1.75 A1 0.10 0.25 A2 1.25 1.50 b 0.31 0.51 D 4.80 4.90 5.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 1.27 BSC h 0.25 0.50 L 0.40 1.27 L1 1.04 REF L2 0.25 BSC θ 0O 8 O θ1 5O 15O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. Drawings not to scale. 6 LR645 3-Lead TO-92 Package Outline (N3) D A Seating Plane 1 2 3 L b e1 e C Front View Side View E1 E 1 2 3 Bottom View Symbol MIN Dimension (inches) NOM MAX Drawings not to scale. A .170 .210 b .014 .022 C .014 .022 D .175 .205 E .125 .165 E1 .800 .105 e .095 .105 e1 .045 .055 L .500 - 7 LR645 3-Lead TO-220 (Power Package) Package Outline (N5) A E E2 Q H1 4 D D1 Chamfer Optional 1 2 3 E1 D2 ΦP A Seating Plane A1 E Thermal Pad Detail B L A2 e c A Front View Side View View A - A 1 2 3 L1 b2 b Detail B Symbol MIN Dimension (inches) NOM MAX A .140 .190 A1 .020 .055 A2 .080 .115 b .015 .027 .040 b2 .045 .057 .070 c .014 .024 D .560 .650 D1 .330 .355 D2 .480 .507 E .380 .420 E1 .270 .350 E2 .030 e H1 .230 L .500 .580 L1 .250 Q .100 .135 ΦP .139 .161 .100 BSC .270 JEDEC Registration TO-220, Variation AB, Issue K, April 2002. Drawings not to scale. 8 LR645 3-Lead TO-243AA (SOT-89) Package Outline (N8) D D1 4 C EH E1 1 L b e 2 3 b1 e1 A Top View Side View Symbol MIN Dimensions (mm) NOM MAX A 1.40 1.60 b 0.44 0.56 b1 0.36 0.48 C 0.35 0.44 D 4.40 4.60 D1 1.62 1.83 E 2.29 2.60 E1 2.13 2.29 e 1.50 BSC e1 3.00 BSC H 3.94 4.25 L 0.89 1.20 JEDEC Registration TO-243, Variation AA, Issue C, July 1986. Drawings not to scale. (The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-LR645 B050807 9