RBHV7022DJ-C

HV7022-C 34-Channel Symmetric Row Driver Ordering Information Package Options Device 44 J-Lead Quad Ceramic Chip Carrier HV7022DJ-C 44 J-Lead Quad Plastic Chip Carrier HV7022PJ-C Die in waffle pack HV7022X-C 44 J-Lead Quad Ceramic Chip Carrier (MIL-Std-883 Processed*) RBHV7022DJ-C HV7022-C *For Hi-Rel process flows, refer to page 5-3 of the databook. Features ❏ Processed with HVCMOS® technology ❏ Symmetric row drive (reduces latent imaging in ACTFEL displays) ❏ Output voltages up to 230V ❏ Low-power level shifting ❏ Source/Sink current 70mA (min.) ❏ Shift register speed 4MHz ❏ Pin-programmable shift direction ❏ 44-lead plastic & ceramic surface-mount packages ❏ Hi-Rel processing available General Description The HV7022-C is a low-voltage serial to high-voltage parallel converter with push-pull outputs. It is especially suited for use as a symmetric row driver in AC thin-film electroluminescent (ACTFEL) displays. The HV70 offers 34 output lines, a direction (DIR) pin to give CW or CCW shift register loading, output enable (OE), and polarity (POL) control. After DATA INPUT is entered (on the falling edge of CLOCK), a logic high will cause the output to swing to VPP if POL is high, or to GND if POL is low. Absolute Maximum Ratings Supply voltage, VDD1 Supply voltage, Logic input Ground VPP1 levels1 -0.3V to +15V -0.3V to +250V -0.3V to VDD +0.3V 1.5A dissipation3: Plastic Ceramic 1200mW 1500mW -40°C to +85°C -55°C to 125°C -65°C to +150°C 260°C current 2 Continuous total power Operating temperature range Storage temperature range Plastic Ceramic Lead temperature 1.6mm (1/16 inch) from case for 10 seconds Notes: 1. All voltages are referenced to GND. 2. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 25mW/°C for plastic and at 15mW/°C for ceramic. For Detailed circuit and application information, please refer to Application Note AN-H3. 02/96/022 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV7022-C Electrical Characteristics (over recommended operating conditions of VDD = 12V, TA = 25°C and VPP = 230V unless otherwise noted) DC Characteristics Symbol IDD IPP Parameter VDD supply current High voltage supply current Min Max 10 4 100 750 IDDQ VOH VOL IIH IIL Quiescent VDD supply current High-level output HVOUT Data out Low-level output HVOUT Data out High-level logic input current Low-level logic input current 195 11 30 1 1 -1 100 Units mA mA µA µA µA V V V V µA µA Conditions fCLK = 4MHz 1 Output high1 All Outputs low or High-Z All Outputs low or High-Z (125°C) All VIN = GND or VDD IO= -70mA (-50mA)2 IO= -500µA IO= 70mA (+50mA)2 IO= 500µA VIH = 12V VIL = 0V Notes: 1. The total number of ON outputs times the duty cycle must not exceed the allowable package power disspation. 2. Over military temperature range (-55°C to 125°C). AC Characteristics (VDD = 12V, TC = 25°C) Symbol fCLK tW tSUD tHD tSUC tSUE tSUP tHC tHE tHP tDHL t DLH tTHL tTLH tONH tONL tOFFH tOFFL Parameter Clock frequency Pulse duration clock high or low Data set-up time before falling clock Data hold time after falling clock Setup time clock low before VPP↑ or GND↓ Setup time enable high before VPP↑ or GND↓ Setup time polarity high or low before VPP↑ or GND↓ Hold time clock high after VPP↑ or GND↓ Hold time enable high after VPP↑ or GND↓ Hold time polarity high or low after VPP↑ or GND↓ Delay time high to low level output from clock Delay time low to high level output from clock Transition time high to low level serial output Transition time low to high level serial output High level turn-on time Q outputs from enable Low level turn-on time Q outputs from enable High level turn-off time Q outputs from enable Low level turn-off time Q outputs from enable Slew rate, VPP or GND 125 100 100 300 300 300 500 300 300 150 200 200 100 500 500 1000 500 45 Min Max 4 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns V/µs CL = 10pF CL = 10pF CL = 15pF CL = 15pF IO = -50 mA,VOH =195V RL = 2 kΩ to 95V IO = 50 mA,VOH =130V RL = 2 kΩ to 30V IO = -50 mA,VOH =195V RL = 2 kΩ to 95V IO = 50 mA,VOH =130V RL = 2 kΩ to 30V With one active output driving a 4.7 nF load to VPP or GND Conditions 2 HV7022-C Recommended Operating Conditions Symbol VDD VPP VIH VIL fCLK TA IOD Logic supply voltage High voltage supply High-level input voltage VDD = 10.8V VDD = 13.2V Low-level input voltage VDD = 10.8V VDD = 13.2V Clock frequency Operating free-air temperature Plastic Ceramic Allowable pulse current through output diodes -40 -55 8.1 9.9 2.7 3.3 4 +85 +125 ±300 MHz °C °C mA V Parameter Min 10.8 Max 13.2 230 Units V V V Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Input and Output Equivalent Circuits VDD VDD VPP Input Data Out HVOUT GND Logic Inputs GND Logic Data Output GND High Voltage Outputs 3 HV7022-C Switching Waveforms l/fCLK tWL Clock 50% tSUD Data Input 50% tDLH Data Output (D IOA/D IOB) 90% 10% tTLH V PP tSUC 90% GND tTHL tHD 50% VIL tDHL 90% 10% VOH VOL 50% tWH VIH 50% VIH 10% tHC VIH POL 50% 50% VIL 90% GND tHP tSUP V PP 10% VIH OE 50% tSUE tHE 90% 50% VIL VOH 10% HV OUT High Impedance HV OUT tONL tONH tOFFH 90% 10% tOFFL High Impedance VOL 4 HV7022-C Functional Block Diagram VPP OE Polarity VDD LT Data In N HVOUT1 P LT CLK S/R DIR HVOUT2 LT HVOUT34 Data Out GND LT = Level Translator Function Table Inputs I/O Relations O/P HIGH O/P OFF O/P LOW O/P OFF O/P OFF Load S/R, set DIR Notes: H = logic high level, L = logic low level, X = irrelevant, ↓ = high-to-low transition, Q1 = HVOUT 1, Qn = HVOUT(n), etc. * = dependent on previous state and whether an O/P or S/R command occured. Outputs POL H H L L X X X X OE H H H H L X X X Shift Reg * * * * * Qn →Qn+1 Qn →Qn-1 * HV Outputs H HIGH-Z L HIGH-Z All O/P HIGH-Z * * No Change * * * * Q34 Q1 No Change Data Out CLK X X X X X ↓ ↓ No ↓ DIR X X X X X L H X Data H L H L X X X X 5 HV7022-C HVOUT Characteristics 180 Temp = 25° C 180 Temp = 25° C 140 140 I(mA) 100 I(mA) VDD = 12 VDD = 14 VPP > 40V VDD = 12V & 14 V 100 60 VDD = 10 60 20 20 0 20 40 60 80 100 0 20 40 60 80 100 Volts Output N-Channel Characteristics through FET Volts (VPP - VOUT) Output P-Channel Characteristics through FET Pin Configurations HV70 44 Pin J-Lead Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Note: Pin designation for DIR L/H Example:For DIR = L, pin 1 is HVOUT 18 For DIR = H, pin 1 is HVOUT 17 Package Outline 39 38 37 36 35 34 33 32 31 30 29 Function HVOUT 18/17 HVOUT 17/18 HVOUT 16/19 HVOUT 15/20 HVOUT 14/21 HVOUT 13/22 HVOUT 12/23 HVOUT 11/24 HVOUT 10/25 HVOUT 9/26 HVOUT 8/27 HVOUT 7/28 HVOUT 6/29 HVOUT 5/30 HVOUT 4/31 HVOUT 3/32 HVOUT 2/33 HVOUT 1/34 Data Out Output Enable Clock GND Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function DIR VDD Polarity Data In VPP N/C HVOUT 34/1 HVOUT 33/2 HVOUT 32/3 HVOUT 31/4 HVOUT 30/5 HVOUT 29/6 HVOUT 28/7 HVOUT 27/8 HVOUT 26/9 HVOUT 25/10 HVOUT 24/11 HVOUT 23/12 HVOUT 22/13 HVOUT 21/14 HVOUT 20/15 HVOUT 19/16 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18 top view 44-pin J-Lead Package 02/06//02 ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 6 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com Package Outline 44-Lead PQFP Package Outline (PG) D D1 E E1 Note 1 (Index Area D1/4 x E1/4) L2 48 1 b e L L1 θ Seating Plane Gauge Plane Top View View B A A2 Seating Plane A1 View B Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) NOM MAX A 2.45 A1 0.25 - A2 1.95 2.00 2.10 b 0.30 0.45 D 13.65 13.90 14.15 D1 9.80 10.00 10.20 E 13.65 13.90 14.15 E1 9.80 10.00 10.20 e 0.80 BSC L 0.73 0.88 1.03 L1 1.95 REF L2 0.25 BSC θ 3.5O 7 O θ1 5O 16O JEDEC Registration M0-112, Variation AA-2, Issue B, Sep.1995. Doc. #: DSPD-44PQFPPG A031607 Package Outline 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max.), .050in pitch .048/.042 x 45O 6 D D1 1 44 .056/.042 x 45O 40 .150 MAX Note 1 (Index Area) .075 MAX E1 E Note 2 (3 places) 0.20max 3 Places Top View View B Side View b1 A A2 e A1 Base Plane Seating Plane .020 MIN b Side View View B Note: 1. A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Exact shape of this feature is optional. Symbol MIN Dimension (inches) NOM MAX A .165 .172 .180 A1 .090 .105 .120 A2 .062 .083 b .013 .021 b1 .026 .036 D .685 .690 .695 D1 .650 .653 .656 E .685 .690 .695 E1 .650 .653 .656 e .050 BSC JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. Drawings are not to scale. Doc. #: DSPD-44PLCCPJ B051607