RBHV7224DG

HV7224 40-Channel Symmetric Row Driver Ordering Information Device 80-Lead Ceramic Gullwing HV7224DG Package Options 64-Lead 3-Sided Die in waffle pack Plastic Gullwing HV7224PG HV7224X 80-Lead Ceramic Gullwing (MIL-STD-883 Processed*) RBHV7224DG HV7224 * For Hi-Rel process flows, refer to page 5-3 of the Databook. Features ❏ Processed with HVCMOS® technology ❏ Symmetric row drive (reduces latent imaging in ACTFEL displays) ❏ Output voltage up to 240V ❏ Low-power level shifting ❏ Source/Sink current 70mA (min.) ❏ Shift Register Speed 3MHz ❏ Pin-programmable shift direction (DIR, SHIFT) ❏ Hi-Rel processing available General Description The HV72 is a low-voltage serial to high-voltage parallel converters with push-pull outputs. It is especially suitable for use as a symmetric row driver in AC thin-film electroluminescent (ACTFEL) displays. When the data reset pin (DRIO) is at logic high, it will reset all the outputs of the internal shift register to zero. At the same time, the output of the shift register will start shifting a logic high from the least significant bit to the most significant bit. The DRIO can be triggered at any time. The DIR and SHIFT pins control the direction of data shift through the device. When DIR is at logic high, DRIOA is the input and DRIOB is the output. When DIR is grounded, DRIOB is the input and the DRIOA is the output. See the Output Sequence Operation Table for output sequence. The POL and OE pins perform the polarity select and output enable function respectively. Data is loaded on the low to high transition of the clock. A logic high will cause the output to swing to VPP if POL is high, or to GND if POL is low. All outputs will be in HighZ state if OE is at logic high. Data output buffers are provided for cascading devices. Absolute Maximum Ratings Supply voltage, VDD1 Supply voltage, VPP Logic input levels Continuous total power dissipation 2 Plastic Ceramic Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds -0.5V to +7V -0.5V to +260V -0.5V to VDD +0.5V 1200mW 1900mW Plastic -40°C to +85°C Ceramic -55°C to +125°C -65°C to +150°C 260°C Notes: 1. All voltages are referenced to GND. 2. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 19mW/°C for ceramic. 02/96/022 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV7224 Electrical Characteristics (over recommended operating conditions of VDD = 5V, VPP = 240V, and TA = 25°C unless noted) DC Characteristics Symbol IDD IPP IDDQ VOH VOL IIH IIL ISAT VDD supply current High voltage supply current Quiescent VDD supply current High-level output HVOUT Data out Low-level output HVOUT Data out High-level logic input current Low-level logic input current Saturation current HVOUT P-Ch N-Ch Note: 1. Only one output can be turned on at a time. Parameter Min Max 10 2.0 4.0 100 Units mA mA mA µA V V Conditions fCLK = 3MHz Outputs low or High-Z One Output High1 All VIN = GND or VDD IO= -70mA IO= -100µA IO= 70mA IO= 100µA VIH = VDD VIL = 0V 190 4.5 50 0.5 1.0 -1.0 -80 75 V V µA µA mA mA AC Characteristics Symbol fCLK tW (H/L) tSUD tHD tSUC tSUE tHC tHE tDHL tDLH * * Parameter Clock frequency Pulse width - clock high or low Data set-up time before clock rises Data hold time after clock rises HVOUT delay from clock rises (Hi-Z to H or L) HVOUT delay from Output Enable falls HVOUT delay from clock rises (H or L to Hi-Z) HVOUT delay from Output Enable rises Delay time clock to data output falls Delay time clock to data output rises HVOUT fall time HVOUT rise time POL pulse width Output Enable pulse width Slew rate, VPP or GND Min Max 3.0 Units MHz ns ns ns Conditions 150 50 50 1.0 600 2.0 600 250 250 2.0 2.0 3.0 3.0 45 µs ns µs ns ns ns µs µs µs µs V/µs CL = 330pF // RL = 10kΩ CL = 330pF // RL = 10kΩ CL = 330pF // RL = 10kΩ CL = 330pF // RL = 10kΩ CL = 15pF CL = 15pF CL = 330pF // RL = 10kΩ CL = 330pF // RL = 10kΩ tONF tONR tPOW tOEW One active output driving 4.7nF load * The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is equal to tWH. Therefore the delay is measured from the trailing edge of the clock. 2 HV7224 Recommended Operating Conditions Symbol VDD VPP VIH VIL fCLK IO TA IOD Logic supply voltage High voltage supply† Parameter Min 4.5 0 0.7 VDD 0 Max 5.5 240 VDD 0.2VDD 3 ±70 Plastic Ceramic Allowable pulse current through output diode -40 -55 +85 +125 ±300 Units V V V V MHz mA °C °C mA High-level input voltage Low-level input voltage Clock frequency High voltage output current Operating free-air temperature Notes: † Output will not switch at V PP = 0V. Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Input and Output Equivalent Circuits VDD VDD VPP Input Data Out HVOUT GND (Logic) Logic Inputs GND (Logic) Logic Data Output GND (Power) High Voltage Outputs 3 HV7224 Switching Waveforms l/fCLK t WH 50% t SUD 50% t HD Data Valid 50% Data Valid t DLH Data Reset Output (DRIOA/DRIOB) 50% t DHL VOH 50% VOL t SUC HVOUT (POL = H) High Impedance 90% HVOUT (POL = L) 10% t SUC t ONF t HC 10% VOL t ONR 90% 10% High Impedance t HC 90% VIH VIL 50% t WL VIH CLK 50% 50% VIL Data Reset Input (DRIOA/DRIOB) VOH POL 50% t POW VIH 50% VIL t OEW VIH OE 50% 50% VIL t SUE HVOUT 10% High Impedance t ONR 90% t HE 90% VOH High Impedance 90% 10% t SUE t ONF t HE HVOUT 10% VOL 4 HV7224 Functional Block Diagram V PP OE Polarity V DD LT P HVOUT1 D IOA N SHIFT CLK S/R DIR LT HVOUT 2 LT D IOB HVOUT 40 GND LT = Level Translator Function Table I/O Relations CLK O/P HIGH O/P OFF O/P LOW O/P OFF X X X X DIR X X X X Inputs S/R Data H L H X POL H X L X OE L L L H HV Outputs H HIGH-Z L All O/P HIGH-Z Notes: H = logic high level, L = logic low level, X = irrelevant Data input (DRIO) loaded on the low-to-high transistion of the clock. Only one active output can be set at a time. Output Sequence Operation Table DIR L H L H Shift L L H H Data Reset In Data Reset Out DRIOB DRIOA DRIOB DRIOA DRIOA1 DRIOB2 DRIOA1 DRIOB2 HVOUT# Sequence 40 → 1 1 → 40 20 → 1 → 40 → 21 21 → 40 → 1 → 20 Direction* Option (See pin-out on P. 12-158) A A B B * Reference to package outline or chip layout drawing. 1.DRIOA is DRIOBdelayed by 40 clock pulses. 2. DRIOB is DRIOA delayed by 40 clock pulses. 5 HV7224 Pin Configurations HV72 Option A: Pin Function 1 HVOUT1/40 2 HVOUT 2/39 3 HVOUT 3/38 4 HVOUT 4/37 5 HVOUT 5/36 6 HVOUT 6/35 7 HVOUT 7/34 8 HVOUT 8/33 9 HVOUT 9/32 10 HVOUT 10/31 11 HVOUT 11/30 12 HVOUT 12/29 13 HVOUT 13/28 14 HVOUT 14/27 15 HVOUT 15/26 16 HVOUT 16/25 17 HVOUT 17/24 18 HVOUT 18/23 19 HVOUT 19/22 20 HVOUT 20/21 21 VPP 22 N/C 23 GND (Power) 24 GND (Logic) 25 DIR 26 VDD 27 CLK 28 N/C 29 SHIFT 30 N/C 31 DRIOA 32 N/C Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Function N/C DRIOB OE NC POL N/C VDD N/C GND (Logic) GND (Power) N/C VPP HVOUT 21/20 HVOUT 22/19 HVOUT 23/18 HVOUT 24/17 HVOUT 25/16 HVOUT 26/15 HVOUT 27/14 HVOUT 28/13 HVOUT 29/12 HVOUT 30/11 HVOUT 31/10 HVOUT 32/9 HVOUT 33/8 HVOUT 34/7 HVOUT 35/6 HVOUT 36/5 HVOUT 37/4 HVOUT 38/3 HVOUT 39/2 HVOUT 40/1 HV72 Option B: Pin Function 1 HVOUT 20/21 2 HVOUT 19/22 3 HVOUT 18/23 4 HVOUT 17/24 5 HVOUT 16/25 6 HVOUT 15/26 7 HVOUT 14/27 8 HVOUT 13/28 9 HVOUT 12/29 10 HVOUT 11/30 11 HVOUT 10/31 12 HVOUT 9/32 13 HVOUT 8/33 14 HVOUT 7/34 15 HVOUT 6/35 16 HVOUT 5/36 17 HVOUT 4/37 18 HVOUT 3/38 19 HVOUT 2/39 20 HVOUT 1/40 21 VPP 22 N/C 23 GND (Power) 24 GND (Logic) 25 DIR 26 VDD 27 CLK 28 N/C 29 SHIFT 30 N/C 31 DRIOA 32 N/C Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Function N/C DRIOB OE N/C POL N/C VDD N/C GND (Logic) GND (Power) N/C VPP HVOUT 40/1 HVOUT 39/2 HVOUT 38/3 HVOUT 37/4 HVOUT 36/5 HVOUT 35/6 HVOUT 34/7 HVOUT 33/8 HVOUT 32/9 HVOUT 31/10 HVOUT 30/11 HVOUT 29/12 HVOUT 28/13 HVOUT 27/14 HVOUT 26/15 HVOUT 25/16 HVOUT 24/17 HVOUT 23/18 HVOUT 22/19 HVOUT 21/20 Note: Pin designation for DIR H/L, SHIFT = L. Example: For DIR = H, pin 1 is HVOUT1. For DIR = L, pin 1 is HVOUT40. Pins 65–80 are NC (ceramic only). Note: Pin designation for DIR L/H, SHIFT = H. Example: For DIR = L, pin 1 is HVOUT20. For DIR = H, pin 1 is HVOUT21. Pins 65–80 are NC (ceramic only). 6 HV7224 Package Outline 1 Index 64 64 65 41 40 Index 24 25 top view 3-sided Plastic 64-pin Gullwing Package 40 41 80 1 top view 80-pin Ceramic Gullwing Package 24 25 02/06//02 ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com